amd64: Use Intel behavior for 16b sh[lr]d when count>16 #64
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According to the Intel SDM for `shld` and `shrd` instructions, the result is undefined when shift count is greater than operand size. Observed behavior of Intel CPUs in this case is to shift bits in from source first, then from destination. This is also how QEMU models these instructions. Discovered via QEMU differential tests.
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According to the Intel SDM for
shldandshrdinstructions, the result is undefined when shift count is greater than operand size. Observed behavior of Intel CPUs in this case is to shift bits in from source first, then from destination. This is also how QEMU models these instructions. Discovered via QEMU differential tests.Submitted upstream at https://bugs.kde.org/show_bug.cgi?id=492961