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feat(CMSIS): Enable SPIXF cache controller (SFCC) in SystemInit for MAX32572 #930

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Feb 23, 2024
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Original file line number Diff line number Diff line change
Expand Up @@ -122,6 +122,9 @@ __weak void SystemInit(void)
/* Make sure interrupts are enabled. */
__enable_irq();

/* Enable SPIXF cache */
MXC_SFCC_Enable();

/* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
/* Grant full access, per "Table B3-24 CPACR bit assignments". */
/* DDI0403D "ARMv7-M Architecture Reference Manual" */
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