fix(CMSIS): Set CTB clock to max frequency for MAX32572 startup #1087
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Jake-Carter
approved these changes
Aug 1, 2024
sihyung-maxim
pushed a commit
to analogdevicesinc/hal_adi
that referenced
this pull request
Aug 1, 2024
ozersa
pushed a commit
to analogdevicesinc/hal_adi
that referenced
this pull request
Sep 11, 2024
ozersa
pushed a commit
to analogdevicesinc/hal_adi
that referenced
this pull request
Sep 11, 2024
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Description
In the MAX32572, the
GCR_CLKCTRL.cryptoclk_divvalue is set to 1 (not 0 as documented) on reset. This makes the CTB block run at half speed (ISO/2). This PR sets the CTB clock to its max speed (ISO) on startup.Checklist Before Requesting Review