docs: add docs/library/cn0363/* specific IPs

docs/library/cn0363/cn0363_dma_sequencer/index.rst

@@ -0,0 +1,104 @@
+.. _cn0363_dma_sequencer:
+
+CN0363 DMA Sequencer FPGA Peripheral
+================================================================================
+
+.. hdl-component-diagram::
+
+The CN0363 Sequencer FPGA Peripheral is part of the 
+:dokuwiki:`CN0363 HDL project documentation <resources/eval/user-guides/eval-cn0363-pmdz/reference_hdl>` 
+and is responsible to sequence the various data channels to the DMA.
+
+Files
+--------------------------------------------------------------------------------
+
+.. list-table::
+    :header-rows: 1
+
+    * - Name
+      - Description
+    * - :git-hdl:`/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v`
+      - Verilog source for the peripheral.
+    * - :git-hdl:`/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl`
+      - TCL script to generate the Vivado IP-integrator project for the 
+        peripheral.
+
+Signal and Interface Pins
+--------------------------------------------------------------------------------
+
+.. hdl-interfaces::
+
+    * - clk
+      - Clock
+      - All other signals are synchronous to this clock.
+    * - resetn
+      - Synchronous active low reset
+      - Resets the internal state machine of the core.
+    * - phase
+      - AXI-Stream slave
+      - Phase data channel.
+    * - data
+      - AXI-Stream slave
+      - Sample data channel.
+    * - data_filtered
+      - AXI-Stream slave
+      - Filtered sample data channel.
+    * - i_q
+      - AXI-Stream slave
+      - Demodulated I/Q sample data channel.
+    * - i_q_filtered
+      - AXI-Stream slave
+      - Filtered demodulated I/Q sample data channel.
+    * - dma_wr
+      - FIFO Write Interface master
+      - Low-level SPI bus interface that is controlled by peripheral.
+    * - overflow
+      - Output
+      - The overflow signal is asserted if a overflow on the DMA interface is
+        detected.
+    * - channel_enable
+      - Input
+      - Data channel enable sequencer output enable.
+    * - processing_resetn
+      - Output
+      - Reset signal for the processing pipeline
+
+Theory of Operation
+--------------------------------------------------------------------------------
+
+The CN0363 DMA sequencer core acts as a link between the CN0363 processing
+pipeline and the connected DMA controller. On one side it accepts data from the
+processing pipeline and on the other side it sends the data to the DMA
+controller. The core is only active when the DMA controller signals that it is
+waiting for data, when it is inactive it also asserts the ``processing_resetn``
+signal to keep the processing pipeline in reset. Since the DMA is running at a
+much faster clock than the output data rate from the processing pipeline the
+different channels are time-division-multiplexed and send one by one to the DMA
+controller over the ``dma_wr`` interface.
+
+When active the core cycles through the input channels in the following order.
+
+#. phase (Reference channel)
+#. data (Reference channel)
+#. data_filtered (Reference channel)
+#. i_q, I component (Reference channel)
+#. i_q, Q component (Reference channel)
+#. i_q_filtered, I component (Reference channel)
+#. i_q_filtered, Q component (Reference channel)
+#. phase (Sample channel)
+#. data (Sample channel)
+#. data_filtered (Sample channel)
+#. i_q, I component (Sample channel)
+#. i_q, Q component (Sample channel)
+#. i_q_filtered, I component (Sample channel)
+#. i_q_filtered, Q component (Sample channel)
+
+Each of these has a corresponding bit in the ``channel_enable`` and only if the
+bit is set the channel is sent to the ``dma_wr`` interface, otherwise it is
+discarded. This allows an application to select which data channels it wants to
+capture.
+
+More Information
+--------------------------------------------------------------------------------
+
+-  :dokuwiki:`[Wiki] CN0363 HDL project documentation <resources/eval/user-guides/eval-cn0363-pmdz/reference_hdl>`

docs/library/cn0363/cn0363_phase_data_sync/index.rst

@@ -0,0 +1,97 @@
+.. _cn0363_phase_data_sync:
+
+CN0363 Phase Data Sync FPGA Peripheral
+================================================================================
+
+.. hdl-component-diagram::
+
+The CN0363 Phase Data Sync FPGA Peripheral is part of the :ref:`EVAL-CN0363-PMDZ HDL
+reference design <cn0363>` and is responsible for preparing the ADC conversion 
+result data and aligning it with the phase and feeding both to the processing 
+pipeline.
+
+Files
+--------------------------------------------------------------------------------
+
+.. list-table::
+    :header-rows: 1
+
+    * - Name
+      - Description
+    * - :git-hdl:`/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v`
+      - Verilog source for the peripheral.
+    * - :git-hdl:`/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.tcl`
+      - TCL script to generate the Vivado IP-integrator project for the
+        peripheral.
+
+Signal and Interface Pins
+--------------------------------------------------------------------------------
+
+.. hdl-interfaces::
+
+    * - clk
+      - Clock
+      - All other signals are synchronous to this clock.
+    * - resetn
+      - Synchronous active low reset
+      - Resets the internal state machine of the core.
+    * - processing_resetn
+      - Synchronous active low reset
+      - Indicator that the processing pipeline is in reset.
+    * - S_AXIS_SAMPLE
+      - AXI-Stream slave
+      - Input sample data stream
+    * - M_AXIS_SAMPLE
+      - AXI-Stream master
+      - Output sample data stream
+    * - M_AXIS_PHASE
+      - AXI-Stream master
+      - Output phase data stream
+    * - sample_has_stat
+      - Input
+      - Whether the incoming data on ``S_AXIS_SAMPLE`` has the STAT register
+        appended.
+    * - conv_done
+      - Input
+      - Conversion done signal from the ADC.
+    * - phase
+      - Input
+      - Current excitation signal phase.
+    * - overflow
+      - Input
+      - The overflow signal is asserted if a new sample arrives before the
+        previous one has been consumed.
+
+Theory of Operation
+--------------------------------------------------------------------------------
+
+The CN0363 Phase Data Sync FPGA Peripheral takes the raw ADC sample data read by
+a SPI controller from the ADC on the S_AXIS_SAMPLE stream. The data is assembled
+into 24-bit word and converted from offset binary to two's complement signed.
+
+When a rising edge is detected on the ``conv_done signal`` the core takes a 
+snapshot of the phase input signal. This data will be assumed to the phase 
+that belongs to the next incoming data sample on the S_AXIS_SAMPLE. The data 
+is aligned with the corresponding phase data and both are send out on the 
+``M_AXIS_SAMPLE`` and ``M_AXIS_PHASE stream``.
+
+If the ``sample_has_stat`` signal is asserted the core will receive 32-bit 
+instead of 24-bit per sample on the S_AXIS_SAMPLE stream. The last 8-bit are 
+assumed to contain the STAT register of the ADC, which among other things 
+contains the information about which channel the ADC result belongs to. This 
+information can be used to detect and fix channel swaps. If 
+``sample_has_stat`` is not asserted the core assumes that no channel swaps 
+happen and the whole pipeline is always running fast enough to accept a 
+sample before the next one is ready.
+
+If ``processing_resetn`` is asserted the processing pipeline is assumed to be 
+in reset and incapable of accepting new samples and when a new sample arrives at
+the ``S_AXIS_SAMPLE`` port a overflow condition is generated. The signal also 
+resets the channel swap detection logic and makes sure that the next sample that 
+is inserted into the processing pipeline after the reset belongs to the first 
+channel.
+
+More Information
+--------------------------------------------------------------------------------
+
+- :ref:`EVAL-CN0363-PMDZ HDL reference design <cn0363>`

docs/library/cn0363/index.rst

@@ -0,0 +1,13 @@
+.. _cn0363_lib:
+
+CN0363 Specific IPs
+================================================================================
+
+Contents
+--------
+
+.. toctree::
+   :maxdepth: 2
+
+   CN0363 DMA Sequencer <cn0363_dma_sequencer/index>
+   CN0363 Phase Data Sync <cn0363_phase_data_sync/index>

docs/library/index.rst

@@ -81,6 +81,7 @@ Utilities
    axi_pwm_gen/index
    axi_sysid/index
    axi_tdd/index
+   cn0363/index
    common/ad_dds/index
    corundum/index
    util_axis_fifo/index