Add SYCL FPGA support to the job generator

[SimeonEhrig]

No description provided.

[psychocoderHPC]

@SimeonEhrig I saw in the failing CI jobs

The following tests FAILED:
	 12 - parallelLoopPatterns (Timeout)

I merged today #2456 maybe it is required to rebase against the fix

[SimeonEhrig]

@fwyzard Does PR #2456 fix the broken test? If yes, can you please rebase PR #2471 that I can rebase this PR.

[fwyzard]

I've done all the rebasing, let's see how the tests go.

[fwyzard]

Looks like the blockSharedSharingTest test fails with the FPGA backend in debug mode.

[fwyzard]

...we were just in time for intel/llvm#16929 :-/

[SimeonEhrig]

...we were just in time for intel/llvm#16929 :-/

How do we continue? I think it makes no sense anymore to merge the PR, except you still want to do FPGA develop and maybe is it in another way later.

[fwyzard]

I would prefer to merge it and continue the work!
This summer we have a student sponsored by Intel (or Altera) to work on FPGAs.

[SimeonEhrig]

I would prefer to merge it and continue the work!
This summer we have a student sponsored by Intel (or Altera) to work on FPGAs.

Okay. The PR is ready to be reviewed and merged. Your PR should be automatically merged too.