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Testbenches for i2c in #13

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Kreijstal wants to merge 48 commits intoalexforencich:masteralexforencich/verilog-i2c:masterfrom Kreijstal:testbenches_for_i2cKreijstal/I2C:testbenches_for_i2cCopy head branch name to clipboard

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Commits on Jun 28, 2024

• saving

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• Refactored I2C PHY module for improved readability and maintainability.

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• Set default value for phy_busy and update delay register width to 17 bits.

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• creating testbench

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Commits on Jun 29, 2024

• free formatting

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• formatting plus testbench works now

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• compartementalize the test

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• save whatever

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• looks good

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• good progress

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Commits on Jun 30, 2024

• Refactored register assignments and state transitions in i2c_single_reg module.

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• Updated state values to 5 bits in i2c_single_reg module.

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• It now works with verilator

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• some changes

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• making everything a task

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• making everything a task

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• Updated state parameters and added padding bits to the input filters.

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• Added signal declarations and updated signal assignments for I2C slave module.

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• generated blocks work

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• verible format called everywhere

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• verilator bug

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• Fixing issue thanks to verilator

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• formatting using verilog format

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• forgot to format

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• this will fix rst so it is async

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Commits on Jul 2, 2024

• adding write event

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• testbench goes on tb

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• add this from other branch

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• Merge pull request #1 from Kreijstal/last_write_event

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• fixing the test

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• missing comma

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• fix the error of 0 sized int

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Commits on Jul 8, 2024

• changing testbenches, on NACK simply stop.. no need to go further...

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• let's stick to verilog for now

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Commits on Jul 9, 2024

• changing logic a little bit

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• Initialize module registers with default values.

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• Initialized all state, address, data, mode, bit count, and signal registers with default values in i2c_slave module.

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  83d7df9

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• changing testbench

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• fixing bug

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• fix master

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Commits on Jul 12, 2024

• adding parameter debug

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• explicit debug statement

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Commits on Jul 13, 2024

• negative reset

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• make conditionally verbose, otherwise, too verbose!

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• verilog does not support implicit params for synth

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Commits on Jul 15, 2024

• fixing 1 display

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• move from one place to the next

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• format using verilible

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