negative reset

rtl/i2c_master.v

@@ -31,7 +31,7 @@ THE SOFTWARE.
  */
 module i2c_master (
     input wire clk,
-    input wire rst,
+    input wire rst_n,
 
     /*
      * Host interface
@@ -633,7 +633,7 @@ I/O pin.  This would prevent devices from stretching the clock period.
 
   i2c_phy phy_instance (
       .clk(clk),
-      .rst(rst),
+      .rst_n,
       .phy_start_bit(phy_start_bit),
       .phy_stop_bit(phy_stop_bit),
       .phy_write_bit(phy_write_bit),
@@ -654,8 +654,8 @@ I/O pin.  This would prevent devices from stretching the clock period.
   );
 
 
-  always @(posedge clk or posedge rst) begin
-    if (rst) begin
+  always @(posedge clk or negedge rst_n) begin
+    if (~rst_n) begin
       state_reg <= STATE_IDLE;
       s_axis_cmd_ready_reg <= 1'b0;
       s_axis_data_tready_reg <= 1'b0;

rtl/i2c_phy.v

@@ -2,7 +2,7 @@
 `timescale 1ns / 1ps
 module i2c_phy (
     input wire clk,
-    input wire rst,
+    input wire rst_n,
 
     // Control signals
     input wire phy_start_bit,
@@ -315,9 +315,9 @@ module i2c_phy (
   end
 
 
-  always @(posedge clk or posedge rst) begin
+  always @(posedge clk or negedge rst_n) begin
 
-    if (rst) begin
+    if (~rst_n) begin
       phy_rx_data_reg <= 1'b0;
       phy_state_reg <= PHY_STATE_IDLE;
       delay_reg <= 17'd0;

rtl/i2c_phy_tb.sv

@@ -7,7 +7,7 @@ module i2c_phy_tb;
 
   // Signals
   reg clk = 0;
-  reg rst = 0;
+  reg rst = 1;
   reg phy_start_bit = 0;
   reg phy_stop_bit = 0;
   reg phy_write_bit = 0;
@@ -62,7 +62,7 @@ module i2c_phy_tb;
   // Instantiate the i2c_phy module
   i2c_phy uut (
       .clk(clk),
-      .rst(rst),
+      .rst(rst_n),
       .phy_start_bit(phy_start_bit),
       .phy_stop_bit(phy_stop_bit),
       .phy_write_bit(phy_write_bit),
@@ -83,7 +83,7 @@ module i2c_phy_tb;
   );
   task initialize;
     begin
-      rst = 1;
+      rst = 0;
       phy_start_bit = 0;
       phy_stop_bit = 0;
       phy_write_bit = 0;
@@ -95,10 +95,10 @@ module i2c_phy_tb;
 
   task reset;
     begin
-      rst = 1;
-      #(CLK_PERIOD * 5);
       rst = 0;
       #(CLK_PERIOD * 5);
+      rst = 1;
+      #(CLK_PERIOD * 5);
     end
   endtask
   task write_operation(input tx_data);

rtl/i2c_single_reg.v

@@ -37,7 +37,7 @@ module i2c_single_reg #(
     parameter DEBUG = 0
 ) (
     input wire clk,
-    input wire rst,
+    input wire rst_n,
 
     /*
      * I2C interface
@@ -102,8 +102,8 @@ module i2c_single_reg #(
   wire start_bit = sda_negedge && scl_i_reg;
   wire stop_bit = sda_posedge && scl_i_reg;
 
-  always @(posedge clk or negedge rst) begin
-    if (rst) begin
+  always @(posedge clk or negedge rst_n) begin
+    if (~rst_n) begin
       state_reg <= STATE_IDLE;
       sda_o_reg <= 1'b1;
     end else begin

rtl/i2c_slave.v

@@ -33,7 +33,7 @@ module i2c_slave #(
     parameter FILTER_LEN = 4
 ) (
     input wire clk,
-    input wire rst,
+    input wire rst_n,
 
     /*
      * Host interface
@@ -446,8 +446,8 @@ I/O pin.  This would prevent devices from stretching the clock period.
     end
   end
 
-  always @(posedge clk or negedge rst) begin
-    if (rst) begin
+  always @(posedge clk or negedge rst_n) begin
+    if (~rst_n) begin
       state_reg <= STATE_IDLE;
       s_axis_data_tready_reg <= 1'b0;
       m_axis_data_tvalid_reg <= 1'b0;

tb/i2c_master_tb.v

@@ -15,6 +15,8 @@ module i2c_master_tb;
 
   reg clk = 0;
   reg rst = 0;
+  wire rst_n;
+  assign rst_n=~rst;
   reg [7:0] current_test = 0;
 
   // I2C master signals
@@ -92,7 +94,7 @@ module i2c_master_tb;
         .DEBUG(1)
       ) i2c_reg (
           .clk(clk),
-          .rst(rst),
+          .rst_n,
           .scl_i(scl_wire),
           .scl_o(scl_o_3),
           .scl_t(scl_t_3),
@@ -184,7 +186,7 @@ module i2c_master_tb;
           .FILTER_LEN(4)
       ) i2c_slave_inst (
           .clk(clk),
-          .rst(rst),
+          .rst_n,
           .release_bus(release_bus_4),
           .s_axis_data_tdata(s_axis_data_tdata_4),
           .s_axis_data_tvalid(s_axis_data_tvalid_4),