-
THEORY 2: GOOD FLOORPLAN VS BAD FLOORPLAN & INTRODUCTION TO LIBRARY CELLS
-
THEORY 3: DESIGN LIBRARY CELL USING MAGIC LAYOUT AND NGSPICE CHARACTERIZATION
- SPICE DECK CREATION FOR CMOS INVERTER
- INCEPTION OF LAYOUT & CMOS FABRICATION PROCESS
- LAB 3: INTRODUCTION TO MAGIC AND SKY130A
- Introduction to Magic Tools and DRC Rules
- Introduction to SKY130 PDK
- Introduction to Magic & Steps to Load SKY130 Tech Rules
- Lab Exercise to Fix Poly-9 Error in SKY130 Tech File
- Lab Challenge Exercise to Describe DRC Error as Geometrical Construct
- Lab Challenge to Find Missing or Incorrect Rules and Fix Them
-
LAB 4: PRE-LAYOUT TIMING ANALYSIS & IMPORTANCE OF GOOD CLOCK TREE
-
THEORY + LAB 5: FINAL STEPS FOR RTL2GDS USING TRITONROUTE & OPENSTA
The RTL (Register Transfer Level) to GDSII (Graphic Data System II) flow is a comprehensive process in integrated circuit (IC) design that transforms a high-level hardware description into a physical layout ready for fabrication. It begins with RTL design, where the circuit's functionality is coded in hardware description languages like Verilog or VHDL. This RTL code is then synthesized into a gate-level netlist. Design for Test (DFT) features are incorporated to facilitate testing. The netlist undergoes floorplanning, placement, and routing to map the circuit onto the chip layout. Clock Tree Synthesis (CTS) ensures efficient clock distribution. After detailed placement and routing, signoff checks including Design Rule Checking (DRC), Layout Versus Schematic (LVS) checks, and Static Timing Analysis (STA) are performed. Finally, the design is exported as a GDSII file, which is used by semiconductor foundries to fabricate the physical ICs
The image below is an Arduino Microcontroller Board. Our focus is on the encircled area, which contains the 'Microprocessor.
We will be designing this microprocessor from the abstract level to the fabrication level using the RTL to GDS flow.
let us Understand about some IC Design Components and Terminologies
| Component | Description |
|---|---|
| Core | The core is the section of the chip where the fundamental logic pf the design is placed. |
| IO Pads | IO pads serve as the communication channels between the core and the external environment. |
| Die | The die is the part of the chip that includes both the core and IO pads. It is the area that is implemented on silicon wafer |
| IPs | Foundry IPs require manual design or human intervention to create, such as components ADC, DAC, PLLs and may more. |
Here is the OpenLANE Detailed ASIC Design Flow:
Open the LINUX Terminal (By default we are in home directory)
- Important LINUX Commands
- cd : It is used to change the current working directory.
- ls : It lists the contents of a directory.
- ls -ltr : It lists the contents of a directory in long format, sorted by modification time in reverse order (oldest first).
- ls --help: It displays a help message with a list of options and usage information for the "ls" command. Note : You can give any command name and then type "--help" to get info about that command.
- clear: It clears the terminal screen.
Now, we go to the work directory where all files related to the workshop are stored
cd Desktop
cd work/tools/
we wil be working with 'openlane_working_dir' --> 'openlane' so use :
cd openlane_working_dir/
cd openlane/
- Important Files and Directories
pdks: It is known as Process Design Kit. For this workshop we are using an opensource pdk i.e 'skywater 130nm pdk'. OPENLANE is built around this 'skywater 130nm pdk'. - skywater-pdk : This has all the pdk related files such as timing libraries, Lef files etc. - open_pdks : It contains set of scripts & files that converts the foundary level pdks to be compatible with the open source EDA Tools. - sky130A : It is a pdk variant , already made compatible with the open source EDA tools. - libs.ref: It contains files specific to the technology such as design libraries, standard cells and many more. - libs.tech: It contains files specific to the Tools.
To enter into bash while being in the openalne dircetory use the command
docker
Now after this we use the script 'flow.tcl' and alongwith it use '-interactive' for the step by step openlane flow. here is the command:
./flow.tcl -interactive
.
Now, OPENLANE is opened, and we input the required packages using the following command:
% package require openlane 0.9
Now, Ther are various pre-built designs in the 'designs' subdirectory. So, here we are selecting the "picorv32a.v" design on which we will execute the RTL to GDS flow. To carry out the synthesis (the project's initial stage) on this design, we first need to set it up using the command:
prep -design picorv32a
After the preparation is complete, we can see a new directory with todays date is created within 'runs' folder in 'picorv32a' folder.
Now, when we open the newly created directory:
At first, every directory will be empty since no operations have been performed on the design. However, there will be a directory named "tmp" that contains various types of files. One of these files is "merged.lef" which includes information about metal layer levels and cell levels. use the follwoing command to open "merged.lef":
less merged.lef
- "config.tcl" File: This file shows which all default parameter is taken by the run.
To open the file use the following command:
less config.tcl
Now, coming back to the step where design preperation was completed successfully. Now, To perform synthesis on the design use the following command :
% run_synthesis
It will take some time to get completed.
- Extras: Watch these videos
Now, First objective after the synthesis is completed is to calculate the Flip Flop Ratio.
Now, if we see the synthesized results we find:
Number of D Flipflops : 1613
Total number of Cells : 14876
Hence, flip flop ratio = (Number of D Flipflops)/(Total number of Cells) Flipflop percentage = FF ratio * 100
FF Ratio : 0.1084
FF Percentage : 10.84 %
Also, Now if we go to:
/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/11-07_06-37/results/synthesis$
we have the synthesis results stored here now.
In order to calculate the utilization factor & aspect ratio, first we need to calculate the height and width of the core and die.
The core area's dimensions will be determined by the design's netlist, which is based on the number of components necessary to implement
the logic. Consequently, the die area's height and width will depend on the core area's dimensions.
For example, lets consider a netlist that is having two logic gates and two flipflops.
Now, if we consider the elements each having area of 1 sq.unit. The netlist contains 4 elements and the minimum total area required for the
core area will be 4 sq.units.
- Utilization Factor: The Utilization Factor is defined as the ratio of the core area occupied by the netlist to the total core area. In an effective floorplan, the Utilization Factor should not be 1. If the Utilization Factor reaches 1, there will be no available space for adding any additional logic, making it a poor floorplan.
Utilization Factor = (Area occupied by netlist / Total core area)
- Aspect Ratio: The Aspect Ratio is defined as the ratio of the height of the core to its width. When the Aspect Ratio is 1, the core is considered to be square-shaped. If the Aspect Ratio is different from 1, the core will have a rectangular shape.
Aspect Ratio = (Height of the core / Width of the core)
So, for the above case:
Utilisation Factor = (4 sq units)/(4sq units) = 1
Aspect Ratio = (2 units)/(2 units) = 1 i.e core has Square Shape
Now, if we take the another case given below:
Utilisation Factor = (4 sq units)/(8 sq units) = 0.5
Aspect Ratio = (2 units)/(4 units) = 0.5 i.e core has Rectangular Shape
The concept of preplaced cells begins with organizing a complex combinational logic circuit, which may contain thousands of gates, into predefined locations within the layout. This involves identifying and positioning critical components or blocks, such as memory modules, clock gating cells, comparators, and multiplexers. These preplaced cells are treated as distinct entities or "black boxes" to streamline integration and management. The arrangement of these preplaced cells and other IPs within the design layout is known as floorplanning. These IP`s / blocks have user defined locations and hence are placed in chip before automated placement- and-routing and are called pre-placed cells. Automated Plcement and routing tools places the remaining logical cells in the design onto the chip.
In circuits, certain high-power components may not receive adequate power from the source due to voltage drops in the connecting wires, causing their operation to fall outside their required voltage range for reliable switching. To address this issue, decoupling capacitors (De-cap cells) are strategically placed near these power-intensive components. These capacitors are connected to the power source and charge to a high level when no switching occurs. When switching activities commence, the decoupling capacitors quickly discharge to supply the necessary power directly to these components. Once switching ceases, the capacitors recharge, ensuring consistent and reliable power delivery to critical circuit components. This mechanism is essential in circuit design to maintain stable operation and prevent performance issues caused by fluctuating power supply conditions.
In the previous section, we discussed using decoupling capacitors (De-cap cells) to manage power distribution for various blocks. However, De-cap cells come with limitations, such as leakage power and increased chip area. To mitigate these issues, we use a technique called power planning. In areas of the chip with significant switching activity, two phenomena can occur: voltage drop and ground bounce.
Voltage Drop
Voltage drop happens when a group of cells switch from 0 to 1 simultaneously, causing a high demand for power. If the power is supplied from a single source, there may be insufficient power, leading to a drop in input voltage at that location. This issue becomes problematic when the voltage level falls below the noise margin.
Ground Bounce Ground bounce occurs when a group of cells switch from 1 to 0 simultaneously, dumping power to the ground pin at the same time. This causes the ground voltage to rise briefly instead of remaining at 0, leading to a phenomenon known as ground bounce. The issue arises when the voltage level exceeds the noise margin.
Power Planning Technique
To prevent these issues, a technique called power planning is used. This involves creating two separate power meshes: one for Vdd (positive voltage) and another for ground. These meshes are typically implemented using the top two metal layers to minimize voltage drops. They are spread across the design and connected to multiple Vdd and ground sources. With this approach, when a cell requires power to switch from 0 to 1, it draws from the nearest Vdd layer. Conversely, when a cell needs to drain power, it discharges to the nearest ground layer. This ensures stable and efficient power distribution throughout the chip.
In a netlist, each component has a distinct shape— for example, an AND gate has one shape while an OR gate has another. However, in a library, all components are represented by a uniform square or rectangular shape. A library contains a variety of elements that are ready to use, each with specified properties such as area and delay. Additionally, there are different versions of the same component, each with varying properties.
In the image above, we have three different sets of the same elements. The larger elements are faster but take up more space, while the smaller elements occupy less area but operate more slowly compared to the larger ones.
In the placement stage, it is crucial to take into account the estimated wire length when positioning cells. Wire length estimation involves calculating the distances from the input sources of cells to the output sinks they drive.
In the example above, the tool positions the blocks based on these estimated wire lengths, as illustrated in the figure below.
-
Standard Cells: These are basic logic gates (like NAND, NOR, XOR, etc.) or more complex functional blocks (like flip-flops or adders) designed to be reusable across different IC designs. They are characterized by their functionality, area, power consumption, and timing characteristics.
-
Library: In the context of IC design, a library (or cell library) consists of a collection of standard cells. Each cell in the library is optimized for specific parameters such as speed (delay), power consumption, area (size), and drive strength.
- A typical Cell Design Flow Involves the follwoing steps as shown below:
-
Propogation Dealy:
Let us take example wavefrom and calculate the Propogation Delay:
But Here a problem can occur if the thresholds move and results may vary:
So choosing a threshold point carefully is very important. -
Transition Time
To ensure a smooth floorplanning process, designers must pay attention to certain parameters, known as switches, which can significantly impact the floorplan when adjusted. For instance, the utilization factor and aspect ratio are among these critical switches. Designers need to verify that these parameters align with the project requirements before initiating the floorplanning stage. The image below illustrates various types of switches involved in the floorplanning phase.
- Now, after the synthesis is completed, To run the Floorplan Use the following command:
run_floorplan
When the floorplaning is completed, To view the results go to the path as shown in image below :
open the def file:
These results are useful for various analysis, for example: we can see the die area :
Now, to open this "def" file in magic , use the following command:
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def
Now, we can use 'Magic' tool to expllore the floorplan.
| Task | Steps |
|---|---|
| Centering the Design | 1. Press S to select the entire design.2. Press V to align it vertically to the middle of the screen. |
| Zooming In on a Specific Area | 1. Left-click and drag to highlight the desired region. 2. Right-click to open the context menu. 3. Press Z to zoom in on the selected area. |
| Retrieving Cell Details | 1. Hover your cursor over the cell you want details for. 2. Press S to select the cell.3. In the tkcon window, type the command what to display the cell's details. |
After successfully completing floorplanning, the design process moves on to the placement stage, which comprises two main phases:
Global Placement: During this phase, the tool determines the approximate locations for all the standard cells in the design. Detailed Placement: In this phase, the tool finalizes the exact positions for all the standard cells and ensures the placement is legal. Legalization involves verifying that no standard cells overlap and that they are all correctly positioned within the designated site rows. To initiate the placement process, use the following command:
run_placement
After the Placement is done. To view the results Go to the following loacation:
/home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/20-07_16-44/results/placement
And then we can see 'picorv32a.placement.def' file. To open it using MAGIC use the follwoing command:
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def
Spice deck basically Netlist having the connectivity information, Input to be provided, Output Tap points and much more.
Proceeding with an example:
- Nodes are required to define the netlist.
MOSFET (ORDER FOR NETLIST) : Drain Gate Substrate Source Syntax for MOSFET In a Netlist: e.g : M1 out in vdd vdd pmos W = 0.375u L = 0.25u
CMOS circuit is a very Robust device, seee the below image:
| Characteristic | Description |
|---|---|
| Switching Threshold (Vth) | The voltage level at which the inverter switches from a high state (logic 1) to a low state (logic 0). |
| Input Low Voltage (Vil) | The highest input voltage that is recognized as logic 0. |
| Input High Voltage (Vih) | The lowest input voltage that is recognized as logic 1. |
| Output Low Voltage (Vol) | The output voltage level when the inverter transitions from high to low. |
| Output High Voltage (Voh) | The output voltage level when the inverter transitions from low to high. |
| Noise Margins | The voltage ranges that define the low noise margin (between Vil and Vol) and the high noise margin (between Vih and Voh). |
| Characteristic | Description |
|---|---|
| Propagation Delays | The time delay for the output to respond to a change in the input signal. |
| Rise Time (tr) | The duration for the output to shift from Vol to Voh. |
| Fall Time (tf) | The duration for the output to shift from Voh to Vol. |
- Example : TO CHANEG THE IO PLACER SETTINGS
First let us verify the current configuration of the Pins, Go to following directory as shown in image below:
Then use the command to open the 'def' file in magic:
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def
As we can seee Pins are randomly equidistant :
Now, if want it to change to some other IO strategy, as there are four strategy supported by IO placer(Open source EDA tool)
To do this, first go the following directory and open 'floorplan.tcl' file:
:~/Desktop/work/tools/openlane_working_dir/openlane/configuration$
And from here we can see the switching variable :
set ::env(FP_IO_MODE) 1; # 0 matching mode - 1 random equidistant mode
It is set as 1 and hence pins are randomly equidistant. Now, go the follwoing tab as shown below and put the following command and change the IO placer settings:
set ::env(FP_IO_MODE) 2
run_floorplan
Hence, we run the floorplan again
Now, we can check the chaneg in the IO placer strategy:
We can see that def file has been updated from the time stamps and date:
Now, let us open it in magic using the earlier used command:
And from the above image we can see teh configuration has been changed.
- Go to Openlane directory and use the following command:
For example here:
git clone <url of the github repo you want to clone>git clone https://github.com/nickson-jose/vsdstdcelldesign.git
From the above image we can see it is cloned successfully.
Now, we will open the 'mag' file and in order to do that we require 'tech'file taht is present in the following directory:
so first we copy that file here, by using the following command:vsduser@vsdsquadron:~/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic$cp sky130A.tech /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign
It is copied successfully.
Now, open the mag file magic:
magic -T sky130A.tech sky130_inv.mag &
When polysilicon crosses the ndiffusion region it is termed as 'NMOS' and when it crosses the pdiffusion region it is termed as 'PMOS', same is verified in image below:
follow this Repository: Click here
In the tckon window, use the following command:
% extract all
% ext2spice cthresh 0 rthresh 0
Now, lets open the created spice file:
This contains the spice deck.
Make the follwoing cahnges in the 'sky130_inv.spice' file:
Now to run the simulation in ngspice, use the follwoing command while being in the 'vsdstdcelldesign' directory:
ngspice sky130_inv.spice
Now, to open the plot use plot y vs time a in ngspice terminal
To characterize the inverter, we analyzed the ngspice plot and determined the following parameters:
-
Rise Time: The time for the output waveform to transition from 20% to 80% of its maximum value.
From plot points: (x0 = 2.18197e-09, y0 = 0.660482) to (x0 = 2.24571e-09, y0 = 2.64019). Calculated Rise Time = 0.0637 ns
-
Fall Time: The time for the output waveform to transition from 80% to 20% of its maximum value.
From plot points: (x0 = 4.0526e-09, y0 = 2.63973) to (x0 = 4.09512e-09, y0 = 0.659245). Calculated Fall Time = 0.0425 ns
-
Propagation Delay(Cell Rise Delay) The time for the output to transition 50% in response to a 50% change at the input.
From plot points: Input(x0 = 2.15018e-09, y0 = 1.65018) to Output(x0 = 2.21088e-09, y0 = 1.65). Calculated Propagation Delay = 0.060 ns
-
Cell Fall Delay: The delay for the output to transition 50% due to a 50% change at the input.
From plot points: (x0 = 4.04991e-09, y0 = 1.65) to (x0 = 4.07745e-09, y0 = 1.65). Calculated Cell Fall Delay = 0.0275 ns
With these parameters successfully characterized, the next step is to create a LEF file.
Follow this Webpage for Documentation Now us the follwoing command to download the Lab files while being in the home directory :
sudo wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tgz
Now you have downloaded the zip file. To extract the labs from the zip file use the command
sudo tar xfz drc_tests.tgz
In the downloaded files , .magicrc file serves as the start-up script for MAGIC.
"Run the command magic -d XR to open the Magic tool."
Let us start by opening met3.mag file in magic
| Step | Instructions |
|---|---|
| Select an Area and Fill with Metal 3 | 1. Open the Magic GUI. 2. Select the desired area on your layout. 3. Navigate to the metal 3 layer. 4. Press P to fill the selected region with metal 3. |
| Create the VIA2 Mask | 1. Open the tkcon terminal within Magic. 2. Type the command: cif see VIA2.3. The metal 3-filled area will now be associated with the VIA2 mask. |
use 'feed clear' to go back to previous view
Load 'poly.mag' file in magic
Verify the spacing between the poly resistor and the poly in the layout and compare it with the specified value on the Skywater website. The image below highlights the spacing error between them. Let's proceed to correct it.
Open the Sky130a.tech file located in the drc_tests directory. Search for the poly.9 keyword and apply the changes shown in the images below. Save the file after making the modifications.
Reload the tech file using the command tech load sky130A.tech, and recheck the design rule checks (DRC) by executing drc check in the tkcon terminal.
Now load nwell.mag file into the magic and check for violations.
In the above layout we have some violations, Open tech file and make changes as shown:
After updating the tech file, use the following commands:
tech load sky130A.tech
drc check
drc style drc(full)
Now, we can see as we apply the contact the errors are removed.
At every level , each node is driving the same load, hence there is no skew, if there would be a case with different loads then there will be skew.
- Setup Timing Analysis
- Hold Timing Analysis
Purpose:
In physical design, it is essential to convert grid information, such as rows and columns, into track information. Tracks are predefined horizontal and vertical paths on each metal layer.
Considerations:
When designing standard cells, consider the following:
Case 1: Input and output ports should align with the intersections of vertical and horizontal tracks. Case 2: The standard cell's width should be an odd multiple of the horizontal track pitch, and its height should be an odd multiple of the vertical track pitch.
LEF File Extraction:
To continue, we need the LEF (Library Exchange Format) file for the Inverter cell. Extract this file from the current Inverter cell to provide essential information for the place-and-route (PNR) process.
Understanding Tracks:
Open the tracks.info file to learn more about the horizontal and vertical tracks available on each metal layer. This file specifies pitch, spacing, and other relevant details necessary for efficient routing.
-
Command to open the custom Inverter Layout in Magic, first go to the 'vsdstdcelldesign' dircetory and then use:
magic -T sky130A.tech sky130_inv.mag &
-
Open the tracks.info file to know more about tracks:
# Fisrt go to the following directory : /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd # open the tracks.info file less tracks.info
-
To set grids as tracks of locali layer, use the follwoing command:
grid 0.46um 0.34um 0.23um 0.17um
Now, we can see in the below image , that the Case 1 consideration is met i.e. Input and output ports are aligned with the intersections of vertical and horizontal tracks.
Now, we can see in the below image , that the Case 2 consideration are also met as 3 boxes are covered between the boundariesi.e. The standard cell's width should be an odd multiple of the horizontal track pitch, and its height should be an odd multiple of the vertica track pitch.
- How to convert labels to ports [No need to do it here as it is already done]:
*Follow this Github Repository For more deatils: * Click here Now, setting up the ports type:
Now we need to extract the LEF file. First save .mag file by using the command ``save sky130_vsdinv.mag``` in the tkcon terminal.
Now, use the follwoing command to open the saved mag file:
magic -T sky130A.tch sky130_vsdinv.mag &
Now, us the follwoing command in tckon window:
# To extract the Lef file use the command: lef write
Now, open the file less sky130_vsdinv.lef
Now, first copy the files in src directory, us ethe following command:
cp sky130_vsdinv.lef /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src
Now, basic idea is to include our custom cell in picorv32a openlane design flow
Also, copy the follwoing files shown in image below in src directory, us the following command:
cp sky130_fd_sc_hd__* /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src
Now, we need to modify the config.tcl file:
Go to picorv32a dircetory and open the file using vimvim config.tclmake the following modifications:
Now, invoke the docker:
Now, do the regular steps as shown:./flow.tcl -interactive package require openlane 0.9 #to continue the work in already made directory in runs folder prep -design picorv32a -tag 12-07_11-26 -overwriteThis will continue our work in '12-07_11-26' and '-overwrite' will continue the work with the chanegs we made and overwrite them.
Now run synthesis run_synthesis
From the figure above, it is evident that the synthesis was successful, with a total of 1554 instances of our vsdinverter. Therefore, this stage has been completed successfully.
From the above figure we can see the worst slack is -23.89 and total negative slack is -711.59. - How to convert labels to ports [No need to do it here as it is already done]:
As we have completed the synthesis stage now we complete the floorplan using the following command:
init_floorplan
place_io
tap_decap_or
Now, as floorplan stage is completed , we run placement
run_placement
Now, lets check whether the cell that we have created has been included in the design or not. Go to the follwoing directory :
/home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/20-07_16-44/results/placement
use :
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &
we cans ee that the cell is successfully placed in the deisgn.
now let us check its alignment is correct or not use command 'expand' in 'tckon' window.
Next stage is to perform STA on the design:
First create 'pre_sta.conf' file in the openlane directory as shiown below:
set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
read_liberty -max /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/sky130_fd_sc_hd__slow.lib
read_liberty -min /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/sky130_fd_sc_hd__fast.lib
read_verilog /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/24-03_10-03/results/synthesis/picorv32a.synthesis.v
link_design picorv32a
read_sdc /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/my_base.sdc
report_checks -path_delay min_max -fields {slew trans net cap input_pins}
report_tns
report_wns
and then create 'my_base.sdc' file in the /picorv32a/src directory as shown below:
set ::env(CLOCK_PORT) clk
set ::env(CLOCK_PERIOD) 24.73
set ::env(SYNTH_DRIVING_CELL) sky130_fd_sc_hd__inv_8
set ::env(SYNTH_DRIVING_CELL_PIN) Y
set ::env(SYNTH_CAP_LOAD) 17.653
set ::env(IO_PCT) 0.2
set ::env(SYNTH_MAX_FANOUT) 6
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
puts "\[INFO\]: Setting input delay to: $input_delay_value"
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) /1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
set_load $cap_load [all_outputs]
Now use the command:
sta pre_sta.conf
As we can see that Slack is equal to of that we got in synthesis stage. So STA is succesful.
To update the previous design with the improved version, use the command:
write_verilog //path of the previous design//
#In our case:
write_verilog /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/20-07_16-44/results/synthesis/picorv32a.synthesis.v
This will replace the old design with the optimized one. Once the update is complete, proceed with the Floorplan stage using the same commands as before.
init_floorplan
place_io
tap_decap_or
Upon successful completion of the Floorplan, proceed to the placement step by running the command:
run_placement
as we can see from the below images file has been overwritten
Now after the placement has been completed, we go for CTS:
run_cts
In cts stage buffers get added , modifying the netlist. After completion of the cts we can observe that in the synthesis results directory a new .cts file is added. The newly added CTS file contains both the previous netlist and also the clock buffers that were added during the cts stage.
use the below given command to enter into openRoad:
openroad
In openroad, We will first create the database (creted from lef and def files) and in the timing analysis this db is used. Run the follwoing commands:
read_lef /openLANE_flow/designs/picorv32a/runs/20-07_16-44/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/20-07_16-44/results/cts/picorv32a.cts.def
write_db pico_cts.db
read_db pico_cts.db
read_verilog /openLANE_flow/designs/picorv32a/runs/20-07_16-44/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
report_checks -path_delay min_max -format full_clock_expanded -digits 4
First use ```exit`` to exit from openroad, now you will come to openlane: Now follow these steps: To check the current value of CTS_CLK_BUFFER_LIST
echo $::env(CTS_CLK_BUFFER_LIST)
To remove sky130_fd_sc_hd__clkbuf_1 from the list
set ::env(CTS_CLK_BUFFER_LIST) [lreplace $::env(CTS_CLK_BUFFER_LIST) 0 0]
Now, To check we run the cts agian run_cts
Now, it will failed or in hung state then kill this task
To check the current value of CURRENT_DEF
echo $::env(CURRENT_DEF)
To set def as placement def
set ::env(CURRENT_DEF) /openLANE_flow/designs/picorv32a/runs/12-07_11-26/results/placement/picorv32a.placement.def
To check the current value of CTS_CLK_BUFFER_LIST
echo $::env(CTS_CLK_BUFFER_LIST)
Now run_cts again.
Now, We need to follow the similar steps that we have followed earlier in the openroad. go to openroad again and then:
read_lef /openLANE_flow/designs/picorv32a/runs/12-07_11-26/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/12-07_11-26/results/cts/picorv32a.cts.def
write_db pico_cts1.db
read_db pico_cts1.db
read_verilog /openLANE_flow/designs/picorv32a/runs/12-07_11-26/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4
The setup slack has improved if we use clock_buf_2 now. But there is a tradeoff with the area.
report_clock_skew -hold
report_clock_skew -setup
Exit the openroad first. To check the current value of CTS_CLK_BUFFER_LIST
echo $::env(CTS_CLK_BUFFER_LIST)
To insert sky130_fd_sc_hd__clkbuf_1 from the list
set ::env(CTS_CLK_BUFFER_LIST) [linsert $::env(CTS_CLK_BUFFER_LIST) 0 sky130_fd_sc_hd__clkbuf_1]
- Note: How to know which stage was done previously in the flow?
- We can see it by seeing the def, current def got updated to cts in the previous stage when cts was completed.
use the folllwoing command to check it:
echo $::env(CURRENT_DEF)
-
Maze Routing
Routing grid is build with standard dimensions
Algorithm utilises this routing grod to find the best route between the source and the target.
There are various routes possible, but routes with less band s are preferred (preferable single band).
There are other algorithms too in its replacement as it is more time consuming.
-
While doing routing , DRC Rules need to be followed.
As the CST stage is compelted, now we need to lay down the Power Distribution Network.
Use the folloeing command gen_pdn.
Now, from the above image we can see PDN is successfully generated.
Now, can see that the pitch of the standard cell rails is 2.720, which we have expected.
In the figure above, we can see how power is distributed to the standard cells. Surrounding the design are I/O pads, with the red and blue blocks representing power pads. The red pads supply power, while the blue ones provide the ground connection. These pads connect to power and ground rings that encircle the design, supplying power to straps. The vertical lines seen for the rings are known as power straps. Connections from the power straps and rings extend to the power rails, with standard cells positioned between these rails. The height of the standard cells must be multiples of the rail pitch to ensure proper power and ground supply.
Now, we can see def has been modifoed from cts to pdn.
Now the last stage in the design is Routing , us ethe following command:
run_routing
The routing has been completed with zero violations, but there is a negative slack, we need to eleiminate the engaticve slack for successful completion of the Physical Design Flow.
See the Readme File in configuration directory:
- Commands to view and change parameters to improve timing and run synthesis:
| Step | Command | Description |
|---|---|---|
| 1 | prep -design picorv32a -tag 24-03_10-03 -overwrite |
Prepare the design for updating variables |
| 2 | set lefs [glob $::env(DESIGN_DIR)/src/*.lef] |
Include newly added LEF files in the OpenLane flow |
| 3 | add_lefs -src $lefs |
Merge the LEF files |
| 4 | echo $::env(SYNTH_STRATEGY) |
Display the current value of the SYNTH_STRATEGY variable |
| 5 | set ::env(SYNTH_STRATEGY) "DELAY 3" |
Set a new value for the SYNTH_STRATEGY variable |
| 6 | echo $::env(SYNTH_BUFFERING) |
Check if SYNTH_BUFFERING is enabled by displaying its current value |
| 7 | echo $::env(SYNTH_SIZING) |
Display the current value of the SYNTH_SIZING variable |
| 8 | set ::env(SYNTH_SIZING) 1 |
Set a new value for the SYNTH_SIZING variable |
| 9 | echo $::env(SYNTH_DRIVING_CELL) |
Check the current value of SYNTH_DRIVING_CELL to ensure it's the correct cell |
| 10 | run_synthesis |
Run the synthesis process after the design is prepared |
And runnning the flow again:
Hence, we successfully got our result with 0 violations and Slack is also met.
To view the final layout, use the following command:
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/22-07_15-00/tmp/merged.lef def read /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/22-07_15-00/results/routing/picorv32a.def &
- To view the Parsitic Extraction file, Go to the follwoing directory:
Also verilog files were modified after certain stages, see here:
This project has utilized resources and materials from the following sources:
- VSD Standard Cell Design
- Google Skywater PDK
- Materials provided in the NASSCOM VSD SoC Design Program