ESP32 Family: Add multiple transctions to SPI for improved efficency

[gamblor21]

While doing some other work with my Saleae, I noticed large SPI transfers had a gap every 4Kb for about 300 microseconds. Over larger transfers this delay adds up and becomes more apparent the faster the SPI frequency as the delay is constant vs frequency.

This PR adds multiple transaction queuing. The current implementation sends 1 transaction at a time. In the linked IDF example it shows how to include multiple transactions. This basically eliminates the delay (it drops to 14 microseconds).

The only downside I have found is you go from one SPI transaction in memory to 10, each transaction is 34 bytes so not a large increase.

For example:
At 80Mhz for a 100 KB transfer the ideal transfer time is 10 milliseconds. The current 300 microsecond delay every 4KB results in a total delay of ~7.2 milliseconds resulting in a total time of 17.2 milliseconds. Almost double the expected time.
At 10Mhz for a 100KB transfer the ideal transfer time is 80 milliseconds. The added 7.2 milliseconds delay for 100KB results in 87.2 milliseconds, almost 10% more then expected.

The most obvious example of the speedup having a positive effect will be in SPI graphic displays (including displayio), But any large SPI transfer will see a speedup, and the faster the frequency the more apparent.

The current transaction buffer size of 10 was arbitrarily chosen.

[tannewt]

Looks good! Thank you!