adafruit · tannewt · May 26, 2022 · May 25, 2022 · May 25, 2022 · May 25, 2022
diff --git a/ports/stm/Makefile b/ports/stm/Makefile
@@ -302,11 +302,11 @@ $(BUILD)/firmware.hex: $(BUILD)/firmware.elf
 
 $(BUILD)/firmware.uf2: $(BUILD)/firmware.hex
 	$(ECHO) "Create $@"
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f 0x57755a57 -b $(BOOTLOADER_OFFSET) -c -o "$(BUILD)/firmware.uf2" $^
+	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b $(BOOTLOADER_OFFSET) -c -o "$(BUILD)/firmware.uf2" $^
 
 flash: $(BUILD)/firmware.bin
 	$(ECHO) "Writing $< to the board"
-	dfu-util -a 0 --dfuse-address 0x08000000 -D $(BUILD)/firmware.bin
+	dfu-util -a 0 --dfuse-address $(BOOTLOADER_OFFSET) -D $(BUILD)/firmware.bin
 
 include $(TOP)/py/mkrules.mk
 

diff --git a/ports/stm/boards/STM32L4R5_boot.ld b/ports/stm/boards/STM32L4R5_boot.ld
@@ -8,7 +8,7 @@ MEMORY
     FLASH (rx)          : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */
     FLASH_ISR (rx)      : ORIGIN = 0x08010000, LENGTH = 4K /* ISR vector. Kind of wasteful. */
     FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 1024K-128K-64K-4K  /* For now, limit to 1MB so that bank switching is still possible. */
-    FLASH_FS (rw)       : ORIGIN = 0x080e0000, LENGTH = 128K
+    FLASH_FS (rw)       : ORIGIN = 0x08100000, LENGTH = 1024K
     RAM (xrw)           : ORIGIN = 0x20000000, LENGTH = 640K
 }
 

diff --git a/ports/stm/boards/STM32L4R5_default.ld b/ports/stm/boards/STM32L4R5_default.ld
@@ -8,7 +8,7 @@ MEMORY
     FLASH (rx)          : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */
     FLASH_ISR (rx)      : ORIGIN = 0x08000000, LENGTH = 4K /* ISR vector. Kind of wasteful. */
     FLASH_FIRMWARE (rx) : ORIGIN = 0x08001000, LENGTH = 1024K-128K-4K  /* For now, limit to 1MB so that bank switching is still possible. */
-    FLASH_FS (rw)       : ORIGIN = 0x080e0000, LENGTH = 128K
+    FLASH_FS (rw)       : ORIGIN = 0x08100000, LENGTH = 1024K
     RAM (xrw)           : ORIGIN = 0x20000000, LENGTH = 640K
 }
 

diff --git a/ports/stm/boards/swan_r5/board.c b/ports/stm/boards/swan_r5/board.c
@@ -33,14 +33,19 @@
 void initialize_discharge_pin(void) {
     /* Initialize the 3V3 discharge to be OFF and the output power to be ON */
     __HAL_RCC_GPIOE_CLK_ENABLE();
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+
     GPIO_InitTypeDef GPIO_InitStruct;
-    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+    /* Set the DISCHARGE pin and the USB_DETECT pin to FLOAT */
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
     GPIO_InitStruct.Pin = GPIO_PIN_6;
-    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
-    HAL_GPIO_WritePin(GPIOE, GPIO_PIN_6, GPIO_PIN_SET);
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); /* PE6 DISCHRG */
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); /* PC6 is USB_DETECT */
+
+    /* Turn on the 3V3 regulator */
     GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
     GPIO_InitStruct.Pin = GPIO_PIN_4;
     HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
     HAL_GPIO_WritePin(GPIOE, GPIO_PIN_4, GPIO_PIN_SET);
@@ -53,14 +58,26 @@ void board_init(void) {
     //  Set tick interrupt priority, default HAL value is intentionally invalid
     //  Without this, USB does not function.
     HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL);
+
+    initialize_discharge_pin();
+
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    GPIO_InitTypeDef GPIO_InitStruct;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+    HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, GPIO_PIN_SET);
+    HAL_Delay(50);
+    HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, GPIO_PIN_RESET);
 }
 
 bool board_requests_safe_mode(void) {
     return false;
 }
 
 void reset_board(void) {
-    initialize_discharge_pin();
 }
 
 void board_deinit(void) {

diff --git a/ports/stm/boards/swan_r5/mpconfigboard.mk b/ports/stm/boards/swan_r5/mpconfigboard.mk
@@ -14,6 +14,7 @@ LD_DEFAULT = boards/STM32L4R5_default.ld
 # UF2 boot option
 LD_BOOT = boards/STM32L4R5_boot.ld
 UF2_OFFSET = 0x8010000
+UF2_BOOTLOADER ?= 1
 
 # Turn all of the below off while trying to get the thing to run
 # These modules are implemented in ports/<port>/common-hal:

diff --git a/ports/stm/boards/swan_r5/pins.c b/ports/stm/boards/swan_r5/pins.c
@@ -1,49 +1,131 @@
 #include "py/objtuple.h"
 #include "shared-bindings/board/__init__.h"
 
+// extended pins
+STATIC const mp_rom_map_elem_t board_module_carrier_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PD09) },
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PD08) },
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) },
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PE03) },
+
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PD01) },
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_CS), MP_ROM_PTR(&pin_PD00) },
+
+    { MP_ROM_QSTR(MP_QSTR_RTS), MP_ROM_PTR(&pin_PG12) },
+    { MP_ROM_QSTR(MP_QSTR_CTS), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_RX0), MP_ROM_PTR(&pin_PG08) },
+    { MP_ROM_QSTR(MP_QSTR_TX0), MP_ROM_PTR(&pin_PG07) },
+
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PE01) },
+
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_SCL3), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_SDA3), MP_ROM_PTR(&pin_PC09) },
+
+    { MP_ROM_QSTR(MP_QSTR_RX2), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_RTS2), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_CTS2), MP_ROM_PTR(&pin_PD03) },
+    { MP_ROM_QSTR(MP_QSTR_TX3), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_RX3), MP_ROM_PTR(&pin_PB11) },
+    { MP_ROM_QSTR(MP_QSTR_RTS3), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_CTS3), MP_ROM_PTR(&pin_PB13) },
+
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) },
+    { MP_ROM_QSTR(MP_QSTR_SCL2), MP_ROM_PTR(&pin_PF01) },
+    { MP_ROM_QSTR(MP_QSTR_SDA2), MP_ROM_PTR(&pin_PF00) },
+
+    { MP_ROM_QSTR(MP_QSTR_QEN), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_QCS), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_QCLK), MP_ROM_PTR(&pin_PE10) },
+
+    { MP_ROM_QSTR(MP_QSTR_EN), MP_ROM_PTR(&pin_PE04) },
+    { MP_ROM_QSTR(MP_QSTR_TX2), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) },
+    { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) },
+    { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) },
+
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_QIO3), MP_ROM_PTR(&pin_PE15) },
+    { MP_ROM_QSTR(MP_QSTR_QIO2), MP_ROM_PTR(&pin_PE14) },
+    { MP_ROM_QSTR(MP_QSTR_QIO1), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_QIO0), MP_ROM_PTR(&pin_PE12) },
+
+};
+
+MP_DEFINE_CONST_DICT(board_module_carrier, board_module_carrier_table);
+
+const mp_obj_type_t carrier_type = {
+    { &mp_type_type },
+    .name = MP_QSTR_Ext,
+    .locals_dict = (mp_obj_dict_t *)&board_module_carrier,
+};
+
+
 // Core Feather Pins
 STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
     CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
 
+    { MP_ROM_QSTR(MP_QSTR_ext), MP_ROM_PTR(&carrier_type) },
+
     { MP_ROM_QSTR(MP_QSTR_ENABLE_3V3), MP_ROM_PTR(&pin_PE04) },
     { MP_ROM_QSTR(MP_QSTR_DISCHARGE_3V3), MP_ROM_PTR(&pin_PE06) },
     { MP_ROM_QSTR(MP_QSTR_DISABLE_DISCHARGING), MP_ROM_TRUE },
     { MP_ROM_QSTR(MP_QSTR_ENABLE_DISCHARGING), MP_ROM_FALSE },
 
-    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) },
-    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
-    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
-    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC01) },
-    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC04) },
-    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) },     // PWM, ADC
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },     // PWM, ADC
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },     // ADC
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC01) },     // ADC
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC04) },     // ADC
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PC05) },     // ADC
+
     { MP_ROM_QSTR(MP_QSTR_VOLTAGE_MONITOR), MP_ROM_PTR(&pin_PA00) },
     { MP_ROM_QSTR(MP_QSTR_BUTTON_USR), MP_ROM_PTR(&pin_PC13) },
     { MP_ROM_QSTR(MP_QSTR_SWITCH), MP_ROM_PTR(&pin_PE04) },
-    { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_PB02) }, // boot button, but looks like it's wired to GND on the schematic
+    { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_PB02) },
 
-    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) },
-    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) },
-    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) },
-    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA04) },    // DAC1 output also
-    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },
-    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) },     // PWM
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) },     // PWM
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) },     // PWM
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA04) },    // ADC, DAC1 output also
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },    // ADC, PWM
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },    // ADC, PWM
 
     { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PE02) },
-    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },   // DAC1 output also
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },   // ADC, PWM, DAC2 output also
 
-    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) },
-    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) },    // PWM
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) },    // PWM
 
     { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) },   // D10
     { MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) },   // D13
 
     { MP_ROM_QSTR(MP_QSTR_SS), MP_ROM_PTR(&pin_PD00) },
     { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PD01) },
-    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB14) },
-    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB14) },   // PWM?
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB15) },   // PWM?
 
-    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA09) },
-    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA09) },     // ADC, PWM
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA10) },     // PWM
 
     { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
     { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },

diff --git a/ports/stm/mpconfigport.mk b/ports/stm/mpconfigport.mk
@@ -8,6 +8,7 @@ ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F405xx STM32F407xx))
         CIRCUITPY_SDIOIO ?= 1
         # Number of USB endpoint pairs.
         USB_NUM_ENDPOINT_PAIRS = 4
+        UF2_FAMILY_ID ?= 0x6d0922fa
 endif
 
 ifeq ($(MCU_SERIES),F4)
@@ -25,6 +26,7 @@ ifeq ($(MCU_SERIES),F4)
         CIRCUITPY_ROTARYIO ?= 0
         CIRCUITPY_RTC ?= 0
         USB_NUM_ENDPOINT_PAIRS = 4
+        UF2_FAMILY_ID ?= 0x57755a57
 endif
 
 ifeq ($(MCU_SERIES),H7)
@@ -43,6 +45,7 @@ ifeq ($(MCU_SERIES),H7)
         CIRCUITPY_RTC ?= 0
 
         USB_NUM_ENDPOINT_PAIRS = 9
+        UF2_FAMILY_ID ?= 0x6db66082
 endif
 
 ifeq ($(MCU_SERIES),F7)
@@ -59,6 +62,7 @@ ifeq ($(MCU_SERIES),F7)
         CIRCUITPY_RTC ?= 0
 
         USB_NUM_ENDPOINT_PAIRS = 6
+        UF2_FAMILY_ID ?= 0x53b80f00
 endif
 
 ifeq ($(MCU_SERIES),L4)
@@ -77,6 +81,7 @@ ifeq ($(MCU_SERIES),L4)
         # This slide deck https://www.st.com/content/ccc/resource/training/technical/product_training/98/89/c8/6c/3e/e9/49/79/STM32L4_Peripheral_USB.pdf/files/STM32L4_Peripheral_USB.pdf/jcr:content/translations/en.STM32L4_Peripheral_USB.pdf
         # cites 16 endpoints, 8 endpoint pairs, while section 3.39 of the L4R5 datasheet states 6 endpoint pairs.
         USB_NUM_ENDPOINT_PAIRS = 6
+        UF2_FAMILY_ID ?= 0x00ff6919
 endif
 
 CIRCUITPY_PARALLELDISPLAY := 0
diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c
@@ -95,12 +95,8 @@ STATIC const flash_layout_t flash_layout[] = {
 STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4)));
 
 #elif defined(STM32L4)
-// todo - the L4 devices can have different flash sizes and different page sizes
-// depending upon the dual bank configuration
-// This is hardcoded for the Swan R5. When support for other devices is needed more conditionals will be required
-// to differentiate.
 STATIC const flash_layout_t flash_layout[] = {
-    { 0x08000000, 0x1000, 256 },
+    { 0x08100000, 0x1000, 256 },
 };
 STATIC uint8_t _flash_cache[0x1000] __attribute__((aligned(4)));
 
@@ -174,6 +170,9 @@ uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *si
 }
 
 void supervisor_flash_init(void) {
+    #ifdef STM32L4
+    // todo - check that the device is in dual bank mode
+    #endif
 }
 
 uint32_t supervisor_flash_get_block_size(void) {
@@ -202,7 +201,7 @@ void port_internal_flash_flush(void) {
     FLASH_EraseInitTypeDef EraseInitStruct = {};
     #if CPY_STM32L4
     EraseInitStruct.TypeErase = TYPEERASE_PAGES;
-    EraseInitStruct.Banks = FLASH_BANK_1;
+    EraseInitStruct.Banks = FLASH_BANK_2;       // filesystem stored in upper 1MB of flash in dual bank mode
     #else
     EraseInitStruct.TypeErase = TYPEERASE_SECTORS;
     EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V

diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h
@@ -97,9 +97,9 @@
 #endif
 
 #ifdef STM32L4R5xx
-#define STM32_FLASH_SIZE 0x100000 // 1MB    // for now just use the first bank
-#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x20000 // 128KiB
-#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x080e0000
+#define STM32_FLASH_SIZE 0x200000 // 2MB
+#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x100000 // 1024KiB
+#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08100000
 #endif
 
 #define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE)