Merge 7.1 fixes back into main

.github/workflows/build.yml

@@ -35,7 +35,7 @@ jobs:
       with:
         python-version: 3.8
     - name: Get CP deps
-      run: python tools/ci_fetch_deps.py test ${{ github.ref }}
+      run: python tools/ci_fetch_deps.py test ${{ github.sha }}
     - name: CircuitPython version
       run: |
         git describe --dirty --tags || git log --parents HEAD~4..
@@ -141,7 +141,7 @@ jobs:
       with:
         python-version: 3.8
     - name: Get CP deps
-      run: python tools/ci_fetch_deps.py mpy-cross-mac ${{ github.ref }}
+      run: python tools/ci_fetch_deps.py mpy-cross-mac ${{ github.sha }}
     - name: CircuitPython version
       run: |
         git describe --dirty --tags
@@ -197,7 +197,7 @@ jobs:
         submodules: false
         fetch-depth: 1
     - name: Get CP deps
-      run: python tools/ci_fetch_deps.py docs ${{ github.ref }}
+      run: python tools/ci_fetch_deps.py docs ${{ github.sha }}
     - name: CircuitPython version
       run: |
         git describe --dirty --tags
@@ -269,7 +269,7 @@ jobs:
         submodules: false
         fetch-depth: 1
     - name: Get CP deps
-      run: python tools/ci_fetch_deps.py ${{ matrix.board }} ${{ github.ref }}
+      run: python tools/ci_fetch_deps.py ${{ matrix.board }} ${{ github.sha }}
     - name: Install dependencies
       run: |
         sudo apt-get install -y gettext
@@ -321,7 +321,7 @@ jobs:
         submodules: false
         fetch-depth: 1
     - name: Get CP deps
-      run: python tools/ci_fetch_deps.py ${{ matrix.board }} ${{ github.ref }}
+      run: python tools/ci_fetch_deps.py ${{ matrix.board }} ${{ github.sha }}
     - name: Install dependencies
       run: |
         sudo apt-get install -y gettext
@@ -373,7 +373,7 @@ jobs:
         submodules: false
         fetch-depth: 1
     - name: Get CP deps
-      run: python tools/ci_fetch_deps.py ${{ matrix.board }} ${{ github.ref }}
+      run: python tools/ci_fetch_deps.py ${{ matrix.board }} ${{ github.sha }}
     - name: CircuitPython version
       run: git describe --dirty --tags
     - uses: actions/cache@v2
@@ -460,7 +460,7 @@ jobs:
         submodules: false
         fetch-depth: 1
     - name: Get CP deps
-      run: python tools/ci_fetch_deps.py ${{ matrix.board }} ${{ github.ref }}
+      run: python tools/ci_fetch_deps.py ${{ matrix.board }} ${{ github.sha }}
     - name: Install dependencies
       run: |
         sudo apt-get install -y gettext mtools

.github/workflows/create_website_pr.yml

@@ -25,7 +25,7 @@ jobs:
       with:
         python-version: 3.8
     - name: Get CP deps
-      run: python tools/ci_fetch_deps.py website ${{ github.ref }}
+      run: python tools/ci_fetch_deps.py website ${{ github.sha }}
     - name: Install deps
       run: |
         pip install -r requirements-dev.txt

.github/workflows/ports_windows.yml

@@ -70,7 +70,7 @@ jobs:
         submodules: false
         fetch-depth: 1
     - name: Get CP deps
-      run: python tools/ci_fetch_deps.py windows ${{ github.ref }}
+      run: python tools/ci_fetch_deps.py windows ${{ github.sha }}
     - name: CircuitPython version
       run: |
         git describe --dirty --tags

devices/ble_hci/common-hal/_bleio/__init__.c

@@ -107,6 +107,6 @@ void common_hal_bleio_gc_collect(void) {
 }
 
 
-void bleio_background(void) {
+void bleio_hci_background(void) {
     bleio_adapter_background(&common_hal_bleio_adapter_obj);
 }

devices/ble_hci/common-hal/_bleio/__init__.h

@@ -34,7 +34,7 @@
 #include "att.h"
 #include "hci.h"
 
-void bleio_background(void);
+void bleio_hci_background(void);
 void bleio_reset(void);
 
 typedef struct {

ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c

@@ -54,12 +54,33 @@
 #endif
 
 static frequencyio_frequencyin_obj_t *active_frequencyins[TC_INST_NUM];
-volatile uint8_t reference_tc = 0xff;
+volatile uint8_t reference_tc;
 #ifdef SAM_D5X_E5X
 static uint8_t dpll_gclk;
+
+#if !BOARD_HAS_CRYSTAL
+static uint8_t osculp32k_gclk;
+#endif
+
 #endif
 
-void frequencyin_emergency_cancel_capture(uint8_t index) {
+void frequencyin_reset(void) {
+    for (uint8_t i = 0; i < TC_INST_NUM; i++) {
+        active_frequencyins[i] = NULL;
+    }
+
+    reference_tc = 0xff;
+    #ifdef SAM_D5X_E5X
+    dpll_gclk = 0xff;
+
+    #if !BOARD_HAS_CRYSTAL
+    osculp32k_gclk = 0xff;
+    #endif
+
+    #endif
+}
+
+static void frequencyin_emergency_cancel_capture(uint8_t index) {
     frequencyio_frequencyin_obj_t* self = active_frequencyins[index];
 
     NVIC_DisableIRQ(self->TC_IRQ);
@@ -93,7 +114,7 @@ void frequencyin_interrupt_handler(uint8_t index) {
 
     uint64_t current_ns = common_hal_time_monotonic_ns();
 
-    for (uint8_t i = 0; i <= (TC_INST_NUM - 1); i++) {
+    for (uint8_t i = 0; i < TC_INST_NUM; i++) {
         if (active_frequencyins[i] != NULL) {
             frequencyio_frequencyin_obj_t* self = active_frequencyins[i];
             Tc* tc = tc_insts[self->tc_index];
@@ -143,7 +164,7 @@ void frequencyin_interrupt_handler(uint8_t index) {
     ref_tc->COUNT16.INTFLAG.reg |= TC_INTFLAG_OVF;
 }
 
-void frequencyin_reference_tc_init() {
+static void frequencyin_reference_tc_init(void) {
     if (reference_tc == 0xff) {
         return;
     }
@@ -154,9 +175,6 @@ void frequencyin_reference_tc_init() {
     // use the DPLL we setup so that the reference_tc and freqin_tc(s)
     // are using the same clock frequency.
     #ifdef SAM_D5X_E5X
-    if (dpll_gclk == 0xff) {
-        frequencyin_samd51_start_dpll();
-    }
     set_timer_handler(true, reference_tc, TC_HANDLER_FREQUENCYIN);
     turn_on_clocks(true, reference_tc, dpll_gclk);
     #endif
@@ -178,15 +196,15 @@ void frequencyin_reference_tc_init() {
     #endif
 }
 
-bool frequencyin_reference_tc_enabled() {
+static bool frequencyin_reference_tc_enabled(void) {
     if (reference_tc == 0xff) {
         return false;
     }
     Tc *tc = tc_insts[reference_tc];
     return tc->COUNT16.CTRLA.bit.ENABLE;
 }
 
-void frequencyin_reference_tc_enable(bool enable) {
+static void frequencyin_reference_tc_enable(bool enable) {
     if (reference_tc == 0xff) {
         return;
     }
@@ -195,56 +213,69 @@ void frequencyin_reference_tc_enable(bool enable) {
 }
 
 #ifdef SAM_D5X_E5X
-void frequencyin_samd51_start_dpll() {
+static bool frequencyin_samd51_start_dpll(void) {
     if (clock_get_enabled(0, GCLK_SOURCE_DPLL1)) {
-        return;
+        return true;
     }
 
-    uint8_t free_gclk = find_free_gclk(1);
-    if (free_gclk == 0xff) {
-        dpll_gclk = 0xff;
-        return;
+    dpll_gclk = find_free_gclk(1);
+    if (dpll_gclk == 0xff) {
+        return false;
     }
 
-    GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(free_gclk);
     // TC4-7 can only have a max of 100MHz source
     // DPLL1 frequency equation with [X]OSC32K as source: 98.304MHz = 32768(2999 + 1 + 0/32)
     // Will also enable the Lock Bypass due to low-frequency sources causing DPLL unlocks
     // as outlined in the Errata (1.12.1)
     OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(2999);
+
 #if BOARD_HAS_CRYSTAL
-    // we can use XOSC32K directly as the source
-    OSC32KCTRL->XOSC32K.bit.EN32K = 1;
-    OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(1) | OSCCTRL_DPLLCTRLB_LBYPASS;
+    // we can use XOSC32K directly as the source. It has already been initialized in clocks.c
+    OSCCTRL->Dpll[1].DPLLCTRLB.reg =
+        OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val) | OSCCTRL_DPLLCTRLB_LBYPASS;
 #else
-    // can't use OSCULP32K directly; need to setup a GCLK as a reference,
-    // which must be done in samd/clocks.c to avoid waiting for sync
-    return;
-    //OSC32KCTRL->OSCULP32K.bit.EN32K = 1;
-    //OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(0);
+    // We can't use OSCULP32K directly. Set up a GCLK controlled by it
+    // Then use that GCLK as the reference oscillator for the DPLL.
+    osculp32k_gclk = find_free_gclk(1);
+    if (osculp32k_gclk == 0xff) {
+        return false;
+    }
+    enable_clock_generator(osculp32k_gclk, GCLK_GENCTRL_SRC_OSCULP32K_Val, 1);
+    GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(OSCCTRL_GCLK_ID_FDPLL1);
+    OSCCTRL->Dpll[1].DPLLCTRLB.reg =
+        OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val) | OSCCTRL_DPLLCTRLB_LBYPASS;
 #endif
-    OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
 
+    OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
     while (!(OSCCTRL->Dpll[1].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY)) {}
-    enable_clock_generator(free_gclk, GCLK_GENCTRL_SRC_DPLL1_Val, 1);
-    dpll_gclk = free_gclk;
+
+    enable_clock_generator(dpll_gclk, GCLK_GENCTRL_SRC_DPLL1_Val, 1);
+    return true;
 }
 
-void frequencyin_samd51_stop_dpll() {
+static void frequencyin_samd51_stop_dpll(void) {
     if (!clock_get_enabled(0, GCLK_SOURCE_DPLL1)) {
         return;
     }
 
-    disable_clock_generator(dpll_gclk);
+    if (dpll_gclk != 0xff) {
+        disable_clock_generator(dpll_gclk);
+        dpll_gclk = 0xff;
+    }
+
+    #if !BOARD_HAS_CRYSTAL
+    if (osculp32k_gclk != 0xff) {
+        disable_clock_generator(osculp32k_gclk);
+        osculp32k_gclk = 0xff;
+    }
+    #endif
 
     GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = 0;
     OSCCTRL->Dpll[1].DPLLCTRLA.reg = 0;
     OSCCTRL->Dpll[1].DPLLRATIO.reg = 0;
     OSCCTRL->Dpll[1].DPLLCTRLB.reg = 0;
-
     while (OSCCTRL->Dpll[1].DPLLSYNCBUSY.bit.ENABLE) {
     }
-    dpll_gclk = 0xff;
 }
 #endif
 
@@ -421,7 +452,7 @@ void common_hal_frequencyio_frequencyin_deinit(frequencyio_frequencyin_obj_t* se
     self->pin = NO_PIN;
 
     bool check_active = false;
-    for (uint8_t i = 0; i <= (TC_INST_NUM - 1); i++) {
+    for (uint8_t i = 0; i < TC_INST_NUM; i++) {
         if (active_frequencyins[i] != NULL) {
             check_active = true;
         }

ports/atmel-samd/common-hal/frequencyio/FrequencyIn.h

@@ -46,14 +46,7 @@ typedef struct {
 } frequencyio_frequencyin_obj_t;
 
 void frequencyin_interrupt_handler(uint8_t index);
-void frequencyin_emergency_cancel_capture(uint8_t index);
-void frequencyin_reference_tc_init(void);
-void frequencyin_reference_tc_enable(bool enable);
-bool frequencyin_reference_tc_enabled(void);
-#ifdef SAM_D5X_E5X
-void frequencyin_samd51_start_dpll(void);
-void frequencyin_samd51_stop_dpll(void);
-#endif
+void frequencyin_reset(void);
 
 
 #endif // MICROPY_INCLUDED_ATMEL_SAMD_COMMON_HAL_FREQUENCYIO_FREQUENCYIN_H

ports/atmel-samd/supervisor/port.c

@@ -71,6 +71,10 @@
 #include "common-hal/busio/__init__.h"
 #endif
 
+#if CIRCUITPY_FREQUENCYIO
+#include "common-hal/frequencyio/FrequencyIn.h"
+#endif
+
 #include "common-hal/microcontroller/Pin.h"
 
 #if CIRCUITPY_PULSEIO
@@ -388,6 +392,10 @@ void reset_port(void) {
     i2sout_reset();
     #endif
 
+    #if CIRCUITPY_FREQUENCYIO
+    frequencyin_reset();
+    #endif
+
     #if CIRCUITPY_TOUCHIO && CIRCUITPY_TOUCHIO_USE_NATIVE
     touchin_reset();
     #endif
@@ -399,7 +407,7 @@ void reset_port(void) {
     #if CIRCUITPY_PWMIO
     pwmout_reset();
     #endif
-    #if CIRCUITPY_PWMIO || CIRCUITPY_AUDIOIO
+    #if CIRCUITPY_PWMIO || CIRCUITPY_AUDIOIO || CIRCUITPY_FREQUENCYIO
     reset_timers();
     #endif
 

ports/broadcom/qstrdefsport.h

@@ -26,6 +26,9 @@
 
 // qstrs specific to this port, only needed if they aren't auto-generated
 
+// Prevent uncrustify from modifying these lines.
+// *FORMAT-OFF*
+
 // Entries for sys.path
 Q(/sd)
 Q(/sd/lib)

ports/espressif/boards/adafruit_feather_esp32s2_tft/board.c

@@ -86,7 +86,7 @@ void board_init(void) {
 
     common_hal_busio_spi_never_reset(spi);
 
-    displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus;
+    displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus;
     bus->base.type = &displayio_fourwire_type;
 
     common_hal_displayio_fourwire_construct(
@@ -99,7 +99,7 @@ void board_init(void) {
         0,              // polarity
         0               // phase
         );
-    displayio_display_obj_t* display = &displays[0].display;
+    displayio_display_obj_t *display = &displays[0].display;
     display->base.type = &displayio_display_type;
 
     // workaround as board_init() is called before reset_port() in main.c

ports/raspberrypi/common-hal/audiopwmio/PWMAudioOut.c

@@ -207,7 +207,7 @@ void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t *self,
     uint32_t tx_register = (uint32_t)&pwm_hw->slice[self->left_pwm.slice].cc;
     if (self->stereo) {
         // Shift the destination if we are outputting to both PWM channels.
-        tx_register += self->left_pwm.channel * sizeof(uint16_t);
+        tx_register += self->left_pwm.ab_channel * sizeof(uint16_t);
     }
 
     self->pacing_timer = pacing_timer;

ports/raspberrypi/common-hal/busio/I2C.c

@@ -109,8 +109,11 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self,
     // set up as GPIO by the bitbangio.I2C object.
     //
     // Sets pins to open drain, high, and input.
+    //
+    // Do not use the default supplied clock stretching timeout here.
+    // It is too short for some devices. Use the busio timeout instead.
     shared_module_bitbangio_i2c_construct(&self->bitbangio_i2c, scl, sda,
-        frequency, timeout);
+        frequency, BUS_TIMEOUT_US);
 
     self->baudrate = i2c_init(self->peripheral, frequency);