fix some cases of hdlname being added to objects with private names

YosysHQ · Jan 15, 2025 · d640157 · d640157
1 parent 17d4579
commit d640157
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Showing 2 changed files with 10 additions and 1 deletion.
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
@@ -1464,7 +1464,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		log("Importing module %s.\n", RTLIL::id2cstr(module->name));
 	}
 	import_attributes(module->attributes, nl, nl);
-	module->set_string_attribute(ID::hdlname, nl->CellBaseName());
+	if (module->name.isPublic())
+		module->set_string_attribute(ID::hdlname, nl->CellBaseName());
 	module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
 #ifdef VERIFIC_VHDL_SUPPORT
 	if (nl->IsFromVhdl()) {

diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
@@ -377,6 +377,10 @@ static void extract_fsm(RTLIL::Wire *wire)
 	fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
 	fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
 	fsm_cell->attributes = wire->attributes;
+	if(fsm_cell->attributes.count(ID::hdlname)) {
+		fsm_cell->attributes[ID(scopename)] = fsm_cell->attributes[ID::hdlname];
+		fsm_cell->attributes.erase(ID::hdlname);
+	}
 	fsm_data.copy_to_cell(fsm_cell);
 
 	// rename original state wire
@@ -385,6 +389,10 @@ static void extract_fsm(RTLIL::Wire *wire)
 	wire->attributes.erase(ID::fsm_encoding);
 	wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
 	module->wires_[wire->name] = wire;
+	if(wire->attributes.count(ID::hdlname)) {
+		wire->attributes[ID(scopename)] = wire->attributes[ID::hdlname];
+		wire->attributes.erase(ID::hdlname);
+	}
 
 	// unconnect control outputs from old drivers