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Implement a simple 5 stage RISC-V Non pipelined architecture and test it. For now let's settle on the RV32I Base ISA.
- State Machine;
- Instruction Fetch;
- Instruction Decode;
- Execute Stage;
- Memory Access;
- Write back;
Instruction memory will consist of a ROM BRAM (Read only memory Block RAM), for the time being with a width of 32 bits (instruction size, RISC-V like) and a depth of 4096 instructions. The block memory is defined as a single port ROM, that's because we are only interested in reading the hardcoded RISC-V instructions inside of it. The BRAM will have an enable pin and a synchronous reset pin (will only work when memory is enabled). The IP will have an embedded output register where the Instruction to be decoded is saved before the instruction decode stage. The input address is 32 bit wide to ease RISC-V jump instructions. For this time the load_en for the instruction memory will be hard-wired to "1".
Register File is made of a DRAM (Distributed Memory), with two ports, defined with a width of 32 bits (RISC-V Registers size) and 32 words deep (RISC-V ISA defines 32 registers for the register file). For now the output is registered.
Made of 4096 words of 32 bits. Address is 12 bits. write_en generated by control state machine. It will be implemented as a single port RAM as BRAM.
- Clock is now set at 50 MHz, let's try if it works.
For now I am going to implement a small subset of the RV32I ISA. This is a comprehensive list:
| Instruction | Decoded? | Implemented in ALU? |
|---|---|---|
| ADD | Yes | Yes |
| SUB | Yes | Yes |
| JAL | Yes | Yes |
| BEQ | Yes | Yes |
| BNE | Yes | Yes |
| BLT | Yes | Yes |
| BGE | Yes | Yes |
| LW | Yes | Yes |
| SW | Yes | Yes |
| ADDI | Yes | Yes |
| XORI | Yes | Yes |
| ORI | Yes | Yes |
| ANDI | Yes | Yes |
| XOR | Yes | Yes |
| OR | Yes | Yes |
| AND | Yes | Yes |
The entire instruction fetch stage is executed in one clock cycle. Here is the flow of operations:
- If LOAD_EN is active, incoming PC from upper stages is loaded into the PC register (beware, this happens 1 clock cycle before the start of the instruction fetch)
- Rising edge of the clock arrives
- BRAM Instruction Memory fetches instruction reading PC if LOAD_EN_MEM is active. A synchronous RST may reset the Instruction Memory
- In the meantime PC + 4 is computed and saved in NPC (Next Program Counter)
- BRAM will save Instruction in internal IR (instruction register) before the arrival of the next clock pulse
