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Apply FPGA changes to fix AMDS counters #411

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merged 2 commits into from
Aug 20, 2024
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codecubepi
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Resolves:

See the issue conversation for full issue history.

Major Changes:

  • Only trigger AMDS interface if enabled
  • Split timeout counters into byte timeouts and data timeouts
  • Rewrite some logic for generating waiting_for_first_fe and trigger_to_fe_timer

Minor Changes

  • Rename nets in FPGA for clarity

Only trigger AMDS interface if enabled
Split timeout counters into byte timeouts and data timeouts
Rewrite some logic for generating waiting_for_first_fe and trigger_to_fe_timer
@codecubepi codecubepi added bug Something isn't working fpga Involves the FPGA Verilog code. driver Involves the drivers which interface between C firmware and hardware. labels Aug 15, 2024
@codecubepi codecubepi self-assigned this Aug 15, 2024
@codecubepi codecubepi linked an issue Aug 15, 2024 that may be closed by this pull request
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@npetersen2 npetersen2 left a comment

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Overall, looks really good! One question inline to resolve.

sdk/app_cpu1/common/drv/amds.c Outdated Show resolved Hide resolved
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Excellent work

@codecubepi codecubepi merged commit 146936c into v1.3-staging Aug 20, 2024
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@codecubepi codecubepi deleted the amds-timeout#393 branch August 20, 2024 19:05
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Successfully merging this pull request may close these issues.

New AMDS Interface not timing out correctly
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