Fix sensor enable/disable issue (#410)

* Redo sched_isr logic generation to fix sensor enable/disable bug

* Fix typo in comment

* Add new defines in user config for overriding scheduler tolerance

* Address PR feedback, single define

* Flip scheduler tolerance from negative to positive

ip_repo/amdc_timing_manager_1.0/README.md

@@ -77,6 +77,7 @@ This IP is accessed via the AXI4-Lite register-based interface from the DSP. Thi
 | -- | -- | -- |
 | 0 | RESET_SCHED_ISR | Clears the hardware interrupt once it has been recieved by the processing system |
 | 1 | SCHED_SOURCE_MODE | Determines the source of the interrupt for the scheduler: legacy mode or timing manager-synchronized |
+| 31 | SCHED_ISR | (READ-ONLY) The scheduler ISR interrupt signal directly from the timing manager, made available for debugging |
 
 ### ISR_TIME
 

ip_repo/amdc_timing_manager_1.0/component.xml

@@ -288,7 +288,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>22a43c4b</spirit:value>
+            <spirit:value>acf7e706</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -304,7 +304,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>22a43c4b</spirit:value>
+            <spirit:value>acf7e706</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1176,8 +1176,8 @@
         <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
       </xilinx:taxonomies>
       <xilinx:displayName>amdc_timing_manager_v1.0</xilinx:displayName>
-      <xilinx:coreRevision>46</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-06-19T20:23:24Z</xilinx:coreCreationDateTime>
+      <xilinx:coreRevision>47</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2024-08-05T18:33:28Z</xilinx:coreCreationDateTime>
       <xilinx:tags>
         <xilinx:tag xilinx:name="ui.data.coregen.dd@657e33ab_ARCHIVE_LOCATION">c:/Users/atolson3/Documents/AMDC/AMDC-Firmware/ip_repo/amdc_timing_manager_1.0</xilinx:tag>
         <xilinx:tag xilinx:name="ui.data.coregen.dd@20b81b5c_ARCHIVE_LOCATION">c:/Users/atolson3/Documents/AMDC/AMDC-Firmware/ip_repo/amdc_timing_manager_1.0</xilinx:tag>
@@ -1784,13 +1784,18 @@
         <xilinx:tag xilinx:name="ui.data.coregen.dd@3cf2ca94_ARCHIVE_LOCATION">s:/School/WEMPEC/firmware-e/ip_repo/amdc_timing_manager_1.0</xilinx:tag>
         <xilinx:tag xilinx:name="ui.data.coregen.dd@423ac97f_ARCHIVE_LOCATION">s:/School/WEMPEC/firmware-e/ip_repo/amdc_timing_manager_1.0</xilinx:tag>
         <xilinx:tag xilinx:name="ui.data.coregen.dd@561ddb05_ARCHIVE_LOCATION">s:/School/WEMPEC/firmware-e/ip_repo/amdc_timing_manager_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@525182b5_ARCHIVE_LOCATION">s:/School/WEMPEC/firmware-amds/ip_repo/amdc_timing_manager_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@52b49438_ARCHIVE_LOCATION">s:/School/WEMPEC/firmware-amds/ip_repo/amdc_timing_manager_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@7563d5a3_ARCHIVE_LOCATION">s:/School/WEMPEC/firmware-amds/ip_repo/amdc_timing_manager_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@bd97fe7_ARCHIVE_LOCATION">s:/School/WEMPEC/firmware-amds/ip_repo/amdc_timing_manager_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@28a02058_ARCHIVE_LOCATION">s:/School/WEMPEC/firmware-amds/ip_repo/amdc_timing_manager_1.0</xilinx:tag>
       </xilinx:tags>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
       <xilinx:xilinxVersion>2019.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="4b7306e2"/>
       <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ed1368d5"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5a78d643"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="19ce77a4"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="19e46283"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e7b50784"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="af80574e"/>

ip_repo/amdc_timing_manager_1.0/hdl/amdc_timing_manager_v1_0_S00_AXI.v

@@ -530,7 +530,7 @@
             4'h2   : reg_data_out <= sensor_done_status; // Sensor Done Status
             4'h3   : reg_data_out <= slv_reg3; // User Ratio
             4'h4   : reg_data_out <= slv_reg4; // PWM Sync
-            4'h5   : reg_data_out <= slv_reg5;  // ISR
+            4'h5   : reg_data_out <= {sched_isr,slv_reg5[30:0]};  // ISR - MSb is sched_isr from TM for debug
             4'h6   : reg_data_out <= sched_tick_time; // Trigger timer
             4'h7   : reg_data_out <= adc_enc_time_reg; // ADC & Encoder Times
             4'h8   : reg_data_out <= amds_01_time_reg; // AMDS Times

ip_repo/amdc_timing_manager_1.0/src/timing_manager.v

@@ -196,19 +196,15 @@ module timing_manager(
     //          acquisition/conversion cycle (e.g. on the rising edge
     //          of the all_done signal)
     //////////////////////////////////////////////////////////////////
+    wire assert_sched_isr;
+    assign assert_sched_isr = sched_source_mode ? (sensors_enabled ? all_done_pe : (count == user_ratio)) : // sched_source_mode == 1, Timing Manager Mode
+                                                  (count == user_ratio);                                    // sched_source_mode == 0, Legacy Mode
     always @(posedge clk, negedge rst_n) begin
         if (!rst_n)
             sched_isr <= 0;
         else if (reset_sched_isr)
             sched_isr <= 0;
-        else if (~sched_source_mode & (count == user_ratio))
-            // Legacy (mode 0)
-            sched_isr <= 1;
-        else if (sched_source_mode & ~sensors_enabled & (count == user_ratio))
-            // Timing Manager (mode 1) with no sensors enabled
-            sched_isr <= 1;
-        else if (sched_source_mode & all_done_pe)
-            // Timing Manager (mode 1) after sensors are enabled
+        else if (assert_sched_isr)
             sched_isr <= 1;
     end
 

sdk/app_cpu1/common/drv/timing_manager.c

@@ -173,7 +173,7 @@ uint32_t timing_manager_get_trigger_count(void)
  * Specify the interrupt source of the scheduler ISR:
  *
  * Mode 0 uses the timing manager's 'trigger' signal, i.e. the control
- * frequency based on the PWM carrier frequency and the user-specified PWM sub-ratio.
+ * frequency is based on the PWM carrier frequency and the user-specified PWM sub-ratio.
  *
  * Mode 1 uses the timing manager's 'all_done' signal, calling the scheduler
  * when all the sensors are done with acquisition. When no sensors are enabled,

sdk/app_cpu1/common/sys/scheduler.c

@@ -198,7 +198,7 @@ void scheduler_run(void)
             // due to the imprecision of converting FPGA time to double values in the C code.
             // Therefore, we will schedule the task if the difference between the
             // usec_since_last_run and the target interval is within the defined tolerance.
-            if ((usec_since_last_run - t->interval_usec) >= SCHEDULER_INTERVAL_TOLERANCE_USEC) {
+            if ((t->interval_usec - usec_since_last_run) <= SCHEDULER_INTERVAL_TOLERANCE_USEC) {
 
                 // Time to run this task!
                 task_stats_pre_task(&t->stats);

sdk/app_cpu1/common/sys/scheduler.h

@@ -14,13 +14,24 @@
 #define USEC_TO_SEC(usec) (usec / USEC_IN_SEC)
 
 // Timing Threshold - 60ns
-//   Typically, the variance of the measured interval from the expected interval is
-//   no more than 20ns, but we'll use a tolerance of three times this for safety :)
-//   The tolerance value is negative, as the target interval is subtracted from
-//   the measured interval. If the former is larger than the latter, the subtraction
-//   result will be a negative value. The check to run the task then confirms
-//   that the difference is *less-negative* than this tolerance
-#define SCHEDULER_INTERVAL_TOLERANCE_USEC (-0.06)
+//   When the scheduler checks to see if a task should be scheduled in scheduler_run(),
+//   the task's measured loop time is subtracted from the target loop time. If the former
+//   is larger than the latter, the result will be negative and obviously the task should be
+//   scheduled. However, it is possible with floating point numbers that the measured loop
+//   time will be *just less* than the target loop time, in which case the subtraction
+//   result will be a very small positive number. We still want the task to be run in this
+//   case, so instead of checking if the subtraction result is less than 0, we check that
+//   it is less than a very small positive variance value. Typically, this variance of the
+//   measured interval from the expected interval is no more than 20ns, but we'll use a
+//   tolerance of three times this for safety :)
+//   NOTE: this is with the default timing settings of 100 kHz PWM Carrier and
+//   a Timing Manager ratio of 10 events. For abnormal timing settings, the
+//   magnitude of the tolerance can be overridden in user_config.h
+#ifndef USER_CONFIG_SCHEDULER_INTERVAL_TOLERANCE_USEC
+#define SCHEDULER_INTERVAL_TOLERANCE_USEC (0.06)
+#else
+#define SCHEDULER_INTERVAL_TOLERANCE_USEC (USER_CONFIG_SCHEDULER_INTERVAL_TOLERANCE_USEC)
+#endif
 
 // Callback into application when task is run:
 typedef void (*task_callback_t)(void *);

sdk/app_cpu1/user/usr/user_config.h

@@ -49,4 +49,12 @@
 // set to 1 for enabled, 0 for disabled
 #define USER_CONFIG_ENABLE_AMDS_SUPPORT (0)
 
+// Scheduler Interval Tolerance Override
+// as of AMDC Firmware v1.3, all timing variables for tasks (runtime, loop time, etc)
+// are stored as double-precision floating point values, which have precision errors
+// that require a margin of tolerance. sometimes non-default PWM frequency and/or
+// timing manager ratios may necessitate un-commenting the following define to override
+// the default tolerance in common/sys/scheduler.h
+//#define USER_CONFIG_SCHEDULER_INTERVAL_TOLERANCE_USEC (0.15)
+
 #endif // USER_CONFIG_H