nec/pc9801: add 7220 monitor clock register, cleanups around display …

…enable

src/mame/nec/apc.cpp

@@ -212,9 +212,6 @@ UPD7220_DRAW_TEXT_LINE_MEMBER( apc_state::hgdc_draw_text )
 {
 	rgb_t const *const palette = m_palette->palette()->entry_list_raw();
 
-//  if(m_video_ff[DISPLAY_REG] == 0) //screen is off
-//      return;
-
 //  uint8_t interlace_on = m_video_reg[2] == 0x10; /* TODO: correct? */
 	uint8_t char_size = 19;
 
@@ -305,7 +302,7 @@ uint8_t apc_state::apc_port_28_r(offs_t offset)
 	{
 		if(offset & 4)
 		{
-			printf("Read undefined port %02x\n",offset+0x28);
+			logerror("Read undefined port %02x\n",offset+0x28);
 			res = 0xff;
 		}
 		else
@@ -322,7 +319,7 @@ void apc_state::apc_port_28_w(offs_t offset, uint8_t data)
 	else
 	{
 		if(offset & 4)
-			printf("Write undefined port %02x\n",offset+0x28);
+			logerror("Write undefined port %02x\n",offset+0x28);
 		else
 			m_i8259_s->write((offset & 2) >> 1, data);
 	}
@@ -366,7 +363,7 @@ uint8_t apc_state::apc_kbd_r(offs_t offset)
 
 void apc_state::apc_kbd_w(offs_t offset, uint8_t data)
 {
-	printf("KEYB %08x %02x\n",offset,data);
+	logerror("KEYB %08x %02x\n",offset,data);
 }
 
 void apc_state::apc_dma_segments_w(offs_t offset, uint8_t data)
@@ -434,7 +431,7 @@ uint8_t apc_state::apc_rtc_r()
 	/*
 	bit 1 high: low battery.
 	*/
-	//fprintf(stderr, "RTC Read: %d\n", m_rtc->data_out_r());
+	//logerror("RTC Read: %d\n", m_rtc->data_out_r());
 	return m_rtc->data_out_r();
 }
 
@@ -465,7 +462,7 @@ RTC write bits: 76543210
                 |\------- "don't care"
                 \-------- ///
 */
-	if (data&0xc0) fprintf(stderr,"RTC write: 0x%02x\n", data);
+	if (data&0xc0) logerror("RTC write: 0x%02x\n", data);
 	m_rtc->c0_w(BIT(data, 0)); // correct assuming theres a delay for changing command lines before stb
 	m_rtc->c1_w(BIT(data, 1)); // "
 	m_rtc->c2_w(BIT(data, 2)); // "
@@ -854,23 +851,23 @@ void apc_state::apc_dma_hrq_changed(int state)
 
 	m_dmac->hack_w(state);
 
-//  printf("%02x HLDA\n",state);
+//  logerror("%02x HLDA\n",state);
 }
 
 void apc_state::apc_tc_w(int state)
 {
 	/* floppy terminal count */
 	m_fdc->tc_w(state);
 
-//  printf("TC %02x\n",state);
+//  logerror("TC %02x\n",state);
 }
 
 uint8_t apc_state::apc_dma_read_byte(offs_t offset)
 {
 	address_space &program = m_maincpu->space(AS_PROGRAM);
 	offs_t addr = (m_dma_offset[m_dack] << 16) | offset;
 
-//  printf("%08x\n",addr);
+//  logerror("%08x\n",addr);
 
 	return program.read_byte(addr);
 }
@@ -881,7 +878,7 @@ void apc_state::apc_dma_write_byte(offs_t offset, uint8_t data)
 	address_space &program = m_maincpu->space(AS_PROGRAM);
 	offs_t addr = (m_dma_offset[m_dack] << 16) | offset;
 
-//  printf("%08x %02x\n",addr,data);
+//  logerror("%08x %02x\n",addr,data);
 
 	program.write_byte(addr, data);
 }
@@ -891,10 +888,10 @@ inline void apc_state::set_dma_channel(int channel, int state)
 	if (!state) m_dack = channel;
 }
 
-void apc_state::apc_dack0_w(int state) { /*printf("%02x 0\n",state);*/ set_dma_channel(0, state); }
-void apc_state::apc_dack1_w(int state) { /*printf("%02x 1\n",state);*/ set_dma_channel(1, state); }
-void apc_state::apc_dack2_w(int state) { /*printf("%02x 2\n",state);*/ set_dma_channel(2, state); }
-void apc_state::apc_dack3_w(int state) { /*printf("%02x 3\n",state);*/ set_dma_channel(3, state); }
+void apc_state::apc_dack0_w(int state) { /*logerror("%02x 0\n",state);*/ set_dma_channel(0, state); }
+void apc_state::apc_dack1_w(int state) { /*logerror("%02x 1\n",state);*/ set_dma_channel(1, state); }
+void apc_state::apc_dack2_w(int state) { /*logerror("%02x 2\n",state);*/ set_dma_channel(2, state); }
+void apc_state::apc_dack3_w(int state) { /*logerror("%02x 3\n",state);*/ set_dma_channel(3, state); }
 
 /*
 CH0: CRT

src/mame/nec/pc9801.cpp

@@ -645,6 +645,7 @@ void pc9801_state::pc9801_common_io(address_map &map)
 	map(0x0060, 0x0063).rw(m_hgdc[0], FUNC(upd7220_device::read), FUNC(upd7220_device::write)).umask16(0x00ff); //upd7220 character ports / <undefined>
 	map(0x0064, 0x0064).w(FUNC(pc9801_state::vrtc_clear_w));
 //  map(0x006c, 0x006f) border color / <undefined>
+	map(0x006c, 0x006f).w(FUNC(pc9801_state::border_color_w)).umask16(0x00ff);
 	// TODO: PC-98Bible suggests that $73 timer #1 is unavailable on non-vanilla models (verify on HW)
 	// (can be accessed only thru the $3fdb alias)
 	map(0x0070, 0x0077).rw(m_pit, FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0xff00);

src/mame/nec/pc9801.h

@@ -310,6 +310,8 @@ class pc9801_state : public pc98_base_state
 	u8 m_vram_bank = 0;
 	u8 m_vram_disp = 0;
 
+	virtual void border_color_w(offs_t offset, u8 data);
+
 private:
 	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
 
@@ -403,6 +405,8 @@ class pc9801vm_state : public pc9801_state
 	void pc9801rs_video_ff_w(offs_t offset, uint8_t data);
 	void pc9801rs_a0_w(offs_t offset, uint8_t data);
 
+	virtual void border_color_w(offs_t offset, u8 data) override;
+
 	uint8_t ide_ctrl_r();
 	void ide_ctrl_w(uint8_t data);
 	uint16_t ide_cs0_r(offs_t offset, uint16_t mem_mask = ~0);

src/mame/nec/pc9801_v.cpp

@@ -32,8 +32,10 @@ uint32_t pc9801_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap
 
 	/* graphics */
 	if(m_video_ff[DISPLAY_REG] != 0)
+	{
 		m_hgdc[1]->screen_update(screen, bitmap, cliprect);
-	m_hgdc[0]->screen_update(screen, bitmap, cliprect);
+		m_hgdc[0]->screen_update(screen, bitmap, cliprect);
+	}
 
 	return 0;
 }
@@ -82,9 +84,6 @@ void pc9801_state::draw_text(bitmap_rgb32 &bitmap, uint32_t addr, int y, int wd,
 {
 	rgb_t const *const palette = m_palette->palette()->entry_list_raw();
 
-	if(m_video_ff[DISPLAY_REG] == 0) //screen is off
-		return;
-
 //  uint8_t interlace_on = m_video_ff[INTERLACE_REG];
 	uint8_t char_size = m_video_ff[FONTSEL_REG] ? 16 : 8;
 
@@ -126,7 +125,8 @@ void pc9801_state::draw_text(bitmap_rgb32 &bitmap, uint32_t addr, int y, int wd,
 			if((tile & 0x7e00) == 0x5600)
 			{
 				// ikochan (karaoke intro) and mightyhd (game start and gameplay)
-				// draws these PCG strips where first tile is identical to second, with LR disabled.
+				// draws these PCG strips where first tile is identical to second,
+				// with LR disabled on both but expecting the right half at the repetition anyway.
 				// TODO: what happens with LR enabled?
 				if(lasttile == (tile | knj_tile))
 				{
@@ -473,6 +473,25 @@ void pc9801_state::pc9801_a0_w(offs_t offset, uint8_t data)
 	}
 }
 
+void pc9801_state::border_color_w(offs_t offset, u8 data)
+{
+	if (data & ~1)
+		logerror("border_color_w [%02x] %02x\n", offset + 1, data);
+}
+
+void pc9801vm_state::border_color_w(offs_t offset, u8 data)
+{
+	pc9801_state::border_color_w(offset, data);
+	if (offset)
+	{
+		// 24.83/15.75 kHz selector, available for everything but vanilla class
+		// TODO: verify clock for 200 line mode (handtuned), verify that vanilla effectively cannot select it thru dips.
+		const XTAL screen_clock = (data & 1 ? XTAL(21'052'600) : (XTAL(21'052'600) / 3) * 2) / 8;
+
+		m_hgdc[0]->set_unscaled_clock(screen_clock);
+		m_hgdc[1]->set_unscaled_clock(screen_clock);
+	}
+}
 
 /*************************************************
  *

src/mame/nec/pc9821.cpp

@@ -82,8 +82,8 @@ uint32_t pc9821_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap
 		}
 		else
 			m_hgdc[1]->screen_update(screen, bitmap, cliprect);
+		m_hgdc[0]->screen_update(screen, bitmap, cliprect);
 	}
-	m_hgdc[0]->screen_update(screen, bitmap, cliprect);
 
 	return 0;
 }