Merge pull request #425 from guitorri/remove-non-GPL-verilog-a

Remove non-GPL verilog-a models.
Qucs · Feb 1, 2016 · 3f91d37 · 3f91d37
2 parents c03b491 + c11e12c
commit 3f91d37
Show file tree

Hide file tree

Showing 84 changed files with 23,284 additions and 150,913 deletions.
diff --git a/Makefile.am b/Makefile.am
@@ -57,16 +57,16 @@ QUCSTEST_ENV = export PATH=$(MORE_PATH):$(PATH); \
                export QUCS_LIBDIR=$(abs_top_srcdir)/qucs/qucs-lib/library; \
                export QUCSATOR=qucsator;
 
-# Run tests for Qucs (GUI) 
+if COND_MACOSX
+macossuffix=_OSX
+endif
+
+# Run tests for Qucs (GUI)
 # Schematic to Netlist conversion require QucsConv and Qucs component library,
 # so use the prefix of the installed package.
 qucscheck: $(PWD)/qucs-test
 	$(QUCSTEST_ENV) \
-	cd qucs-test && python run.py --qucs
-
-if COND_MACOSX
-macossuffix=_OSX
-endif
+	cd qucs-test && python run.py --qucs --exclude skip$(macossuffix).txt
 
 # Run test on qucsator
 qucsatorcheck: $(PWD)/qucs-test

diff --git a/qucs-core/qucs-core.cbp b/qucs-core/qucs-core.cbp
@@ -290,10 +290,6 @@
 		<Unit filename="src/components/verilog/andor4x3.va" />
 		<Unit filename="src/components/verilog/andor4x4.va" />
 		<Unit filename="src/components/verilog/binarytogrey4bit.va" />
-		<Unit filename="src/components/verilog/bsim3v34nMOS.va" />
-		<Unit filename="src/components/verilog/bsim3v34pMOS.va" />
-		<Unit filename="src/components/verilog/bsim4v30nMOS.va" />
-		<Unit filename="src/components/verilog/bsim4v30pMOS.va" />
 		<Unit filename="src/components/verilog/comp_1bit.va" />
 		<Unit filename="src/components/verilog/comp_2bit.va" />
 		<Unit filename="src/components/verilog/comp_4bit.va" />
@@ -306,19 +302,9 @@
 		<Unit filename="src/components/verilog/dmux4to16.va" />
 		<Unit filename="src/components/verilog/fa1b.va" />
 		<Unit filename="src/components/verilog/fa2b.va" />
-		<Unit filename="src/components/verilog/fbh_hbt-2_2a.va" />
 		<Unit filename="src/components/verilog/gatedDlatch.va" />
 		<Unit filename="src/components/verilog/greytobinary4bit.va" />
 		<Unit filename="src/components/verilog/ha1b.va" />
-		<Unit filename="src/components/verilog/hicumL0V1p12.va" />
-		<Unit filename="src/components/verilog/hicumL0V1p2.va" />
-		<Unit filename="src/components/verilog/hicumL0V1p2g.va" />
-		<Unit filename="src/components/verilog/hicumL0V1p3.va" />
-		<Unit filename="src/components/verilog/hicumL2V2p11.va" />
-		<Unit filename="src/components/verilog/hicumL2V2p22.va" />
-		<Unit filename="src/components/verilog/hicumL2V2p23.va" />
-		<Unit filename="src/components/verilog/hicumL2V2p24.va" />
-		<Unit filename="src/components/verilog/hicumL2V2p31n.va" />
 		<Unit filename="src/components/verilog/hpribin4bit.va" />
 		<Unit filename="src/components/verilog/jkff_SR.va" />
 		<Unit filename="src/components/verilog/libverilog.ap" />

diff --git a/qucs-core/src/components/component_id.h b/qucs-core/src/components/component_id.h
@@ -145,20 +145,11 @@ enum circuit_type {
   CIR_BUFFER,
 
   // verilog devices
-  CIR_HBT_X,
-  CIR_hicumL2V2p1,
   CIR_mod_amp,
-  CIR_hic2_full,
   CIR_log_amp,
-  CIR_hic0_full,
   CIR_potentiometer,
   CIR_MESFET,
   CIR_EKV26MOS,
-  CIR_hicumL0V1p2,
-  CIR_hicumL0V1p2g,
-  CIR_hicumL0V1p3,
-  CIR_hicumL2V2p23,
-  CIR_hicumL2V2p24,
   CIR_photodiode,
   CIR_phototransistor,
   CIR_nigbt,

diff --git a/qucs-core/src/components/components.h b/qucs-core/src/components/components.h
@@ -142,28 +142,14 @@
 #include "digital/digisource.h"
 #include "digital/buffer.h"
 
-#include "verilog/hicumL2V2p11.core.h"
-#include "verilog/fbh_hbt-2_2a.core.h"
-#include "verilog/mod_amp.core.h"
-#include "verilog/hicumL2V2p22.core.h"
+#include "verilog/EKV26MOS.core.h"
 #include "verilog/log_amp.core.h"
-#include "verilog/hicumL0V1p12.core.h"
-#include "verilog/potentiometer.core.h"
 #include "verilog/MESFET.core.h"
-#include "verilog/EKV26MOS.core.h"
-#include "verilog/bsim3v34nMOS.core.h"
-#include "verilog/bsim3v34pMOS.core.h"
-#include "verilog/bsim4v30nMOS.core.h"
-#include "verilog/bsim4v30pMOS.core.h"
-#include "verilog/hicumL0V1p2.core.h"
-#include "verilog/hicumL0V1p2g.core.h"
-#include "verilog/hicumL0V1p3.core.h"
-#include "verilog/hicumL2V2p23.core.h"
-#include "verilog/hicumL2V2p24.core.h"
-#include "verilog/hicumL2V2p31n.core.h"
+#include "verilog/mod_amp.core.h"
+#include "verilog/nigbt.core.h"
 #include "verilog/photodiode.core.h"
 #include "verilog/phototransistor.core.h"
-#include "verilog/nigbt.core.h"
+#include "verilog/potentiometer.core.h"
 
 #include "verilog/dff_SR.core.h"
 #include "verilog/tff_SR.core.h"

diff --git a/qucs-core/src/components/verilog/CMakeLists.txt b/qucs-core/src/components/verilog/CMakeLists.txt
@@ -16,10 +16,6 @@ SET( VA_FILES
   andor4x3
   andor4x4
   binarytogrey4bit
-  bsim3v34nMOS
-  bsim3v34pMOS
-  bsim4v30nMOS
-  bsim4v30pMOS
   comp_1bit
   comp_2bit
   comp_4bit
@@ -32,19 +28,9 @@ SET( VA_FILES
   EKV26MOS
   fa1b
   fa2b
-  fbh_hbt-2_2a
   gatedDlatch
   greytobinary4bit
   ha1b
-  hicumL0V1p12
-  hicumL0V1p2
-  hicumL0V1p2g
-  hicumL0V1p3
-  hicumL2V2p11
-  hicumL2V2p22
-  hicumL2V2p23
-  hicumL2V2p24
-  hicumL2V2p31n
   hpribin4bit
   jkff_SR
   log_amp

diff --git a/qucs-core/src/components/verilog/Makefile.am b/qucs-core/src/components/verilog/Makefile.am
@@ -44,28 +44,14 @@ XML_BUILD = \
 .va.cpp:
 
 VA_FILES = \
-	fbh_hbt-2_2a.va \
-	hicumL2V2p11.va \
-	mod_amp.va \
-	hicumL2V2p22.va \
+	EKV26MOS.va \
 	log_amp.va \
-	hicumL0V1p12.va \
-	potentiometer.va \
 	MESFET.va \
-	EKV26MOS.va \
-	bsim3v34nMOS.va \
-	bsim3v34pMOS.va \
-	bsim4v30nMOS.va \
-	bsim4v30pMOS.va \
-	hicumL0V1p2.va \
-	hicumL0V1p2g.va \
-	hicumL0V1p3.va \
-	hicumL2V2p23.va \
-	hicumL2V2p24.va \
-	hicumL2V2p31n.va \
+	mod_amp.va \
+	nigbt.va \
 	photodiode.va \
 	phototransistor.va \
-	nigbt.va \
+	potentiometer.va \
 	\
 	dff_SR.va \
 	tff_SR.va \