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Fix CSPLayout to ensure qubits in multi qubit gates are connected #12912

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@ChilliPenguin ChilliPenguin commented Aug 6, 2024

Summary

Adds more qubit connection requirements for CSPLayout to ensure 3+ qubit gates work correctly.
This fixes #7155 and is essentially just adding onto PR #7625 with slight modification and unit tests added.

Details and comments

This doesn't address the issue of directionality (specifically how should a connection between two control qubits be enforced if directionality matters)

@qiskit-bot qiskit-bot added the Community PR PRs from contributors that are not 'members' of the Qiskit repo label Aug 6, 2024
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@ChilliPenguin ChilliPenguin changed the title [WIP] Fix CSPLayout to ensure qubits in multi qubit gates are connected Fix CSPLayout to ensure qubits in multi qubit gates are connected Aug 6, 2024
@ChilliPenguin ChilliPenguin marked this pull request as ready for review August 6, 2024 22:45
@ChilliPenguin ChilliPenguin requested a review from a team as a code owner August 6, 2024 22:45
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1ucian0 commented Feb 19, 2025

Hi @ChilliPenguin, thanks for taking care of it. Can you @Silrem as a co-author? as you are based on their PR. I think enforcing the 3q-gate bidirectional when you dont know how the box is implemented makes sense. If it is a controlled-2q or a 2c-1q gate, maybe you can relax it?

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CSP ignores 3-or-more-qubit gates
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