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Qiskit · Feb 19, 2023 · 48ce32c · 48ce32c
1 parent 0160592
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Showing 4 changed files with 21 additions and 10 deletions.
diff --git a/qiskit/circuit/library/standard_gates/equivalence_library.py b/qiskit/circuit/library/standard_gates/equivalence_library.py
@@ -41,6 +41,7 @@
     SwapGate,
     CSwapGate,
     iSwapGate,
+    SiSwapGate,
     SXGate,
     SXdgGate,
     CSXGate,
@@ -751,13 +752,13 @@
 #      └──────────┘           └────────────┘└────────────┘
 
 q = QuantumRegister(2, "q")
-def_iswap = QuantumCircuit(q)
+def_siswap = QuantumCircuit(q)
 for inst, qargs, cargs in [
-    (RXXGate(-np.pi / 4), [q[0], q[1]], []),
-    (RYYGate(-np.pi / 4), [q[1], q[1]], []),
+    (RXXGate(-pi / 4), [q[0], q[1]], []),
+    (RYYGate(-pi / 4), [q[0], q[1]], []),
 ]:
-    def_iswap.append(inst, qargs, cargs)
-_sel.add_equivalence(iSwapGate(), def_iswap)
+    def_siswap.append(inst, qargs, cargs)
+_sel.add_equivalence(SiSwapGate(), def_siswap)
 
 # SXGate
 #               global phase: π/4

diff --git a/qiskit/circuit/library/standard_gates/siswap.py b/qiskit/circuit/library/standard_gates/siswap.py
@@ -37,8 +37,8 @@ class SiSwapGate(Gate):
         B\ q_0, q_1 =
             \begin{pmatrix}
                 1       & 0                  & 0                     & 0     \\
-                0       & \frac{1}{\sqrt(2)} & \frac{i}{\sqrt(2)}     & 0     \\
-                0       & \frac{i}{\sqrt(2)} & \frac{1}{\sqrt(2)}     & 0     \\
+                0       & \frac{1}{\sqrt{2}} & \frac{i}{\sqrt{2}}     & 0     \\
+                0       & \frac{i}{\sqrt{2}} & \frac{1}{\sqrt{2}}     & 0     \\
                 0       & 0                  & 0                     & 1
             \end{pmatrix}
     """

diff --git a/qiskit/synthesis/su4/siswap_decompose.py b/qiskit/synthesis/su4/siswap_decompose.py
@@ -42,8 +42,12 @@ class SiSwapDecomposer:
     """
     A class for decomposing 2-qubit unitaries into at most 3 uses of the sqrt(iSWAP) gate.
 
+    This basis is attractive in that it is shorter/cheaper than iSWAP and generates a large
+    volume (~79%) of Haar-random SU(4) unitaries with only two applications, and an even
+    larger volume when approximation is enabled.
+
     Args:
-        euler_basis (list(str)): single-qubit gates basis in the decomposition
+        euler_basis (list(str)): single-qubit gates basis in the decomposition.
 
     Reference:
         1. C. Huang et al,

diff --git a/test/python/synthesis/test_siswap_synthesis.py b/test/python/synthesis/test_siswap_synthesis.py
@@ -35,6 +35,7 @@
 
 _EPS = 1e-12
 
+
 @ddt
 class TestSiSwapSynth(QiskitTestCase):
     """Test synthesis of SU(4)s over SiSwap basis."""
@@ -112,7 +113,7 @@ def test_siswap_corners_0_use(self, corner):
             [np.pi / 4, np.pi / 8, -np.pi / 8],  # inverse of above (and locally equivalent)
             [np.pi / 4, np.pi / 16, np.pi / 16],  # quarter-way between CX and SWAP
             [np.pi / 4, np.pi / 16, np.pi / 16],  # inverse of above (and locally equivalent)
-            [np.pi / 6, np.pi / 8, np.pi / 24],  # red and blue and green intersection 
+            [np.pi / 6, np.pi / 8, np.pi / 24],  # red and blue and green intersection
             [np.pi / 6, np.pi / 8, -np.pi / 24],  # inverse of above (not locally equivalent)
             [np.pi / 16, np.pi / 24, np.pi / 48],  # red and blue and purple intersection
             [np.pi / 16, np.pi / 24, -np.pi / 48],  # inverse of above (not locally equivalent)
@@ -121,11 +122,16 @@ def test_siswap_corners_0_use(self, corner):
     )
     def test_siswap_special_points(self, p):
         """Test special points in the Weyl chamber related to SiSwap polytopes."""
-        u = Operator(RXXGate(-2*p[0])) & Operator(RYYGate(-2*p[1])) & Operator(RZZGate(-2*p[2]))
+        u = (
+            Operator(RXXGate(-2 * p[0]))
+            & Operator(RYYGate(-2 * p[1]))
+            & Operator(RZZGate(-2 * p[2]))
+        )
         decomposer = SiSwapDecomposer(euler_basis=["u"])
         circuit = decomposer(u)
         self.assertEqual(circuit.count_ops().get("siswap", 0), 2)
         self.assertEqual(Operator(circuit), Operator(u))
 
+
 if __name__ == "__main__":
     unittest.main()