Add cocotb testbench runner

.github/workflows/_cocotb_test.yml

@@ -0,0 +1,40 @@
+on:
+  workflow_call:
+
+jobs:
+  cocotb_test:
+    runs-on: ubuntu-latest
+    steps:
+      # Git repositories
+      - name: Checkout Source
+        uses: actions/checkout@v2
+        with:
+          path: PandABlocks-fpga
+          # require history to get back to last tag for version number of branches
+          fetch-depth: 0
+
+      # Login into ghcr
+      - name: login to ghcr
+        uses: docker/login-action@v1
+        with:
+          registry: ghcr.io
+          username: ${{ github.actor }}
+          password: ${{ secrets.GITHUB_TOKEN  }}
+      - name: Run cocotb tests
+        run: |
+          docker pull ghcr.io/pandablocks/pandablocks-dev-container:4.0a7
+          docker run \
+            --net=host \
+            -v "${{ github.workspace }}:/repos" \
+            -v "${{ github.workspace }}/build:/build" \
+            ghcr.io/pandablocks/pandablocks-dev-container:4.0a7 \
+            /bin/bash -c \
+            "cd PandABlocks-fpga && ln -s CONFIG.example CONFIG && make cocotb_tests && sed -i 's/\/repos\/pandablocks-fpga\///i' cocotb_coverage.xml"
+      - name: Upload coverage to Codecov
+        uses: codecov/codecov-action@v4
+        with:
+          name: nvc-coverage
+          files: cocotb_coverage.xml
+        # env:
+        #   CODECOV_TOKEN: ${{ secrets.CODECOV_TOKEN }}
+

.github/workflows/code.yml

@@ -20,9 +20,12 @@ jobs:
   make_zpkg:
     uses: ./.github/workflows/_make_zpkg.yml
 
-  # Release on push to tag
+  # cocotb tests
+  cocotb_test:
+    uses: ./.github/workflows/_cocotb_test.yml
+
   release:
-    needs: [ make_boot, make_zpkg, test_hdl, test_matrix, test_python_autogen ]
+    needs: [ make_boot, make_zpkg, test_hdl, test_matrix, test_python_autogen, cocotb_test ]
     uses: ./.github/workflows/_release.yml
 
   # Generate job matrix to evenly split tests
@@ -38,4 +41,5 @@ jobs:
     needs: [test_matrix, test_python_autogen]
     uses: ./.github/workflows/_test_hdl.yml
     with:
-      matrix: ${{needs.test_matrix.outputs.matrix}}
+      matrix: ${{needs.test_matrix.outputs.matrix}}
+

.gitignore

@@ -14,3 +14,6 @@
 
 # For mac
 *.DS_Store
+
+# cocotb build dir
+sim_build*

Makefile

@@ -250,6 +250,12 @@ single_hdl_test: $(TIMING_BUILD_DIRS) $(BUILD_DIR)/hdl_timing/pcap carrier_ip
 hdl_timing: $(TIMING_BUILD_DIRS)
 .PHONY: hdl_timing
 
+MODULE = all
+SIMULATOR = nvc
+# e.g. make cocotb_tests MODULE=pulse TEST="No delay or stretch"
+cocotb_tests: $(AUTOGEN_BUILD_DIR)
+	$(PYTHON) $(TOP)/common/python/cocotb_timing_test_runner.py -c --panda-build-dir $(BUILD_DIR) --sim $(SIMULATOR) $(MODULE) '$(TEST)'
+.PHONY: cocotb_tests
 
 # ------------------------------------------------------------------------------
 # FPGA build

common/hdl/defines/support.vhd

@@ -9,6 +9,8 @@ constant c_UNSIGNED_GRAY_ENCODING    : std_logic_vector(1 downto 0) := "01";
 constant c_SIGNED_BINARY_ENCODING    : std_logic_vector(1 downto 0) := "10";
 constant c_SIGNED_GRAY_ENCODING      : std_logic_vector(1 downto 0) := "11";
 
+type vector_array is array(natural range <>) of std_logic_vector;
+
 --
 -- Functions
 --
@@ -96,4 +98,5 @@ begin
     return index;
 end function;
 
+
 end support;

common/hdl/fifo.vhd

@@ -0,0 +1,139 @@
+-- FIFO with AXI style handshaking.  The valid signal is asserted by the
+-- producer when data is available to be transferred, and the ready signal is
+-- asserted when the receiver is ready: transfer happens on the clock cycle when
+-- ready and valid are asserted.  Two further AXI rules are followed: when valid
+-- is asserted it must remain asserted until ready is seen; and the assertion of
+-- valid must be independent of the state of ready.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.support.all;
+USE work.top_defines.all;
+
+entity fifo is
+    generic (
+        FIFO_BITS : natural := 5;       -- log2 FIFO depth
+        DATA_WIDTH : natural;           -- Width of data path
+        MEM_STYLE : string := ""        -- Can override tool default
+    );
+    port (
+        clk_i : in std_logic;
+
+        -- Write interface
+        write_valid_i : in std_logic;
+        write_ready_o : out std_logic := '0';
+        write_data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
+
+        -- Read interface
+        read_valid_o : out std_logic := '0';
+        read_ready_i : in std_logic;
+        read_data_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
+
+        -- Control and status
+        reset_fifo_i : in std_logic := '0';
+        fifo_depth_o : out unsigned(FIFO_BITS downto 0) := (others => '0')
+    );
+end;
+
+architecture arch of fifo is
+    subtype DATA_RANGE is natural range DATA_WIDTH-1 downto 0;
+    subtype ADDRESS_RANGE is natural range 0 to 2**FIFO_BITS-1;
+    subtype ADDRESS_RANGE_BITS is natural range FIFO_BITS downto 0;
+
+    signal fifo : vector_array(ADDRESS_RANGE)(DATA_RANGE);
+    attribute RAM_STYLE : string;
+    attribute RAM_STYLE of fifo : signal is MEM_STYLE;
+
+    -- This is just computing a mask with only the top bit set to be used for
+    -- detecting the FIFO full condition
+    function COMPARE_MASK return unsigned
+    is
+        variable result : unsigned(ADDRESS_RANGE_BITS) := (others => '0');
+    begin
+        result(FIFO_BITS) := '1';
+        return result;
+    end;
+
+    signal write_pointer : unsigned(ADDRESS_RANGE_BITS) := (others => '0');
+    signal read_pointer : unsigned(ADDRESS_RANGE_BITS) := (others => '0');
+    -- The read valid state is separated from read_valid_o to improve data flow
+    signal read_valid : std_logic := '0';
+
+begin
+    process (clk_i)
+        variable read_enable : std_logic;
+        variable next_write_pointer : unsigned(ADDRESS_RANGE_BITS);
+        variable next_read_pointer : unsigned(ADDRESS_RANGE_BITS);
+        variable write_address : ADDRESS_RANGE;
+        variable read_address : ADDRESS_RANGE;
+        variable next_read_valid : std_logic;
+
+    begin
+        if rising_edge(clk_i) then
+            next_write_pointer := write_pointer;
+            next_read_pointer := read_pointer;
+            if reset_fifo_i then
+                next_write_pointer := (others => '0');
+                next_read_pointer := (others => '0');
+                -- Block writes during reset
+                write_ready_o <= '0';
+                read_valid <= '0';
+                read_enable := '0';
+            else
+                -- Advance write pointer if writing
+                if write_valid_i and write_ready_o then
+                    next_write_pointer := write_pointer + 1;
+                end if;
+
+                -- Advance read pointer if reading.  We keep read_data_o valid
+                -- at all times when possible
+                read_enable :=
+                    read_valid and (read_ready_i or not read_valid_o);
+                if read_enable then
+                    next_read_pointer := read_pointer + 1;
+                end if;
+
+                -- Compute full and empty conditions.  Empty is simply equality
+                -- of pointers, full is when the write pointer is exactly one
+                -- FIFO depth ahead of the read pointer.  This computation can
+                -- safely be done on the next_ pointers, which gives a small
+                -- flow optimisation.
+                write_ready_o <= to_std_logic(
+                    next_write_pointer /= (next_read_pointer xor COMPARE_MASK));
+                read_valid <= to_std_logic(
+                    next_write_pointer /= next_read_pointer);
+            end if;
+            write_pointer <= next_write_pointer;
+            read_pointer <= next_read_pointer;
+
+            -- Throw away the top bit of the read/write pointers for access, the
+            -- top bit is only used as a cycle counter to distinguish full and
+            -- empty states
+            write_address := to_integer(write_pointer(FIFO_BITS-1 downto 0));
+            read_address  := to_integer(read_pointer(FIFO_BITS-1 downto 0));
+
+            -- Write
+            if write_valid_i and write_ready_o then
+                fifo(write_address) <= write_data_i;
+            end if;
+
+            -- Read
+            next_read_valid := read_valid_o;
+            if reset_fifo_i then
+                next_read_valid := '0';
+            elsif read_enable then
+                read_data_o <= fifo(read_address);
+                next_read_valid := '1';
+            elsif read_ready_i then
+                next_read_valid := '0';
+            end if;
+            read_valid_o <= next_read_valid;
+
+            -- Compute number of points in FIFO, also counting the output buffer
+            fifo_depth_o <=
+                next_write_pointer - next_read_pointer + next_read_valid;
+        end if;
+    end process;
+end;

common/hdl/spbram.vhd

@@ -33,22 +33,18 @@ end spbram;
 architecture rtl of spbram is
 
 type mem_type is array (2**AW-1 downto 0) of std_logic_vector (DW-1 downto 0);
-shared variable mem : mem_type := (others => (others => '0'));
 
 begin
 
-process (clka)
+process (clka, clkb)
+    variable mem : mem_type := (others => (others => '0'));
 begin
-   if (clka'event and clka = '1') then
+   if rising_edge(clka) then
      if (wea = '1') then
         mem(to_integer(unsigned(addra))) := dina;
      end if;
    end if;
-end process;
-
-process (clkb)
-begin
-   if (clkb'event and clkb = '1') then
+   if rising_edge(clkb) then
      doutb <= mem(to_integer(unsigned(addrb)));
    end if;
 end process;