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Add V850E2M Architecture #1430

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merged 13 commits into from
Jun 29, 2020
Merged

Add V850E2M Architecture #1430

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9f6cbc8
Add V850E2M Architecture
Aleckaj Jan 14, 2020
946ef86
Removed Whitespaces, Fixed some Floatissues, Fixed Divideproblems
Aleckaj Jan 16, 2020
392b38b
Added Manual and syncronised Code with @esaulenka
Aleckaj Jan 18, 2020
b356b40
Changed NOP Instruction
Aleckaj Jan 19, 2020
5e660b8
Added Files for builder subsystem + little bugfixes
Aleckaj Jan 21, 2020
8f3cf0d
Improved code with the help of @GhidorahRex
Aleckaj Feb 17, 2020
ddbbafa
adjusted .cspec-File
Aleckaj Feb 19, 2020
798c94f
Minor changes with help of @GhidorahRex
Aleckaj Feb 21, 2020
f317ada
Macros and cspec fixes
Aleckaj Feb 24, 2020
ab6112c
initial V850 patterns
mumbel Mar 1, 2020
17540d3
Merge pull request #1 from mumbel/v850patterns
Aleckaj Mar 2, 2020
d37ef2a
Added small changes from @esaulenka
Aleckaj Mar 2, 2020
cfc4c8c
Added .opinion File by @HexRoman for the analyzeHeadless
Aleckaj Apr 12, 2020
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Empty file added Ghidra/Processors/V850E2M/Module.manifest
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4 changes: 4 additions & 0 deletions Ghidra/Processors/V850E2M/build.gradle
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apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
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apply from: "$rootProject.projectDir/gradle/processorProject.gradle"
apply plugin: 'eclipse'
eclipse.project.name = 'Processors v850'
30 changes: 30 additions & 0 deletions Ghidra/Processors/V850E2M/certification.manifest
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##VERSION: 2.0
Module.manifest||GHIDRA||||END|
build.gradle||GHIDRA||||END|
data/languages/V850E2M.cspec||GHIDRA||||END|
data/languages/V850E2M.ldefs||GHIDRA||||END|
data/languages/V850E2M.pspec||GHIDRA||||END|
data/languages/V850E2M.slaspec||GHIDRA||||END|
data/languages/Helpers/Conditions.sinc||GHIDRA||||END|
data/languages/Helpers/Extras.sinc||GHIDRA||||END|
data/languages/Helpers/Macros.sinc||GHIDRA||||END|
data/languages/Helpers/Register.sinc||GHIDRA||||END|
data/languages/Helpers/Tokens.sinc||GHIDRA||||END|
data/languages/Helpers/Variables.sinc||GHIDRA||||END|
data/languages/Instructions/Arithmetic.sinc||GHIDRA||||END|
data/languages/Instructions/BitSearch.sinc||GHIDRA||||END|
data/languages/Instructions/BitManipulation.sinc||GHIDRA||||END|
data/languages/Instructions/Branch.sinc||GHIDRA||||END|
data/languages/Instructions/Conditional.sinc||GHIDRA||||END|
data/languages/Instructions/DataManipulation.sinc||GHIDRA||||END|
data/languages/Instructions/Divide.sinc||GHIDRA||||END|
data/languages/Instructions/Float.sinc||GHIDRA||||END|
data/languages/Instructions/HighSpeedDivide.sinc||GHIDRA||||END|
data/languages/Instructions/Load.sinc||GHIDRA||||END|
data/languages/Instructions/Logic.sinc||GHIDRA||||END|
data/languages/Instructions/Multiply.sinc||GHIDRA||||END|
data/languages/Instructions/MultiplyAccumulate.sinc||GHIDRA||||END|
data/languages/Instructions/Saturated.sinc||GHIDRA||||END|
data/languages/Instructions/Special.sinc||GHIDRA||||END|
data/languages/Instructions/Store.sinc||GHIDRA||||END|
data/manuals/v850.idx||GHIDRA||||END|
38 changes: 38 additions & 0 deletions Ghidra/Processors/V850E2M/data/languages/Helpers/Conditions.sinc
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#####################################################
##### Conditions #####
#####################################################


c0003: "v" is op0003=0x0 { tmp:1 = ($(OV)) == 1; export tmp; }
c0003: "nv" is op0003=0x8 { tmp:1 = ($(OV)) == 0; export tmp; }
c0003: "c" is op0003=0x1 { tmp:1 = ($(CY)) == 1; export tmp; }
c0003: "nc" is op0003=0x9 { tmp:1 = ($(CY)) == 0; export tmp; }
c0003: "e" is op0003=0x2 { tmp:1 = ($(Z)) == 1; export tmp; }
c0003: "ne" is op0003=0xA { tmp:1 = ($(Z)) == 0; export tmp; }
c0003: "nh" is op0003=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; }
c0003: "h" is op0003=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; }
c0003: "n" is op0003=0x4 { tmp:1 = ($(S)) == 1; export tmp; }
c0003: "p" is op0003=0xC { tmp:1 = ($(S)) == 0; export tmp; }
c0003: "r" is op0003=0x5 { tmp:1 = 1; export tmp; }
c0003: "sa" is op0003=0xD { tmp:1 = ($(SAT)) == 1; export tmp; }
c0003: "lt" is op0003=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; }
c0003: "ge" is op0003=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; }
c0003: "le" is op0003=0x7 { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; }
c0003: "gt" is op0003=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; }

c1720: "v" is op1720=0x0 { tmp:1 = ($(OV)) == 1; export tmp; }
c1720: "nv" is op1720=0x8 { tmp:1 = ($(OV)) == 0; export tmp; }
c1720: "c" is op1720=0x1 { tmp:1 = ($(CY)) == 1; export tmp; }
c1720: "nc" is op1720=0x9 { tmp:1 = ($(CY)) == 0; export tmp; }
c1720: "e" is op1720=0x2 { tmp:1 = ($(Z)) == 1; export tmp; }
c1720: "ne" is op1720=0xA { tmp:1 = ($(Z)) == 0; export tmp; }
c1720: "nh" is op1720=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; }
c1720: "h" is op1720=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; }
c1720: "n" is op1720=0x4 { tmp:1 = ($(S)) == 1; export tmp; }
c1720: "p" is op1720=0xC { tmp:1 = ($(S)) == 0; export tmp; }
c1720: "r" is op1720=0x5 { tmp:1 = 1; export tmp; }
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c1720: "sa" is op1720=0xD { tmp:1 = ($(SAT)) == 1; export tmp; }
c1720: "lt" is op1720=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; }
c1720: "ge" is op1720=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; }
c1720: "le" is op1720=0x7 { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; }
c1720: "gt" is op1720=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; }
125 changes: 125 additions & 0 deletions Ghidra/Processors/V850E2M/data/languages/Helpers/Extras.sinc
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#####################################################
##### Extras #####
#####################################################


# read r0 always return zero
R0004: _R0004 is _R0004 & _R0004=0 { local x:4=0; export x; }
R0004: _R0004 is _R0004 { export _R0004; }

R1115: _R1115 is _R1115 & _R1115=0 { local x:4=0; export x; }
R1115: _R1115 is _R1115 { export _R1115; }

R2731: _R2731 is _R2731 & _R2731=0 { local x:4=0; export x; }
R2731: _R2731 is _R2731 { export _R2731; }


adr9: res is op0406 & s1115
[ res = ((s1115 << 4) | (op0406 << 1)) + inst_start; ]
{
export *:4 res;
}

adr22: res is s0005; op1631 & op1616=0
[ res = ((s0005 << 16) | op1631) + inst_start; ]
{
export *:4 res;
}

adr32: res is op1631 & op1616=0; op3247
[ res = ((op3247 << 16) | op1631) + inst_start; ]
{
export *:4 res;
}

reg4: op0_1720 is op2323=0 & op0_1720 { export op0_1720; }
reg4: op1_1720 is op2323=1 & op1_1720 { export op1_1720; }



##### Prep/Disp Loop #####

PrepList20: r20 is prep27=1 & r20 { push(r20); }
PrepList20: is prep27=0 { }

PrepList21: r21 is prep26=1 & prep27=0 & r21 { push(r21); }
PrepList21: PrepList20,r21 is prep26=1 & PrepList20 & r21 { push(r21); }
PrepList21: PrepList20 is prep26=0 & PrepList20 { }

PrepList22: r22 is prep25=1 & prep2627=0 & r22 { push(r22); }
PrepList22: PrepList21,r22 is prep25=1 & PrepList21 & r22 { push(r22); }
PrepList22: PrepList21 is prep25=0 & PrepList21 { }

PrepList23: r23 is prep24=1 & prep2527=0 & r23 { push(r23); }
PrepList23: PrepList22,r23 is prep24=1 & PrepList22 & r23 { push(r23); }
PrepList23: PrepList22 is prep24=0 & PrepList22 { }

PrepList24: r24 is prep31=1 & prep2427=0 & r24 { push(r24); }
PrepList24: PrepList23,r24 is prep31=1 & PrepList23 & r24 { push(r24); }
PrepList24: PrepList23 is prep31=0 & PrepList23 { }

PrepList25: r25 is prep30=1 & prep2427=0 & prep31=0 & r25 { push(r25); }
PrepList25: PrepList24,r25 is prep30=1 & PrepList24 & r25 { push(r25); }
PrepList25: PrepList24 is prep30=0 & PrepList24 { }

PrepList26: r26 is prep29=1 & prep2427=0 & prep3031=0 & r26 { push(r26); }
PrepList26: PrepList25,r26 is prep29=1 & PrepList25 & r26 { push(r26); }
PrepList26: PrepList25 is prep29=0 & PrepList25 { }

PrepList27: r27 is prep28=1 & prep2427=0 & prep2931=0 & r27 { push(r27); }
PrepList27: PrepList26,r27 is prep28=1 & PrepList26 & r27 { push(r27); }
PrepList27: PrepList26 is prep28=0 & PrepList26 { }

PrepList28: r28 is prep23=1 & prep2431=0 & r28 { push(r28); }
PrepList28: PrepList27,r28 is prep23=1 & PrepList27 & r28 { push(r28); }
PrepList28: PrepList27 is prep23=0 & PrepList27 { }

PrepList29: r29 is prep22=1 & prep2431=0 & prep23=0 & r29 { push(r29); }
PrepList29: PrepList28,r29 is prep22=1 & PrepList28 & r29 { push(r29); }
PrepList29: PrepList28 is prep22=0 & PrepList28 { }

PrepList30: ep is prep00=1 & prep2431=0 & prep2223=0 & ep { push(ep); }
PrepList30: PrepList29,ep is prep00=1 & PrepList29 & ep { push(ep); }
PrepList30: PrepList29 is prep00=0 & PrepList29 { }

PrepList: { lp } is prep21=1 & prep2431=0 & prep2223=0 & prep00=0 & lp { push(lp); }
PrepList: { PrepList30,lp } is prep21=1 & PrepList30 & lp { push(lp); }
PrepList: { PrepList30 } is prep21=0 & PrepList30 { push(lp); }
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DispList31: lp is prep21=1 & lp { pop(lp); }
DispList31: is prep21=0 { }

DispList30: ep,DispList31 is DispList31 & prep00=1 & ep { pop(ep); }
DispList30: DispList31 is DispList31 & prep00=0 { }

DispList29: r29,DispList30 is DispList30 & prep22=1 & r29 { pop(r29); }
DispList29: DispList30 is DispList30 & prep22=0 { }

DispList28: r28,DispList29 is DispList29 & prep23=1 & r28 { pop(r28); }
DispList28: DispList29 is DispList29 & prep23=0 { }

DispList27: r27,DispList28 is DispList28 & prep28=1 & r27 { pop(r27); }
DispList27: DispList28 is DispList28 & prep28=0 { }

DispList26: r26,DispList27 is DispList27 & prep29=1 & r26 { pop(r26); }
DispList26: DispList27 is DispList27 & prep29=0 { }

DispList25: r25,DispList26 is DispList26 & prep30=1 & r25 { pop(r25); }
DispList25: DispList26 is DispList26 & prep30=0 { }

DispList24: r24,DispList25 is DispList25 & prep31=1 & r24 { pop(r24); }
DispList24: DispList25 is DispList25 & prep31=0 { }

DispList23: r23,DispList24 is DispList24 & prep24=1 & r23 { pop(r23); }
DispList23: DispList24 is DispList24 & prep24=0 { }

DispList22: r22,DispList23 is DispList23 & prep25=1 & r22 { pop(r22); }
DispList22: DispList23 is DispList23 & prep25=0 { }

DispList21: r21,DispList22 is DispList22 & prep26=1 & r21 { pop(r21); }
DispList21: DispList22 is DispList22 & prep26=0 { }

DispList: { r20,DispList21 } is DispList21 & prep27=1 & r20 { pop(r20); }
DispList: { DispList21 } is DispList21 & prep27=0 { pop(r20); }
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