CD audio fixes

MegaCD.sv

@@ -477,6 +477,10 @@ hps_ext hps_ext
 (
 	.clk_sys(clk_sys),
 	.EXT_BUS(EXT_BUS),
+
+	.cd_data_ready(1),
+	.cdda_ready(MCD_CDDA_WR_READY),
+
 	.cd_in(cd_in),
 	.cd_out(cd_out)
 );
@@ -503,6 +507,7 @@ end
 wire rom_download = ioctl_download & (ioctl_index[5:0] <= 6'h01);
 wire cdc_dat_download = ioctl_download & (ioctl_index[5:0] == 6'h02);
 wire cdc_sub_download = ioctl_download & (ioctl_index[5:0] == 6'h03);
+wire cdc_cdda_download = ioctl_download & (ioctl_index[5:0] == 6'h04);
 wire save_download = ioctl_download & (ioctl_index[5:0] == 6'h05);
 wire code_download = ioctl_download & &ioctl_index;
 
@@ -708,6 +713,7 @@ wire [15:0] MCD_PCM_SL;
 wire [15:0] MCD_PCM_SR;
 wire [15:0] MCD_CDDA_SL;
 wire [15:0] MCD_CDDA_SR;
+wire        MCD_CDDA_WR_READY;
 
 wire [17:0] MCD_PRG_ADDR;
 wire [15:0] MCD_PRG_DO;
@@ -775,8 +781,10 @@ MCD MCD
 	.CDD_DM(scd_cdd_dm),
 
 	.CDC_DATA(cdc_d),
-	.CDC_DAT_WR(cdc_wr & cdc_dat_download),
+	.CDC_DAT_WR(cdc_wr & (cdc_dat_download | cdc_cdda_download)),
 	.CDC_SC_WR(cdc_wr & cdc_sub_download),
+	.CDC_CDDA_WR(cdc_wr & cdc_cdda_download),
+	.CDDA_WR_READY(MCD_CDDA_WR_READY),
 
 	.PCM_SL(MCD_PCM_SL),
 	.PCM_SR(MCD_PCM_SR),

rtl/MCD/CDDA.vhd

@@ -17,8 +17,8 @@ entity CD_DAC is
 		FD_DI			: in std_logic_vector(10 downto 0);
 		FD_WR			: in std_logic;
 
-		DM				: in std_logic;
-		
+		WR_READY 		: out std_logic;
+
 		SL				: out signed(15 downto 0);
 		SR				: out signed(15 downto 0)
 	);
@@ -46,6 +46,15 @@ architecture rtl of CD_DAC is
 
 	signal CDDA_REF   : integer;
 
+	component CDDA_FIFO
+		port (
+			CLK, nRESET, RD, WR         : in std_logic;
+			DIN                         : in std_logic_vector(31 downto 0);
+			EMPTY, FULL, WRITE_READY    : out std_logic;
+			Q                           : out std_logic_vector(31 downto 0)
+		);
+	end component;
+
 begin
 
 	EN <= ENABLE;
@@ -67,25 +76,28 @@ begin
 						FIFO_D(15 downto 0) <= CD_DI;
 					else
 						FIFO_D(31 downto 16) <= CD_DI;
-						if FULL = '0' and DM = '0' then
+						if FULL = '0' then
 							WR_REQ <= '1';
 						end if;
 					end if;
 				end if;
 			end if;
 		end if;
 	end process;
+
 
-	FIFO : entity work.CDDA_FIFO 
+	FIFO : CDDA_FIFO
 	port map(
-		clock		=> CLK,
-		data		=> FIFO_D,
-		wrreq		=> WR_REQ,
-		full		=> FULL,
-
-		rdreq		=> RD_REQ,
-		empty		=> EMPTY,
-		q			=> FIFO_Q
+		CLK          => CLK,
+		nRESET      => RST_N,
+		DIN         => FIFO_D,
+		WR          => WR_REQ,
+		FULL        => FULL,
+		WRITE_READY => WR_READY,
+
+		RD          => RD_REQ,
+		EMPTY       => EMPTY,
+		Q           => FIFO_Q
 	);
 
 	CDDA_REF <= 532034 when PALSW = '1' else 536931;

rtl/MCD/CDDA_FIFO.v

@@ -0,0 +1,71 @@
+module CDDA_FIFO
+(
+	input      CLK,
+	input      nRESET,
+	input      RD,
+	input      WR,
+	input      [31:0] DIN,
+	output     FULL,
+	output     EMPTY,
+	output     WRITE_READY,
+	output reg [31:0] Q
+
+);
+
+localparam SECTOR_SIZE = 2352*8/32;
+localparam BUFFER_AMOUNT = 5 * 1024*8/32;
+
+reg OLD_WRITE, OLD_READ;
+
+reg [12:0] FILLED_COUNT;
+reg [12:0] READ_ADDR, WRITE_ADDR;
+
+wire WRITE_REQ = ~OLD_WRITE & WR;
+wire READ_REQ = ~OLD_READ & RD;
+
+assign FULL = (FILLED_COUNT == BUFFER_AMOUNT);
+assign EMPTY = ~|FILLED_COUNT;
+assign WRITE_READY = (FILLED_COUNT <= (BUFFER_AMOUNT - SECTOR_SIZE)); // Ready to receive sector
+
+always @(posedge CLK or negedge nRESET) begin
+	if (~nRESET) begin
+		OLD_WRITE <= 0;
+		OLD_READ <= 0;
+		READ_ADDR <= 0;
+		WRITE_ADDR <= 0;
+		FILLED_COUNT <= 0;
+	end else begin
+		OLD_WRITE <= WR;
+		OLD_READ <= RD;
+
+		if (WRITE_REQ) begin
+			if (WRITE_ADDR == BUFFER_AMOUNT-1) begin
+				WRITE_ADDR <= 0;
+			end else begin
+				WRITE_ADDR <= WRITE_ADDR + 1'b1;
+			end
+		end
+
+		if (READ_REQ) begin
+			if (READ_ADDR == BUFFER_AMOUNT-1) begin
+				READ_ADDR <= 0;
+			end else begin
+				READ_ADDR <= READ_ADDR + 1'b1;
+			end
+			Q <= BUFFER_Q;
+		end
+
+		FILLED_COUNT <= FILLED_COUNT + WRITE_REQ - READ_REQ;
+	end
+end
+
+reg [31:0] BUFFER[BUFFER_AMOUNT];
+reg [31:0] BUFFER_Q;
+always @(posedge CLK) begin
+	BUFFER_Q <= BUFFER[READ_ADDR];
+	if (WRITE_REQ) begin
+		BUFFER[WRITE_ADDR] <= DIN;
+	end
+end
+
+endmodule

rtl/MCD/MCD.qip

@@ -4,6 +4,6 @@ set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ASIC_PKG.v
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) MC68K.vhd ]
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) CDC.vhd ]
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) CDDA.vhd ]
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) CDDA_FIFO.vhd ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) CDDA_FIFO.v ]
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) PCM.vhd ]
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) CDC.vhd ]

rtl/MCD/MCD.vhd

@@ -52,6 +52,8 @@ entity MCD is
 		CDC_DATA			: in std_logic_vector(15 downto 0);
 		CDC_DAT_WR		: in std_logic;
 		CDC_SC_WR		: in std_logic;
+		CDC_CDDA_WR		: in std_logic;
+		CDDA_WR_READY	: out std_logic;
 
 		PCM_SL			: out signed(15 downto 0);
 		PCM_SR			: out signed(15 downto 0);
@@ -423,12 +425,12 @@ begin
 		PALSW			=> PALSW,
 
 		CD_DI   		=> CDC_DATA,
-		CD_WR   		=> CDC_DAT_WR,
+		CD_WR   		=> CDC_CDDA_WR,
 
 		FD_DI   		=> ASIC_FD_DAT,
 		FD_WR   		=> ASIC_FD_WR,
 
-		DM   			=> CDD_DM,
+		WR_READY		=> CDDA_WR_READY,
 
 		SL   			=> CDDA_SL,
 		SR   			=> CDDA_SR