Skip to content

Commit

Permalink
fixup: lower to STORETPIDR2 pseudo
Browse files Browse the repository at this point in the history
  • Loading branch information
@SamTebbs33
SamTebbs33 committed Apr 2, 2024
1 parent 34f9e9c commit 19a7169
Show file tree
Hide file tree
Showing 9 changed files with 110 additions and 92 deletions.
23 changes: 22 additions & 1 deletion llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1121,9 +1121,30 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
default:
break;

case AArch64::STORETPIDR2: {
Register BufferAddr = MI.getOperand(0).getReg();
auto TPIDR2Object = MI.getOperand(1).getReg();
unsigned Offset = MI.getOperand(2).getImm();
// Store the buffer pointer to the TPIDR2 stack object.
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::STRXui))
.addReg(BufferAddr)
.addUse(TPIDR2Object)
.addImm(0 + Offset);
// Set the reserved bytes (10-15) to zero
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::STRHHui))
.addReg(AArch64::WZR)
.addUse(TPIDR2Object)
.addImm(5 + Offset);
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::STRWui))
.addReg(AArch64::WZR)
.addUse(TPIDR2Object)
.addImm(3 + Offset);
MI.eraseFromParent();
return true;
}

case AArch64::STACKALLOC: {
Register Dest = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
Register SPCopy = MI.getOperand(2).getReg();
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::SUBXrs), Dest)
.addReg(SPCopy)
Expand Down
26 changes: 4 additions & 22 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2974,30 +2974,12 @@ AArch64TargetLowering::EmitExpandZABuffer(MachineInstr &MI,
.addReg(SPCopy);
MFI.CreateVariableSizedObject(Align(16), nullptr);

// expand pseudo in expand pass or remove pseudo and remove stack object

unsigned TPIDR2Object = TPIDR2->FrameIndex;

Register Zero32 = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
MachineInstrBuilder Wzr =
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY), Zero32)
.addReg(AArch64::WZR);

// Store the buffer pointer to the TPIDR2 stack object.
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(AArch64::STRXui))
.addReg(BufferAddr)
.addFrameIndex(TPIDR2Object)
.addImm(0);
// Set the reserved bytes (10-15) to zero
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(AArch64::STRHHui))
.addReg(Wzr.getReg(0))
.addFrameIndex(TPIDR2Object)
.addImm(5);
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(AArch64::STRWui))
.addReg(Wzr.getReg(0))
.addFrameIndex(TPIDR2Object)
.addImm(3);

auto MI2 = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(AArch64::STORETPIDR2))
.addReg(BufferAddr)
.addFrameIndex(TPIDR2Object)
.addImm(0);
BB->remove_instr(&MI);
return BB;
}
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3633,6 +3633,7 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
case AArch64::LDRDui:
case AArch64::STRXui:
case AArch64::STRDui:
case AArch64::STORETPIDR2:
Scale = TypeSize::getFixed(8);
Width = TypeSize::getFixed(8);
MinOffset = 0;
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -980,6 +980,9 @@ include "SMEInstrFormats.td"
//===----------------------------------------------------------------------===//

let hasSideEffects = 1, isCodeGenOnly = 1 in {

def STORETPIDR2 : Pseudo<(outs), (ins GPR64:$addr, GPR64sp:$frameindex, i32imm:$offset), []>, Sched<[]>;

let Defs = [SP] in {

def STACKALLOC : Pseudo<(outs GPR64:$addr), (ins GPR64:$size, GPR64:$sp), []>, Sched<[]>;
Expand Down
44 changes: 24 additions & 20 deletions llvm/test/CodeGen/AArch64/sme-disable-gisel-fisel.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -222,9 +222,10 @@ define double @za_new_caller_to_za_shared_callee(double %x) nounwind noinline o
; CHECK-COMMON-NEXT: mov x9, sp
; CHECK-COMMON-NEXT: sub x8, x9, x8
; CHECK-COMMON-NEXT: mov sp, x8
; CHECK-COMMON-NEXT: stur x8, [x29, #-16]
; CHECK-COMMON-NEXT: sturh wzr, [x29, #-6]
; CHECK-COMMON-NEXT: stur wzr, [x29, #-4]
; CHECK-COMMON-NEXT: sub x9, x29, #16
; CHECK-COMMON-NEXT: str x8, [x9]
; CHECK-COMMON-NEXT: strh wzr, [x9, #10]
; CHECK-COMMON-NEXT: str wzr, [x9, #12]
; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
; CHECK-COMMON-NEXT: cbz x8, .LBB6_2
; CHECK-COMMON-NEXT: b .LBB6_1
Expand Down Expand Up @@ -260,9 +261,10 @@ define double @za_shared_caller_to_za_none_callee(double %x) nounwind noinline
; CHECK-COMMON-NEXT: mov x9, sp
; CHECK-COMMON-NEXT: sub x8, x9, x8
; CHECK-COMMON-NEXT: mov sp, x8
; CHECK-COMMON-NEXT: stur x8, [x29, #-16]
; CHECK-COMMON-NEXT: sturh wzr, [x29, #-6]
; CHECK-COMMON-NEXT: stur wzr, [x29, #-4]
; CHECK-COMMON-NEXT: sub x9, x29, #16
; CHECK-COMMON-NEXT: str x8, [x9]
; CHECK-COMMON-NEXT: strh wzr, [x9, #10]
; CHECK-COMMON-NEXT: str wzr, [x9, #12]
; CHECK-COMMON-NEXT: rdsvl x8, #1
; CHECK-COMMON-NEXT: sturh w8, [x29, #-8]
; CHECK-COMMON-NEXT: sub x8, x29, #16
Expand Down Expand Up @@ -302,13 +304,14 @@ define fp128 @f128_call_za(fp128 %a, fp128 %b) "aarch64_inout_za" nounwind {
; CHECK-COMMON-NEXT: mul x8, x8, x8
; CHECK-COMMON-NEXT: sub x8, x9, x8
; CHECK-COMMON-NEXT: mov sp, x8
; CHECK-COMMON-NEXT: stur x8, [x29, #-16]
; CHECK-COMMON-NEXT: rdsvl x8, #1
; CHECK-COMMON-NEXT: sub x9, x29, #16
; CHECK-COMMON-NEXT: sturh wzr, [x29, #-6]
; CHECK-COMMON-NEXT: stur wzr, [x29, #-4]
; CHECK-COMMON-NEXT: sturh w8, [x29, #-8]
; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x9
; CHECK-COMMON-NEXT: rdsvl x9, #1
; CHECK-COMMON-NEXT: sub x10, x29, #16
; CHECK-COMMON-NEXT: sub x11, x29, #16
; CHECK-COMMON-NEXT: str x8, [x11]
; CHECK-COMMON-NEXT: strh wzr, [x11, #10]
; CHECK-COMMON-NEXT: str wzr, [x11, #12]
; CHECK-COMMON-NEXT: sturh w9, [x29, #-8]
; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x10
; CHECK-COMMON-NEXT: bl __addtf3
; CHECK-COMMON-NEXT: smstart za
; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
Expand Down Expand Up @@ -366,13 +369,14 @@ define double @frem_call_za(double %a, double %b) "aarch64_inout_za" nounwind {
; CHECK-COMMON-NEXT: mul x8, x8, x8
; CHECK-COMMON-NEXT: sub x8, x9, x8
; CHECK-COMMON-NEXT: mov sp, x8
; CHECK-COMMON-NEXT: stur x8, [x29, #-16]
; CHECK-COMMON-NEXT: rdsvl x8, #1
; CHECK-COMMON-NEXT: sub x9, x29, #16
; CHECK-COMMON-NEXT: sturh wzr, [x29, #-6]
; CHECK-COMMON-NEXT: stur wzr, [x29, #-4]
; CHECK-COMMON-NEXT: sturh w8, [x29, #-8]
; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x9
; CHECK-COMMON-NEXT: rdsvl x9, #1
; CHECK-COMMON-NEXT: sub x10, x29, #16
; CHECK-COMMON-NEXT: sub x11, x29, #16
; CHECK-COMMON-NEXT: str x8, [x11]
; CHECK-COMMON-NEXT: strh wzr, [x11, #10]
; CHECK-COMMON-NEXT: str wzr, [x11, #12]
; CHECK-COMMON-NEXT: sturh w9, [x29, #-8]
; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x10
; CHECK-COMMON-NEXT: bl fmod
; CHECK-COMMON-NEXT: smstart za
; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
Expand Down
52 changes: 28 additions & 24 deletions llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,13 +16,14 @@ define void @test_lazy_save_1_callee() nounwind "aarch64_inout_za" {
; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x8, x9, x8
; CHECK-NEXT: mov sp, x8
; CHECK-NEXT: stur x8, [x29, #-16]
; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: sub x9, x29, #16
; CHECK-NEXT: sturh wzr, [x29, #-6]
; CHECK-NEXT: stur wzr, [x29, #-4]
; CHECK-NEXT: sturh w8, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x9
; CHECK-NEXT: rdsvl x9, #1
; CHECK-NEXT: sub x10, x29, #16
; CHECK-NEXT: sub x11, x29, #16
; CHECK-NEXT: str x8, [x11]
; CHECK-NEXT: strh wzr, [x11, #10]
; CHECK-NEXT: str wzr, [x11, #12]
; CHECK-NEXT: sturh w9, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: bl private_za_callee
; CHECK-NEXT: smstart za
; CHECK-NEXT: mrs x8, TPIDR2_EL0
Expand Down Expand Up @@ -54,9 +55,10 @@ define void @test_lazy_save_2_callees() nounwind "aarch64_inout_za" {
; CHECK-NEXT: mov sp, x8
; CHECK-NEXT: rdsvl x19, #1
; CHECK-NEXT: sub x20, x29, #16
; CHECK-NEXT: stur x8, [x29, #-16]
; CHECK-NEXT: sturh wzr, [x29, #-6]
; CHECK-NEXT: stur wzr, [x29, #-4]
; CHECK-NEXT: sub x9, x29, #16
; CHECK-NEXT: str x8, [x9]
; CHECK-NEXT: strh wzr, [x9, #10]
; CHECK-NEXT: str wzr, [x9, #12]
; CHECK-NEXT: sturh w19, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x20
; CHECK-NEXT: bl private_za_callee
Expand Down Expand Up @@ -100,13 +102,14 @@ define float @test_lazy_save_expanded_intrinsic(float %a) nounwind "aarch64_inou
; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x8, x9, x8
; CHECK-NEXT: mov sp, x8
; CHECK-NEXT: stur x8, [x29, #-16]
; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: sub x9, x29, #16
; CHECK-NEXT: sturh wzr, [x29, #-6]
; CHECK-NEXT: stur wzr, [x29, #-4]
; CHECK-NEXT: sturh w8, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x9
; CHECK-NEXT: rdsvl x9, #1
; CHECK-NEXT: sub x10, x29, #16
; CHECK-NEXT: sub x11, x29, #16
; CHECK-NEXT: str x8, [x11]
; CHECK-NEXT: strh wzr, [x11, #10]
; CHECK-NEXT: str wzr, [x11, #12]
; CHECK-NEXT: sturh w9, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: bl cosf
; CHECK-NEXT: smstart za
; CHECK-NEXT: mrs x8, TPIDR2_EL0
Expand Down Expand Up @@ -140,13 +143,14 @@ define void @test_lazy_save_and_conditional_smstart() nounwind "aarch64_inout_za
; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x8, x9, x8
; CHECK-NEXT: mov sp, x8
; CHECK-NEXT: stur x8, [x29, #-80]
; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: sub x9, x29, #80
; CHECK-NEXT: sturh wzr, [x29, #-70]
; CHECK-NEXT: stur wzr, [x29, #-68]
; CHECK-NEXT: sturh w8, [x29, #-72]
; CHECK-NEXT: msr TPIDR2_EL0, x9
; CHECK-NEXT: rdsvl x9, #1
; CHECK-NEXT: sub x10, x29, #80
; CHECK-NEXT: sub x11, x29, #80
; CHECK-NEXT: str x8, [x11]
; CHECK-NEXT: strh wzr, [x11, #10]
; CHECK-NEXT: str wzr, [x11, #12]
; CHECK-NEXT: sturh w9, [x29, #-72]
; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: bl __arm_sme_state
; CHECK-NEXT: and x19, x0, #0x1
; CHECK-NEXT: tbz w19, #0, .LBB3_2
Expand Down
30 changes: 16 additions & 14 deletions llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,13 +15,14 @@ define void @disable_tailcallopt() "aarch64_inout_za" nounwind {
; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x8, x9, x8
; CHECK-NEXT: mov sp, x8
; CHECK-NEXT: stur x8, [x29, #-16]
; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: sub x9, x29, #16
; CHECK-NEXT: sturh wzr, [x29, #-6]
; CHECK-NEXT: stur wzr, [x29, #-4]
; CHECK-NEXT: sturh w8, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x9
; CHECK-NEXT: rdsvl x9, #1
; CHECK-NEXT: sub x10, x29, #16
; CHECK-NEXT: sub x11, x29, #16
; CHECK-NEXT: str x8, [x11]
; CHECK-NEXT: strh wzr, [x11, #10]
; CHECK-NEXT: str wzr, [x11, #12]
; CHECK-NEXT: sturh w9, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: bl private_za_callee
; CHECK-NEXT: smstart za
; CHECK-NEXT: mrs x8, TPIDR2_EL0
Expand Down Expand Up @@ -50,13 +51,14 @@ define fp128 @f128_call_za(fp128 %a, fp128 %b) "aarch64_inout_za" nounwind {
; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x8, x9, x8
; CHECK-NEXT: mov sp, x8
; CHECK-NEXT: stur x8, [x29, #-16]
; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: sub x9, x29, #16
; CHECK-NEXT: sturh wzr, [x29, #-6]
; CHECK-NEXT: stur wzr, [x29, #-4]
; CHECK-NEXT: sturh w8, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x9
; CHECK-NEXT: rdsvl x9, #1
; CHECK-NEXT: sub x10, x29, #16
; CHECK-NEXT: sub x11, x29, #16
; CHECK-NEXT: str x8, [x11]
; CHECK-NEXT: strh wzr, [x11, #10]
; CHECK-NEXT: str wzr, [x11, #12]
; CHECK-NEXT: sturh w9, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: bl __addtf3
; CHECK-NEXT: smstart za
; CHECK-NEXT: mrs x8, TPIDR2_EL0
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/sme-za-lazy-save-buffer.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,9 +24,10 @@ define float @multi_bb_stpidr2_save_required(i32 %a, float %b, float %c) "aarch6
; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x8, x9, x8
; CHECK-NEXT: mov sp, x8
; CHECK-NEXT: stur x8, [x29, #-16]
; CHECK-NEXT: sturh wzr, [x29, #-6]
; CHECK-NEXT: stur wzr, [x29, #-4]
; CHECK-NEXT: sub x9, x29, #16
; CHECK-NEXT: str x8, [x9]
; CHECK-NEXT: strh wzr, [x9, #10]
; CHECK-NEXT: str wzr, [x9, #12]
; CHECK-NEXT: cbz w0, .LBB1_2
; CHECK-NEXT: // %bb.1: // %use_b
; CHECK-NEXT: fmov s1, #4.00000000
Expand All @@ -35,7 +36,6 @@ define float @multi_bb_stpidr2_save_required(i32 %a, float %b, float %c) "aarch6
; CHECK-NEXT: .LBB1_2: // %use_c
; CHECK-NEXT: fmov s0, s1
; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: sub x9, x29, #16
; CHECK-NEXT: sturh w8, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x9
; CHECK-NEXT: bl cosf
Expand Down
15 changes: 8 additions & 7 deletions llvm/test/CodeGen/AArch64/sme-zt0-state.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,12 +42,12 @@ define void @za_zt0_shared_caller_no_state_callee() "aarch64_inout_za" "aarch64_
; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x8, x9, x8
; CHECK-NEXT: mov sp, x8
; CHECK-NEXT: stur x8, [x29, #-16]
; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: sub x9, x29, #16
; CHECK-NEXT: sub x19, x29, #80
; CHECK-NEXT: sturh wzr, [x29, #-6]
; CHECK-NEXT: stur wzr, [x29, #-4]
; CHECK-NEXT: str x8, [x9]
; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: strh wzr, [x9, #10]
; CHECK-NEXT: str wzr, [x9, #12]
; CHECK-NEXT: sturh w8, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x9
; CHECK-NEXT: str zt0, [x19]
Expand Down Expand Up @@ -182,9 +182,10 @@ define void @new_za_zt0_caller() "aarch64_new_za" "aarch64_new_zt0" nounwind {
; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x8, x9, x8
; CHECK-NEXT: mov sp, x8
; CHECK-NEXT: stur x8, [x29, #-16]
; CHECK-NEXT: sturh wzr, [x29, #-6]
; CHECK-NEXT: stur wzr, [x29, #-4]
; CHECK-NEXT: sub x9, x29, #16
; CHECK-NEXT: str x8, [x9]
; CHECK-NEXT: strh wzr, [x9, #10]
; CHECK-NEXT: str wzr, [x9, #12]
; CHECK-NEXT: mrs x8, TPIDR2_EL0
; CHECK-NEXT: cbz x8, .LBB7_2
; CHECK-NEXT: // %bb.1: // %save.za
Expand Down

0 comments on commit 19a7169

Please sign in to comment.