optimize fetch logic

LoveLonelyTime · Jan 26, 2024 · 801883b · 801883b
1 parent cf8be2a
commit 801883b
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Showing 8 changed files with 349 additions and 285 deletions.
diff --git a/src/main/scala/lltriscv/core/Core.scala b/src/main/scala/lltriscv/core/Core.scala
@@ -186,7 +186,7 @@ class CoreFrontend(config: CoreConfig) extends Module {
   iCache.io.flush <> io.iCacheFlush
 
   // Fetch
-  fetch.io.satp := io.satp
+  fetch.io.asid := io.satp(30, 22)
   fetch.io.update <> io.predictorUpdate
   fetch.io.itlb <> itlb.io.request
   fetch.io.icache <> iCache.io.request

diff --git a/src/main/scala/lltriscv/core/DataType.scala b/src/main/scala/lltriscv/core/DataType.scala
@@ -27,3 +27,9 @@ object DataType {
   def asid = UInt(9.W) // 9-bits address space ID
   def aByte = UInt(8.W) // A Byte
 }
+
+object CoreConstant {
+  val XLEN = 32
+  val instructionLength = 4
+  val compressInstructionLength = 2
+}
diff --git a/src/main/scala/lltriscv/core/execute/Memory.scala b/src/main/scala/lltriscv/core/execute/Memory.scala
@@ -187,6 +187,7 @@ class MemoryExecuteStage extends Module {
   ) {
     io.out.bits.error := MemoryErrorCode.misaligned
   }
+  chisel3.util.BitPat
 
   io.out.bits.rd := inReg.rd
   io.out.bits.pc := inReg.pc

diff --git a/src/main/scala/lltriscv/core/fetch/BranchPredictor.scala b/src/main/scala/lltriscv/core/fetch/BranchPredictor.scala
@@ -11,7 +11,7 @@ abstract class BranchPredictor(depth: Int) extends Module {
 
   val io = IO(new Bundle {
     val asid = Input(DataType.asid)
-    val resuest = Flipped(new BranchPredictorRequestIO())
+    val request = Flipped(new BranchPredictorRequestIO())
     val update = Flipped(new BranchPredictorUpdateIO())
   })
 }
@@ -35,25 +35,25 @@ class TwoBitsBranchPredictor(depth: Int) extends BranchPredictor(depth) {
   // Output
   for (i <- 0 until 2) {
     // Default
-    io.resuest.out(i) := Mux(io.resuest.in(i).compress, io.resuest.in(i).pc + 2.U, io.resuest.in(i).pc + 4.U)
+    io.request.out(i) := Mux(io.request.in(i).compress, io.request.in(i).pc + 2.U, io.request.in(i).pc + 4.U)
     for (
       j <- 0 until depth;
       k <- 0 until 2
     ) {
-      when(io.resuest.in(i).pc === table(j)(k).pc && io.asid === table(j)(k).asid) {
+      when(io.request.in(i).pc === table(j)(k).pc && io.asid === table(j)(k).asid) {
         // Output logic table
         switch(table(j)(k).history) {
           is(History.NN) { // N
-            io.resuest.out(i) := Mux(io.resuest.in(i).compress, io.resuest.in(i).pc + 2.U, io.resuest.in(i).pc + 4.U)
+            io.request.out(i) := Mux(io.request.in(i).compress, io.request.in(i).pc + 2.U, io.request.in(i).pc + 4.U)
           }
           is(History.NT) { // T
-            io.resuest.out(i) := table(j)(k).address
+            io.request.out(i) := table(j)(k).address
           }
           is(History.TN) { // T
-            io.resuest.out(i) := table(j)(k).address
+            io.request.out(i) := table(j)(k).address
           }
           is(History.TT) { // T
-            io.resuest.out(i) := table(j)(k).address
+            io.request.out(i) := table(j)(k).address
           }
         }
       }