fix asid bugs

LoveLonelyTime · Feb 8, 2024 · 4ea4d3c · 4ea4d3c
1 parent 47de084
commit 4ea4d3c
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Showing 2 changed files with 2 additions and 1 deletion.
diff --git a/src/main/scala/lltriscv/core/record/TLB.scala b/src/main/scala/lltriscv/core/record/TLB.scala
@@ -93,6 +93,7 @@ class TLB(depth: Int, data: Boolean) extends Module {
     victim.uxwr := pte(4, 1)
     victim.v := pte(0)
     victim.mPage := mPage
+    victim.asid := io.satp(30, 22)
     victim.valid := true.B
   }
 

diff --git a/src/main/scala/lltriscv/core/retire/InstructionRetire.scala b/src/main/scala/lltriscv/core/retire/InstructionRetire.scala
@@ -212,7 +212,7 @@ class InstructionRetire(depth: Int) extends Module {
       io.predictorUpdate.entries(id).address := retireEntries(id).executeResult.real
     }
 
-    when(retireEntries(id).pc === "hc019a528".U) {
+    when(retireEntries(id).pc === "hc00146b4".U) {
       debugBreakpoint := true.B
     }
     when(debugBreakpoint) {