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grammar and header changes for SPV_INTEL_2d_block_io
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@bashbaug
bashbaug committed Dec 11, 2024
1 parent 3f17b2a commit c6b0272
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Showing 10 changed files with 228 additions and 3 deletions.
8 changes: 8 additions & 0 deletions include/spirv/unified1/spirv.bf
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Original file line number Diff line number Diff line change
Expand Up @@ -1284,6 +1284,9 @@ namespace Spv
GlobalVariableHostAccessINTEL = 6187,
GlobalVariableFPGADecorationsINTEL = 6189,
SubgroupBufferPrefetchINTEL = 6220,
Subgroup2DBlockIOINTEL = 6228,
Subgroup2DBlockTransformINTEL = 6229,
Subgroup2DBlockTransposeINTEL = 6230,
GroupUniformArithmeticKHR = 6400,
MaskedGatherScatterINTEL = 6427,
CacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2305,6 +2308,11 @@ namespace Spv
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpSubgroupBlockPrefetchINTEL = 6221,
OpSubgroup2DBlockLoadINTEL = 6231,
OpSubgroup2DBlockLoadTransformINTEL = 6232,
OpSubgroup2DBlockLoadTransposeINTEL = 6233,
OpSubgroup2DBlockPrefetchINTEL = 6234,
OpSubgroup2DBlockStoreINTEL = 6235,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down
120 changes: 117 additions & 3 deletions include/spirv/unified1/spirv.core.grammar.json
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Original file line number Diff line number Diff line change
Expand Up @@ -10131,6 +10131,100 @@
"capabilities" : [ "SubgroupBufferPrefetchINTEL" ],
"version" : "None"
},
{
"opname" : "OpSubgroup2DBlockLoadINTEL",
"class" : "Group",
"opcode" : 6231,
"operands" : [
{ "kind" : "IdRef", "name" : "'Element Size'" },
{ "kind" : "IdRef", "name" : "'Block Width'" },
{ "kind" : "IdRef", "name" : "'Block Height'" },
{ "kind" : "IdRef", "name" : "'Block Count'" },
{ "kind" : "IdRef", "name" : "'Src Base Pointer'" },
{ "kind" : "IdRef", "name" : "'Memory Width'" },
{ "kind" : "IdRef", "name" : "'Memory Height'" },
{ "kind" : "IdRef", "name" : "'Memory Pitch'" },
{ "kind" : "IdRef", "name" : "'Coordinate'" },
{ "kind" : "IdRef", "name" : "'Dst Pointer'" }
],
"capabilities" : [ "Subgroup2DBlockIOINTEL" ],
"version" : "None"
},
{
"opname" : "OpSubgroup2DBlockLoadTransformINTEL",
"class" : "Group",
"opcode" : 6232,
"operands" : [
{ "kind" : "IdRef", "name" : "'Element Size'" },
{ "kind" : "IdRef", "name" : "'Block Width'" },
{ "kind" : "IdRef", "name" : "'Block Height'" },
{ "kind" : "IdRef", "name" : "'Block Count'" },
{ "kind" : "IdRef", "name" : "'Src Base Pointer'" },
{ "kind" : "IdRef", "name" : "'Memory Width'" },
{ "kind" : "IdRef", "name" : "'Memory Height'" },
{ "kind" : "IdRef", "name" : "'Memory Pitch'" },
{ "kind" : "IdRef", "name" : "'Coordinate'" },
{ "kind" : "IdRef", "name" : "'Dst Pointer'" }
],
"capabilities" : [ "Subgroup2DBlockTransformINTEL" ],
"version" : "None"
},
{
"opname" : "OpSubgroup2DBlockLoadTransposeINTEL",
"class" : "Group",
"opcode" : 6233,
"operands" : [
{ "kind" : "IdRef", "name" : "'Element Size'" },
{ "kind" : "IdRef", "name" : "'Block Width'" },
{ "kind" : "IdRef", "name" : "'Block Height'" },
{ "kind" : "IdRef", "name" : "'Block Count'" },
{ "kind" : "IdRef", "name" : "'Src Base Pointer'" },
{ "kind" : "IdRef", "name" : "'Memory Width'" },
{ "kind" : "IdRef", "name" : "'Memory Height'" },
{ "kind" : "IdRef", "name" : "'Memory Pitch'" },
{ "kind" : "IdRef", "name" : "'Coordinate'" },
{ "kind" : "IdRef", "name" : "'Dst Pointer'" }
],
"capabilities" : [ "Subgroup2DBlockTransposeINTEL" ],
"version" : "None"
},
{
"opname" : "OpSubgroup2DBlockPrefetchINTEL",
"class" : "Group",
"opcode" : 6234,
"operands" : [
{ "kind" : "IdRef", "name" : "'Element Size'" },
{ "kind" : "IdRef", "name" : "'Block Width'" },
{ "kind" : "IdRef", "name" : "'Block Height'" },
{ "kind" : "IdRef", "name" : "'Block Count'" },
{ "kind" : "IdRef", "name" : "'Src Base Pointer'" },
{ "kind" : "IdRef", "name" : "'Memory Width'" },
{ "kind" : "IdRef", "name" : "'Memory Height'" },
{ "kind" : "IdRef", "name" : "'Memory Pitch'" },
{ "kind" : "IdRef", "name" : "'Coordinate'" }
],
"capabilities" : [ "Subgroup2DBlockIOINTEL" ],
"version" : "None"
},
{
"opname" : "OpSubgroup2DBlockStoreINTEL",
"class" : "Group",
"opcode" : 6235,
"operands" : [
{ "kind" : "IdRef", "name" : "'Element Size'" },
{ "kind" : "IdRef", "name" : "'Block Width'" },
{ "kind" : "IdRef", "name" : "'Block Height'" },
{ "kind" : "IdRef", "name" : "'Block Count'" },
{ "kind" : "IdRef", "name" : "'Src Pointer'" },
{ "kind" : "IdRef", "name" : "'Dst Base Pointer'" },
{ "kind" : "IdRef", "name" : "'Memory Width'" },
{ "kind" : "IdRef", "name" : "'Memory Height'" },
{ "kind" : "IdRef", "name" : "'Memory Pitch'" },
{ "kind" : "IdRef", "name" : "'Coordinate'" }
],
"capabilities" : [ "Subgroup2DBlockIOINTEL" ],
"version" : "None"
},
{
"opname" : "OpGroupIMulKHR",
"class" : "Group",
Expand Down Expand Up @@ -16588,6 +16682,26 @@
"extensions": [ "SPV_INTEL_subgroup_buffer_prefetch" ],
"version" : "None"
},
{
"enumerant" : "Subgroup2DBlockIOINTEL",
"value" : 6228,
"extensions": [ "SPV_INTEL_2d_block_io" ],
"version" : "None"
},
{
"enumerant" : "Subgroup2DBlockTransformINTEL",
"value" : 6229,
"capabilities" : [ "Subgroup2DBlockIOINTEL" ],
"extensions": [ "SPV_INTEL_2d_block_io" ],
"version" : "None"
},
{
"enumerant" : "Subgroup2DBlockTransposeINTEL",
"value" : 6230,
"capabilities" : [ "Subgroup2DBlockIOINTEL" ],
"extensions": [ "SPV_INTEL_2d_block_io" ],
"version" : "None"
},
{
"enumerant" : "GroupUniformArithmeticKHR",
"value" : 6400,
Expand All @@ -16596,9 +16710,9 @@
},
{
"enumerant" : "MaskedGatherScatterINTEL",
"value" : 6427,
"extensions" : [ "SPV_INTEL_masked_gather_scatter"],
"version" : "None"
"value" : 6427,
"extensions" : [ "SPV_INTEL_masked_gather_scatter"],
"version" : "None"
},
{
"enumerant" : "CacheControlsINTEL",
Expand Down
8 changes: 8 additions & 0 deletions include/spirv/unified1/spirv.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -1283,6 +1283,9 @@ public enum Capability
GlobalVariableHostAccessINTEL = 6187,
GlobalVariableFPGADecorationsINTEL = 6189,
SubgroupBufferPrefetchINTEL = 6220,
Subgroup2DBlockIOINTEL = 6228,
Subgroup2DBlockTransformINTEL = 6229,
Subgroup2DBlockTransposeINTEL = 6230,
GroupUniformArithmeticKHR = 6400,
MaskedGatherScatterINTEL = 6427,
CacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2304,6 +2307,11 @@ public enum Op
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpSubgroupBlockPrefetchINTEL = 6221,
OpSubgroup2DBlockLoadINTEL = 6231,
OpSubgroup2DBlockLoadTransformINTEL = 6232,
OpSubgroup2DBlockLoadTransposeINTEL = 6233,
OpSubgroup2DBlockPrefetchINTEL = 6234,
OpSubgroup2DBlockStoreINTEL = 6235,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down
21 changes: 21 additions & 0 deletions include/spirv/unified1/spirv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1254,6 +1254,9 @@ typedef enum SpvCapability_ {
SpvCapabilityGlobalVariableHostAccessINTEL = 6187,
SpvCapabilityGlobalVariableFPGADecorationsINTEL = 6189,
SpvCapabilitySubgroupBufferPrefetchINTEL = 6220,
SpvCapabilitySubgroup2DBlockIOINTEL = 6228,
SpvCapabilitySubgroup2DBlockTransformINTEL = 6229,
SpvCapabilitySubgroup2DBlockTransposeINTEL = 6230,
SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvCapabilityMaskedGatherScatterINTEL = 6427,
SpvCapabilityCacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2245,6 +2248,11 @@ typedef enum SpvOp_ {
SpvOpControlBarrierWaitINTEL = 6143,
SpvOpArithmeticFenceEXT = 6145,
SpvOpSubgroupBlockPrefetchINTEL = 6221,
SpvOpSubgroup2DBlockLoadINTEL = 6231,
SpvOpSubgroup2DBlockLoadTransformINTEL = 6232,
SpvOpSubgroup2DBlockLoadTransposeINTEL = 6233,
SpvOpSubgroup2DBlockPrefetchINTEL = 6234,
SpvOpSubgroup2DBlockStoreINTEL = 6235,
SpvOpGroupIMulKHR = 6401,
SpvOpGroupFMulKHR = 6402,
SpvOpGroupBitwiseAndKHR = 6403,
Expand Down Expand Up @@ -3015,6 +3023,11 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
case SpvOpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSubgroup2DBlockLoadINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSubgroup2DBlockLoadTransformINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSubgroup2DBlockLoadTransposeINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSubgroup2DBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
Expand Down Expand Up @@ -3946,6 +3959,9 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
case SpvCapabilityGlobalVariableHostAccessINTEL: return "GlobalVariableHostAccessINTEL";
case SpvCapabilityGlobalVariableFPGADecorationsINTEL: return "GlobalVariableFPGADecorationsINTEL";
case SpvCapabilitySubgroupBufferPrefetchINTEL: return "SubgroupBufferPrefetchINTEL";
case SpvCapabilitySubgroup2DBlockIOINTEL: return "Subgroup2DBlockIOINTEL";
case SpvCapabilitySubgroup2DBlockTransformINTEL: return "Subgroup2DBlockTransformINTEL";
case SpvCapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
case SpvCapabilityCacheControlsINTEL: return "CacheControlsINTEL";
Expand Down Expand Up @@ -4859,6 +4875,11 @@ inline const char* SpvOpToString(SpvOp value) {
case SpvOpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
case SpvOpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
case SpvOpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
case SpvOpSubgroup2DBlockLoadINTEL: return "OpSubgroup2DBlockLoadINTEL";
case SpvOpSubgroup2DBlockLoadTransformINTEL: return "OpSubgroup2DBlockLoadTransformINTEL";
case SpvOpSubgroup2DBlockLoadTransposeINTEL: return "OpSubgroup2DBlockLoadTransposeINTEL";
case SpvOpSubgroup2DBlockPrefetchINTEL: return "OpSubgroup2DBlockPrefetchINTEL";
case SpvOpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
case SpvOpGroupIMulKHR: return "OpGroupIMulKHR";
case SpvOpGroupFMulKHR: return "OpGroupFMulKHR";
case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
Expand Down
21 changes: 21 additions & 0 deletions include/spirv/unified1/spirv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1250,6 +1250,9 @@ enum Capability {
CapabilityGlobalVariableHostAccessINTEL = 6187,
CapabilityGlobalVariableFPGADecorationsINTEL = 6189,
CapabilitySubgroupBufferPrefetchINTEL = 6220,
CapabilitySubgroup2DBlockIOINTEL = 6228,
CapabilitySubgroup2DBlockTransformINTEL = 6229,
CapabilitySubgroup2DBlockTransposeINTEL = 6230,
CapabilityGroupUniformArithmeticKHR = 6400,
CapabilityMaskedGatherScatterINTEL = 6427,
CapabilityCacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2241,6 +2244,11 @@ enum Op {
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpSubgroupBlockPrefetchINTEL = 6221,
OpSubgroup2DBlockLoadINTEL = 6231,
OpSubgroup2DBlockLoadTransformINTEL = 6232,
OpSubgroup2DBlockLoadTransposeINTEL = 6233,
OpSubgroup2DBlockPrefetchINTEL = 6234,
OpSubgroup2DBlockStoreINTEL = 6235,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down Expand Up @@ -3011,6 +3019,11 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
case OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case OpSubgroup2DBlockLoadINTEL: *hasResult = false; *hasResultType = false; break;
case OpSubgroup2DBlockLoadTransformINTEL: *hasResult = false; *hasResultType = false; break;
case OpSubgroup2DBlockLoadTransposeINTEL: *hasResult = false; *hasResultType = false; break;
case OpSubgroup2DBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
Expand Down Expand Up @@ -3942,6 +3955,9 @@ inline const char* CapabilityToString(Capability value) {
case CapabilityGlobalVariableHostAccessINTEL: return "GlobalVariableHostAccessINTEL";
case CapabilityGlobalVariableFPGADecorationsINTEL: return "GlobalVariableFPGADecorationsINTEL";
case CapabilitySubgroupBufferPrefetchINTEL: return "SubgroupBufferPrefetchINTEL";
case CapabilitySubgroup2DBlockIOINTEL: return "Subgroup2DBlockIOINTEL";
case CapabilitySubgroup2DBlockTransformINTEL: return "Subgroup2DBlockTransformINTEL";
case CapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
case CapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
case CapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
case CapabilityCacheControlsINTEL: return "CacheControlsINTEL";
Expand Down Expand Up @@ -4855,6 +4871,11 @@ inline const char* OpToString(Op value) {
case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
case OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
case OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
case OpSubgroup2DBlockLoadINTEL: return "OpSubgroup2DBlockLoadINTEL";
case OpSubgroup2DBlockLoadTransformINTEL: return "OpSubgroup2DBlockLoadTransformINTEL";
case OpSubgroup2DBlockLoadTransposeINTEL: return "OpSubgroup2DBlockLoadTransposeINTEL";
case OpSubgroup2DBlockPrefetchINTEL: return "OpSubgroup2DBlockPrefetchINTEL";
case OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
case OpGroupIMulKHR: return "OpGroupIMulKHR";
case OpGroupFMulKHR: return "OpGroupFMulKHR";
case OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
Expand Down
21 changes: 21 additions & 0 deletions include/spirv/unified1/spirv.hpp11
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Original file line number Diff line number Diff line change
Expand Up @@ -1250,6 +1250,9 @@ enum class Capability : unsigned {
GlobalVariableHostAccessINTEL = 6187,
GlobalVariableFPGADecorationsINTEL = 6189,
SubgroupBufferPrefetchINTEL = 6220,
Subgroup2DBlockIOINTEL = 6228,
Subgroup2DBlockTransformINTEL = 6229,
Subgroup2DBlockTransposeINTEL = 6230,
GroupUniformArithmeticKHR = 6400,
MaskedGatherScatterINTEL = 6427,
CacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2241,6 +2244,11 @@ enum class Op : unsigned {
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpSubgroupBlockPrefetchINTEL = 6221,
OpSubgroup2DBlockLoadINTEL = 6231,
OpSubgroup2DBlockLoadTransformINTEL = 6232,
OpSubgroup2DBlockLoadTransposeINTEL = 6233,
OpSubgroup2DBlockPrefetchINTEL = 6234,
OpSubgroup2DBlockStoreINTEL = 6235,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down Expand Up @@ -3011,6 +3019,11 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
case Op::OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSubgroup2DBlockLoadINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSubgroup2DBlockLoadTransformINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSubgroup2DBlockLoadTransposeINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSubgroup2DBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
Expand Down Expand Up @@ -3942,6 +3955,9 @@ inline const char* CapabilityToString(Capability value) {
case Capability::GlobalVariableHostAccessINTEL: return "GlobalVariableHostAccessINTEL";
case Capability::GlobalVariableFPGADecorationsINTEL: return "GlobalVariableFPGADecorationsINTEL";
case Capability::SubgroupBufferPrefetchINTEL: return "SubgroupBufferPrefetchINTEL";
case Capability::Subgroup2DBlockIOINTEL: return "Subgroup2DBlockIOINTEL";
case Capability::Subgroup2DBlockTransformINTEL: return "Subgroup2DBlockTransformINTEL";
case Capability::Subgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
case Capability::GroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
case Capability::MaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
case Capability::CacheControlsINTEL: return "CacheControlsINTEL";
Expand Down Expand Up @@ -4855,6 +4871,11 @@ inline const char* OpToString(Op value) {
case Op::OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
case Op::OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
case Op::OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
case Op::OpSubgroup2DBlockLoadINTEL: return "OpSubgroup2DBlockLoadINTEL";
case Op::OpSubgroup2DBlockLoadTransformINTEL: return "OpSubgroup2DBlockLoadTransformINTEL";
case Op::OpSubgroup2DBlockLoadTransposeINTEL: return "OpSubgroup2DBlockLoadTransposeINTEL";
case Op::OpSubgroup2DBlockPrefetchINTEL: return "OpSubgroup2DBlockPrefetchINTEL";
case Op::OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
case Op::OpGroupIMulKHR: return "OpGroupIMulKHR";
case Op::OpGroupFMulKHR: return "OpGroupFMulKHR";
case Op::OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
Expand Down
8 changes: 8 additions & 0 deletions include/spirv/unified1/spirv.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1226,6 +1226,9 @@
"GlobalVariableHostAccessINTEL": 6187,
"GlobalVariableFPGADecorationsINTEL": 6189,
"SubgroupBufferPrefetchINTEL": 6220,
"Subgroup2DBlockIOINTEL": 6228,
"Subgroup2DBlockTransformINTEL": 6229,
"Subgroup2DBlockTransposeINTEL": 6230,
"GroupUniformArithmeticKHR": 6400,
"MaskedGatherScatterINTEL": 6427,
"CacheControlsINTEL": 6441,
Expand Down Expand Up @@ -2238,6 +2241,11 @@
"OpControlBarrierWaitINTEL": 6143,
"OpArithmeticFenceEXT": 6145,
"OpSubgroupBlockPrefetchINTEL": 6221,
"OpSubgroup2DBlockLoadINTEL": 6231,
"OpSubgroup2DBlockLoadTransformINTEL": 6232,
"OpSubgroup2DBlockLoadTransposeINTEL": 6233,
"OpSubgroup2DBlockPrefetchINTEL": 6234,
"OpSubgroup2DBlockStoreINTEL": 6235,
"OpGroupIMulKHR": 6401,
"OpGroupFMulKHR": 6402,
"OpGroupBitwiseAndKHR": 6403,
Expand Down
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