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@Kaveesha-98
Kaveesha-98 committed Apr 20, 2023
1 parent 61d964c commit a16d5b6
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Showing 95 changed files with 10,515 additions and 485 deletions.
11 changes: 10 additions & 1 deletion .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -19,4 +19,13 @@ cpu-test/cpuTestbench
verilator-tests/dCache/dCache
verilator-tests/testbench/testbench
.fuse_hidden0000465a000000ff
verilator-tests/testbench/binToHex
verilator-tests/testbench/binToHex
verilator-tests/testbench/target_texts
verilator-tests/testbench/objectfiles
verilator-tests/testbench/elffiles
verilator-tests/testbench/dumps
verilator-tests/testbench/programs/build
!vivado/riscv_rob/riscv_rob.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
!vivado/riscv_rob/riscv_rob.srcs/sources_1/imports/FYP-18-RISCV-Core/*.v
!vivado/riscv_rob/riscv_rob.srcs/sim_1/tb.v
!verilog_srcs/*.v
15 changes: 10 additions & 5 deletions src/main/resources/dCacheRegisters.v
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Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,9 @@ module dCacheRegisters #(
localparam block_size = 1 << double_word_offset_width // double words per block
) (
input [31:0] address,
output [63:0] byte_aligned_data,
output [tag_width-1: 0] tag,
output tag_valid,
output reg [63:0] byte_aligned_data,
output reg [tag_width-1: 0] tag,
output reg tag_valid,
input [line_width-1:0] write_line_index,
input [64*block_size - 1:0] write_block,
input [tag_width-1: 0] write_tag,
Expand All @@ -20,9 +20,14 @@ module dCacheRegisters #(
reg [tag_width-1:0] tags [cache_depth-1:0];
reg validBits [cache_depth-1:0];

assign byte_aligned_data = cache[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]][address[double_word_offset_width-1 + 3:3]];
always @(posedge clock) begin
byte_aligned_data <= cache[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]][address[double_word_offset_width-1 + 3:3]];
tag <= tags[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]];
tag_valid <= validBits[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]];
end
/* assign byte_aligned_data = cache[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]][address[double_word_offset_width-1 + 3:3]];
assign tag = tags[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]];
assign tag_valid = validBits[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]];
assign tag_valid = validBits[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]]; */

always @(posedge clock) begin
if (reset) begin
Expand Down
560 changes: 253 additions & 307 deletions src/main/scala/cache/dCache.scala
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4 changes: 2 additions & 2 deletions src/main/scala/common/Fifo.scala
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Expand Up @@ -93,7 +93,7 @@ class randomAccessFifo[T <: Data ]( gen: T, depth: Int) extends Fifo(gen:
}

io.deq.bits := memReg(readPtr)
io.enq.ready := !fullReg
io.enq.ready := !fullReg | (io.deq.valid & io.deq.ready)
io.deq.valid := !emptyReg
//printf(p"$io\n")
}
Expand Down Expand Up @@ -136,7 +136,7 @@ class regFifo[T <: Data ]( gen: T, depth: Int) extends Fifo(gen:
}

io.deq.bits := memReg(readPtr)
io.enq.ready := !fullReg
io.enq.ready := !fullReg | (io.deq.valid & io.deq.ready)
io.deq.valid := !emptyReg
//printf(p"$io\n")
}
4 changes: 2 additions & 2 deletions src/main/scala/common/configuration.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@ import chisel3.experimental.IO

object coreConfiguration {
val robAddrWidth = 3
val ramBaseAddress = 0x00100000
val ramHighAddress = 0x1FFFFFFF
val ramBaseAddress = 0x0000000000100000L
val ramHighAddress = 0x000000001FFFFFFFL
val iCacheOffsetWidth = 2
val iCacheLineWidth = 6
val iCacheTagWidth = 32 - iCacheLineWidth - iCacheOffsetWidth - 2
Expand Down
24 changes: 12 additions & 12 deletions src/main/scala/common/ports.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -154,8 +154,8 @@ class pullCommitFrmRob extends composableInterface {
val robAddr = Input(UInt(robAddrWidth.W))
val rdAddr = Input(UInt(5.W))
val writeBackData = Input(UInt(64.W)) // mtval when exceptionOccured
/* Additional wires when exception handling is added
val execptionOccured = Input(Bool())
//Additional wires when exception handling is added
/* val execptionOccured = Input(Bool())
val mcause = Input(UInt(64.W))
val mepc = Input(UInt(64.W)) */
}
Expand All @@ -169,9 +169,10 @@ class pullCommitFrmRob extends composableInterface {
class commitInstruction extends composableInterface {
val robAddr = Output(UInt(robAddrWidth.W))
val rdAddr = Output(UInt(5.W))
val opcode = Output(UInt(7.W))
val writeBackData = Output(UInt(64.W)) // mtval when exceptionOccured
/* Additional wires when exception handling is added
val execptionOccured = Output(Bool())
// Additional wires when exception handling is added
/* val execptionOccured = Output(Bool())
val mcause = Output(UInt(64.W))
val mepc = Output(UInt(64.W)) */
}
Expand Down Expand Up @@ -228,8 +229,8 @@ class robAllocate extends composableInterface {
val value = Output(UInt(64.W))
val robAddr = Input(UInt(robAddrWidth.W))
}
/* Wire added to handle exceptions
val pc = Input(UInt(32.W)) // to provide mepc when exception are reported */
//Wire added to handle exceptions
//val pc = Input(UInt(32.W)) // to provide mepc when exception are reported
}

/**
Expand Down Expand Up @@ -302,8 +303,8 @@ val instruction = Input(UInt(32.W))
class pushExecResultToRob extends composableInterface {
val robAddr = Output(UInt(robAddrWidth.W))
val execResult = Output(UInt(64.W)) // mtval when exceptionOccured
/* Additional wires when exception handling is added
val execptionOccured = Output(Bool())
// Additional wires when exception handling is added
/* val execptionOccured = Output(Bool())
val mcause = Output(UInt(64.W))
val mepc = Output(UInt(64.W)) */
}
Expand All @@ -316,10 +317,9 @@ class pushExecResultToRob extends composableInterface {
class pullExecResultToRob extends composableInterface {
val robAddr = Input(UInt(robAddrWidth.W))
val execResult = Input(UInt(64.W)) // mtval when exceptionOccured
/* Additional wires when exception handling is added
val execptionOccured = Input(Bool())
val mcause = Input(UInt(64.W))
val mepc = Input(UInt(64.W)) */
// Additional wires when exception handling is added
/* val execeptionOccured = Input(Bool())
val mcause = Input(UInt(64.W)) */
}
/*******************************************************************/

Expand Down
10 changes: 5 additions & 5 deletions src/main/scala/core.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -58,8 +58,8 @@ class core extends Module {
_ := (decode.writeBackResult.ready && rob.commit.ready)
)
// these connections are incorrect an need to be fixed
decode.writeBackResult.rdAddr := rob.commit.rd
decode.writeBackResult.writeBackData := rob.commit.value
decode.writeBackResult.rdAddr := rob.commit.rdAddr
decode.writeBackResult.writeBackData := rob.commit.writeBackData
decode.writeBackResult.robAddr := rob.commit.robAddr
// opcode is left dangling for the moment

Expand Down Expand Up @@ -109,12 +109,12 @@ class core extends Module {
Seq(rob.fromMem.fired, memAccess.toRob.fired).foreach(
_ := (rob.fromMem.ready && memAccess.toRob.ready)
)
rob.fromMem.execResult := memAccess.toRob.writeBackData
rob.fromMem.writeBackData := memAccess.toRob.writeBackData
rob.fromMem.robAddr := memAccess.toRob.robAddr

val dcache = Module(new pipeline.memAccess.cache.dCache)
val dPort = IO(dcache.lowLevelAXI.cloneType)
dPort <> dcache.lowLevelAXI
val dPort = IO(dcache.lowLevelMem.cloneType)
dPort <> dcache.lowLevelMem

memAccess.dCache <> dcache.pipelineMemAccess

Expand Down
31 changes: 30 additions & 1 deletion src/main/scala/coreTestbench.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,30 @@ class testbench extends Module {
//Mux(ports(servicing).RVALID && ports(servicing).RREADY && (serviceState === reading), mem.read(readRequest.address + 4.U + i.U), mem.read(readRequest.address + i.U))
).reverse)

val wready, bvalid = RegInit(false.B)
val awready = RegInit(true.B)
val waddr = Reg(UInt(32.W))

when(programRunning) {
when(ports(data).AWVALID && ports(data).AWREADY) { waddr <= ports(data).AWADDR }
.elsewhen(ports(data).WREADY && ports(data).WVALID) { waddr <= waddr + 4.U }

when(awready) { awready := !ports(data).AWVALID }
.otherwise { awready := (ports(data).BVALID && ports(data).BREADY) }

when(wready) { wready := !(ports(data).WVALID && ports(data).WLAST) }
.otherwise { wready := ports(data).AWVALID && ports(data).AWREADY }

when(bvalid) { bvalid := !ports(data).BREADY }
.otherwise { bvalid := ports(data).WLAST && ports(data).WVALID && ports(data).WREADY }

when(ports(data).WVALID && ports(data).WREADY) {
(0 until 4).foreach( i => {
when(ports(data).WSTRB(i).asBool) { mem.write(waddr + i.U, ports(data).WDATA(7 + 8*i, 8*i)) }
})
}
}

Seq(inst, data).foreach( interface => {
ports(interface).ARREADY := ((serviceState === waiting) && (servicing === interface) && programRunning)
ports(interface).RVALID := ((serviceState === reading) && (servicing === interface))
Expand All @@ -82,6 +106,11 @@ class testbench extends Module {
ports(interface).BVALID := false.B
ports(interface).BRESP := 0.U
})
ports(data).AWREADY := awready
ports(data).WREADY := wready
ports(data).BID := 0.U
ports(data).BVALID := bvalid
ports(data).BRESP := 0.U

val testResult = RegInit((new Bundle {
val valid = Bool()
Expand All @@ -98,7 +127,7 @@ class testbench extends Module {
dut.peripheral.WREADY := wreadyP
dut.peripheral.BVALID := bvalidP

when(dut.peripheral.AWVALID && dut.peripheral.AWVALID) { awreadyP := false.B }
when(dut.peripheral.AWVALID && dut.peripheral.AWREADY) { awreadyP := false.B }
.elsewhen(dut.peripheral.BVALID && dut.peripheral.BREADY) { awreadyP := true.B }

when(dut.peripheral.AWVALID && dut.peripheral.AWREADY) { wreadyP := true.B }
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/decode/constants.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -33,5 +33,5 @@ object constants {
val rdWidth = 5
val opcodeWidth = 7

val initialPC = "h7ffffffc" // h80000000 - 4
val initialPC = "h000ffffc" // h80000000 - 4
}
106 changes: 56 additions & 50 deletions src/main/scala/decode/decode.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -118,11 +118,11 @@ class decode extends Module {
))
val isFetchBranch = WireDefault(false.B) /** Branch instruction in fetchIssueBuffer */

// val isCSR = WireDefault(false.B)
// val waitToCommit = WireDefault(false.B)
// val csrDone = RegInit(false.B)
// val issueRobBuff = RegInit(0.U(robAddrWidth.W))
// val commitRobBuf = RegInit(0.U(robAddrWidth.W))
val isCSR = WireDefault(false.B)
val waitToCommit = WireDefault(false.B)
val csrDone = RegInit(false.B)
val issueRobBuff = RegInit(0.U(robAddrWidth.W))
val commitRobBuf = RegInit(0.U(robAddrWidth.W))

/** Initializing states for the FSMs for fetch buffer and decode buffer */
val emptyState :: fullState :: Nil = Enum(2) /** States of FSM */
Expand Down Expand Up @@ -212,13 +212,13 @@ class decode extends Module {
val robFile = Reg(Vec(regCount, UInt(robAddrWidth.W)))

/** Setting rs1 properties */
when(opcode === auipc.U || opcode === jump.U || opcode === jumpr.U) {
when(opcode === auipc.U || opcode === jump.U) {
rs1.data := pc
rs1.robAddr := 0.U
valid.rs1Data := true.B
valid.rs1RobAddr := false.B
}
when(opcode === load.U || opcode === store.U || opcode === rops.U || opcode === iops.U || opcode === rops32.U || opcode === iops32.U || opcode === cjump.U) {
when(opcode === load.U || opcode === store.U || opcode === rops.U || opcode === iops.U || opcode === rops32.U || opcode === iops32.U || opcode === cjump.U || opcode === jumpr.U || opcode === amos.U) {
rs1.data := registerFile(rs1Addr)
rs1.robAddr := robFile(rs1Addr)
when(stateRegDecodeBuf === fullState) { /** Check dependencies in adjacent instrucitons */
Expand All @@ -231,7 +231,13 @@ class decode extends Module {
}

/** Setting rs2 properties */
when(opcode === jumpr.U || opcode === jump.U) {
when(opcode === jumpr.U) {
rs2.data := pc
rs2.robAddr := 0.U
valid.rs2Data := true.B
valid.rs2RobAddr := false.B
}
when(opcode === jump.U) {
rs2.data := 4.U
rs2.robAddr := 0.U
valid.rs2Data := true.B
Expand All @@ -256,7 +262,7 @@ class decode extends Module {
}

/** Setting rs2 properties for store instructions */
when(opcode === store.U) {
when(opcode === store.U || opcode === amos.U) {
write.data := registerFile(rs2Addr)
write.robAddr := robFile(rs2Addr)
when(stateRegDecodeBuf === fullState) { /** Check dependencies in adjacent instrucitons */
Expand All @@ -275,7 +281,7 @@ class decode extends Module {
validBit(writeBackResult.rdAddr) := 1.U
robValidBit(writeBackResult.rdAddr) := 0.U
}
// commitRobBuf := writeBackResult.robAddr
commitRobBuf := writeBackResult.robAddr
}

/** Rob File writing and deasserting valid bit for rd */
Expand All @@ -284,7 +290,7 @@ class decode extends Module {
robFile(decodeIssueBuffer.instruction(11,7)) := toExec.robAddr
robValidBit(decodeIssueBuffer.instruction(11,7)) := 1.U
validBit(decodeIssueBuffer.instruction(11,7)) := 0.U
// issueRobBuff := toExec.robAddr
issueRobBuff := toExec.robAddr
}
}

Expand All @@ -308,11 +314,11 @@ class decode extends Module {
}
}
is(fullState) {
when(stalled /* || (isCSR && !csrDone)*/) {
when(stalled || (isCSR && !csrDone)) {
validOutFetchBuf := false.B
readyOutFetchBuf := false.B
} otherwise {
validOutFetchBuf := true.B /* !csrDone */
validOutFetchBuf := !csrDone
when(readyOutDecodeBuf) {
readyOutFetchBuf := true.B
when(!fromFetch.fired || fromFetch.pc =/= fromFetch.expected.pc) {
Expand Down Expand Up @@ -390,47 +396,47 @@ class decode extends Module {

/** CSR handling */
/**--------------------------------------------------------------------------------------------------------------------*/
// isCSR := (opcode === system.U) && (fun3 === "b001".U || fun3 === "b010".U || fun3 === "b011".U || fun3 === "b101".U || fun3 === "b110".U || fun3 === "b111".U)
// waitToCommit := isCSR && (issueRobBuff =/= commitRobBuf) && !csrDone
//
// val csrFile = RegInit(VecInit(Seq.fill(csrRegCount)(0.U(64.W))))
//
// when(isCSR && !waitToCommit) {
// val csrReadData = csrFile(immediate)
// val csrWriteData = registerFile(rs1Addr)
// val csrWriteImmediate = rs1Addr & "h0000_0000_0000_001f".U
// registerFile(writeBackResult.rdAddr) := csrReadData
// switch(fun3) {
// is("b001".U) {
// csrFile(immediate) := csrWriteData
// }
// is("b010".U) {
// csrFile(immediate) := csrReadData | csrWriteData
// }
// is("b011".U) {
// csrFile(immediate) := csrReadData & (~csrWriteData)
// }
// is("b101".U) {
// csrFile(immediate) := csrWriteImmediate
// }
// is("b110".U) {
// csrFile(immediate) := csrReadData | csrWriteImmediate
// }
// is("b111".U) {
// csrFile(immediate) := csrReadData & (~csrWriteImmediate)
// }
// }
// csrDone := true.B
// }
//
// when(csrDone && fromFetch.fired && fromFetch.pc === fromFetch.expected.pc) {
// csrDone := false.B
// }
/* isCSR := (opcode === system.U) && (fun3 === "b001".U || fun3 === "b010".U || fun3 === "b011".U || fun3 === "b101".U || fun3 === "b110".U || fun3 === "b111".U)
waitToCommit := isCSR && (issueRobBuff =/= commitRobBuf) && !csrDone
val csrFile = RegInit(VecInit(Seq.fill(csrRegCount)(0.U(64.W))))
when(isCSR && !waitToCommit) {
val csrReadData = csrFile(immediate)
val csrWriteData = registerFile(rs1Addr)
val csrWriteImmediate = rs1Addr & "h0000_0000_0000_001f".U
registerFile(writeBackResult.rdAddr) := csrReadData
switch(fun3) {
is("b001".U) {
csrFile(immediate) := csrWriteData
}
is("b010".U) {
csrFile(immediate) := csrReadData | csrWriteData
}
is("b011".U) {
csrFile(immediate) := csrReadData & (~csrWriteData)
}
is("b101".U) {
csrFile(immediate) := csrWriteImmediate
}
is("b110".U) {
csrFile(immediate) := csrReadData | csrWriteImmediate
}
is("b111".U) {
csrFile(immediate) := csrReadData & (~csrWriteImmediate)
}
}
csrDone := true.B
}
when(csrDone && fromFetch.fired && fromFetch.pc === fromFetch.expected.pc) {
csrDone := false.B
}
*/

/**--------------------------------------------------------------------------------------------------------------------*/
}

object DecodeUnit extends App{
emitVerilog(new decode())
}
}
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