SPI Slave with Multichip Support

KULeuven-MICAS · Dec 3, 2024 · 50f8e80 · 50f8e80
1 parent 4e1a7eb
commit 50f8e80
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Showing 2 changed files with 15 additions and 1 deletion.
diff --git a/axi_spi_slave.sv b/axi_spi_slave.sv
@@ -15,6 +15,8 @@ module axi_spi_slave #(
     parameter AXI_ID_WIDTH   = 3,
     parameter DUMMY_CYCLES   = 32
 ) (
+    // SPI Interface
+    //***************************************
     input  logic test_mode,
     input  logic spi_sclk,
     input  logic spi_cs,
@@ -31,6 +33,10 @@ module axi_spi_slave #(
     output logic spi_sdo2,
     output logic spi_sdo3,
 
+    // Chip ID for Multichip Environment
+    //***************************************
+    input logic [                7:0] chip_id,
+
     // AXI4 MASTER
     //***************************************
     input  logic                      axi_aclk,
@@ -196,7 +202,11 @@ module axi_spi_slave #(
 
   generate
     if (AXI_ADDR_WIDTH > 32) begin : gen_axi_addr_width_msb_assign
-      assign ctrl_addr[AXI_ADDR_WIDTH-1:32] = '0;
+      // First Part: MSB is assigned with chip_id
+      assign ctrl_addr[AXI_ADDR_WIDTH-1:AXI_ADDR_WIDTH-8] = chip_id;
+      // Second Part: until 32th bits are zero
+      assign ctrl_addr[AXI_ADDR_WIDTH-8-1:32] = '0;
+      // Third Part: the 32 LSB bits are assigned by the controller (actual address)
     end
   endgenerate
 

diff --git a/occamy_spi_slave.sv b/occamy_spi_slave.sv
@@ -10,6 +10,7 @@ module occamy_spi_slave #(
 ) (
     input  logic          clk_i,
     input  logic          rst_ni,
+    input  logic [7:0]    chip_id_i,
     output axi_lite_req_t axi_lite_req_o,
     input  axi_lite_rsp_t axi_lite_rsp_i,
 
@@ -45,6 +46,9 @@ module occamy_spi_slave #(
       .spi_oen2_o(spi_oen_o[2]),
       .spi_oen3_o(spi_oen_o[3]),
 
+      // Chip ID
+      .chip_id(chip_id_i),
+
       // AXI4 MASTER
       .axi_aclk(clk_i),
       .axi_aresetn(rst_ni),