Update SW for FPGA Test (#109)

* Update GeMM+XDMA Software

* Fix SW Bugs

* \n -> \r\n

* Delete unnecessary hemaia hjson and update ci

* Modify the default cfg hjson file

.github/workflows/ci.yml

@@ -52,10 +52,10 @@ jobs:
       - name: Compile SW
         run: |
           echo "Compiling SW"
-          make sw CFG_OVERRIDE=target/sw/cfg/hemaia.hjson -j$(nproc)
+          make sw CFG_OVERRIDE=target/sw/cfg/hemaia_ci.hjson -j$(nproc)
       - name: Compile RTL
         run: |
-          make rtl CFG_OVERRIDE=target/rtl/cfg/hemaia.hjson
+          make rtl CFG_OVERRIDE=target/rtl/cfg/hemaia_ci.hjson
       - name: Compile Verilator Binary
         run: |
           make occamy_system_vlt -j$(nproc)

Makefile

@@ -6,7 +6,7 @@
 MKFILE_PATH := $(abspath $(lastword $(MAKEFILE_LIST)))
 MKFILE_DIR := $(dir $(MKFILE_PATH))
 
-CFG_OVERRIDE ?= target/rtl/cfg/hemaia.hjson
+CFG_OVERRIDE ?= target/rtl/cfg/hemaia_tapeout.hjson
 CFG = $(realpath $(CFG_OVERRIDE))
 
 clean:

target/rtl/Makefile

@@ -58,7 +58,7 @@ CFG = $(TARGET_RTL)/cfg/lru.hjson
 $(CFG): FORCE
 	@# If the LRU config file doesn't exist, we use the default config.
 	@if [ ! -e $@ ] ; then \
-		DEFAULT_CFG="$(TARGET_RTL)/cfg/hemaia.hjson"; \
+		DEFAULT_CFG="$(TARGET_RTL)/cfg/hemaia_tapeout.hjson"; \
 		echo "Using default config file: $$DEFAULT_CFG"; \
 		cp $$DEFAULT_CFG $@; \
 	fi

target/rtl/cfg/hemaia.hjson → target/rtl/cfg/hemaia_ci.hjson

@@ -108,10 +108,10 @@
       cfg_base_offset: 65536 // 0x10000
     },
     clusters:[
+      "snax_KUL_cluster",   // snax_cgra_cluster
       "snax_KUL_cluster",
-      "snax_KUL_dse_cluster",
       "snax_hypercorex_cluster",
-      // "snax_dimc_cluster"
+      snax_dimc_cluster
     ],
 
     // peripherals

target/sim/sw/device/apps/snax/snax-gemmx-conv/data/datagen.py

@@ -13,20 +13,11 @@
 import sys
 import os
 
-import subprocess
-
 # Add data utility path
-sys.path.append(os.path.join(os.path.dirname(__file__),
-                "../../../../../../../../util/sim/"))
+sys.path.append(os.path.join(os.path.dirname(__file__), "../../../../../../../../util/sim/"))
 from data_utils import format_scalar_definition, format_vector_definition  # noqa E402
 
 # Add golden model path
-bender_command = subprocess.run(['bender', 'path', 'snitch_cluster'],
-                                capture_output=True, text=True)
-snax_utils_path = bender_command.stdout.strip()
-
-sys.path.append(snax_utils_path + "/util/sim/")
-
 from snax_utils import (  # noqa E402
     conv2d,
     im2col,

target/sim/sw/device/apps/snax/snax-gemmx-conv/data/params.hjson

@@ -23,7 +23,7 @@
   channel_en_C: 1,
 
   // memory space configurations
-  interleaved_address: 1,
+  interleaved_address: 0,
   memory_size: 128,
 
   // hardware parameters