170915.01
Updates:
- added default_rw_hw_access rdl input parameter which sets default hw=rw rather than hw=r for all fields
- added include_field_hw_info xml output parameter, which controls if rdl hw-related info will be included in generated xml
- fix for packing of nested rdl fieldstructs when fieldstructwidth is specified
- updated testbench generator to support parallel root decoder interfaces
- added nack_partial_writes systemverilog output option, which issues nack
for writes of size less than target (rather than relying on check of
returned transaction size) - added support for selectable width write enable control on parallel decoder interfaces (issue #15)
- added regs_use_factory boolean uvmregs parameter to allow registers to use the factory in output model (issue #16)
- added a check for invalid field/fieldstruct bit ranges/widths (issue #17)
- fix for reuse_uvm_classes uvmregs output option (issue #23)
- added max_internal_reg_reps systemverilog parameter to control max replication count allowed for internal registers (issue #24)
- fix for systemverilog issue with back to back pio transactions using gated logic clock (issue #25)
- added ordt_viewer utility for viewing ordt-generated xml files
Known issues:
- external reg array with only 2 registers throws vlog compile error (issue #19)
Info:
Requires java 1.7
To run... java -jar Ordt.jar
Note that Ordt.jar bundles the antlr 4.5 runtime jar (see http://www.antlr.org).