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integration test, HLT instruction
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FEgor04 committed Jun 1, 2024
1 parent adf6f20 commit 28f32fa
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Showing 3 changed files with 45 additions and 10 deletions.
23 changes: 23 additions & 0 deletions src/integration_test.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
import unittest
from translator import parse_lines
from machine import DataPath, ControlUnit

class IntegrationTest(unittest.TestCase):
def test_sum(self):
lines = [
"RESULT: VAR 0",
"LD 5",
"ADD 10",
"ST RESULT",
"HLT"
]
instructions = parse_lines(lines)
data_path = DataPath("", print, instructions)
control_unit = ControlUnit(1, data_path)
try:
for i in range(10):
control_unit.decode_and_execute()
except StopIteration:
pass
self.assertEqual(data_path.memory[0].arg, 10 + 5)

7 changes: 5 additions & 2 deletions src/machine.py
Original file line number Diff line number Diff line change
Expand Up @@ -151,10 +151,9 @@ def address_fetch(self):

def operand_fetch(self):
assert self.program is not None
if self.program.addressing is Addressing.IMMEDIATE:
if self.program.addressing is Addressing.IMMEDIATE or self.program.addressing is None:
self.operand = self.program.arg
return
assert self.address is not None
self.data_path.signal_latch_adress_register(
RegisterSelector.ADDRESS,
self.program_counter,
Expand All @@ -166,6 +165,10 @@ def operand_fetch(self):
self.operand = self.data_path.mem_out.arg

def execute(self):
if self.program.opcode is Opcode.VAR:
raise Exception("Trying to execute VAR instruction!!!! ")
if self.program.opcode is Opcode.HLT:
raise StopIteration()
if self.program.opcode is Opcode.LD:
self.data_path.signal_latch_accumulator(
RegisterSelector.OPERAND,
Expand Down
25 changes: 17 additions & 8 deletions src/translator.py
Original file line number Diff line number Diff line change
Expand Up @@ -20,17 +20,13 @@ def parse_lines(lines: list[str]) -> list[Instruction]:
if line == "":
continue
_, opcode, arg_raw = split_instruction(line)
addressing = parse_addressing(arg_raw)
if addressing is Addressing.IMMEDIATE:
arg_parsed = int(arg_raw) if arg_raw.isdecimal() else arg_raw[1:-1]
arg, addressing = parse_argument(arg_raw, labels)
if opcode == "VAR":
instructions += [
Instruction(Opcode[opcode], arg_parsed, Addressing.IMMEDIATE)
Instruction(Opcode[opcode], arg, addressing)
]
else:
arg_parsed = parse_int_or_none(arg_raw)
if arg_raw != "" and arg_parsed is None:
arg_parsed = labels[arg_raw[1:-1]]
instructions += [Instruction(Opcode[opcode], arg_parsed, addressing)]
instructions += [Instruction(Opcode[opcode], arg, addressing)]
return instructions


Expand All @@ -43,6 +39,19 @@ def parse_labels(lines: list[str]) -> dict[str, int]:
labels[label] = i
return labels

def parse_argument(arg: str, labels: dict[str, int]) -> tuple[str | int, Addressing]:
if len(arg) == 0:
return None, None
addressing = parse_addressing(arg)
if addressing is Addressing.IMMEDIATE:
if arg[0] == "'" and arg[-1] == "'": # is literal
return arg[1:-1], addressing
if arg.isdecimal():
return int(arg), addressing
return labels[arg], addressing
stripped = arg[1:-1]
return int(stripped) if stripped.isdecimal() else labels[stripped], addressing


def parse_addressing(argument: str) -> Addressing | None:
if len(argument) == 0:
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