feat: CMP instruction

src/alu.py

@@ -49,14 +49,16 @@ def signal_alu_operation(self, operation: Opcode, modifiers: set[ALUModifier]):
         left, right = self.process_modifiers(modifiers)
         print(left, right)
         if operation is Opcode.ADD:
-            self.out = left + right
-        if operation is Opcode.SUB:
-            self.out = right - left  # accumulator - buffer
+            out = left + right
+        if operation in {Opcode.SUB, Opcode.CMP}:
+            out = right - left  # accumulator - buffer
         if operation is Opcode.DIV:
-            self.out = right // left
+            out = right // left
         if operation is Opcode.MUL:
-            self.out = right * left
+            out = right * left
         if operation is Opcode.MOD:
-            self.out = right % left
-        self.negative = self.out < 0
-        self.zero = self.out == 0
+            out = right % left
+        if operation is not Opcode.CMP:
+            self.out = out
+        self.negative = out < 0
+        self.zero = out == 0

src/control_unit_test.py

@@ -131,3 +131,21 @@ def test_jz(self):
         self.assertEqual(3, control_unit.program_counter)
         control_unit.decode_and_execute()
         self.assertEqual(4, control_unit.program_counter)
+
+    def test_cmp(self):
+        program = [
+            Instruction(Opcode.LD, 420, Addressing.IMMEDIATE),
+            Instruction(Opcode.CMP, 0, Addressing.IMMEDIATE),
+            Instruction(Opcode.LD, -420, Addressing.IMMEDIATE),
+            Instruction(Opcode.CMP, 0, Addressing.IMMEDIATE),
+        ]
+        data_path = DataPath("", print, program)
+        control_unit = ControlUnit(0, data_path)
+        control_unit.decode_and_execute()
+        control_unit.decode_and_execute()
+        self.assertEqual(control_unit.data_path.alu.zero, False)
+        self.assertEqual(control_unit.data_path.alu.negative, False)
+        control_unit.decode_and_execute()
+        control_unit.decode_and_execute()
+        self.assertEqual(control_unit.data_path.alu.zero, False)
+        self.assertEqual(control_unit.data_path.alu.negative, True)

src/isa.py

@@ -19,6 +19,7 @@ class Opcode(str, Enum):
     MUL = "mul"
     DIV = "div"
     MOD = "mod"
+    CMP = "cmp"
     # Memory
     LD = "ld"
     ST = "st"

src/machine.py

@@ -199,6 +199,7 @@ def execute(self):
             Opcode.MUL,
             Opcode.DIV,
             Opcode.MOD,
+            Opcode.CMP
         }:
             self.data_path.signal_latch_buffer(
                 RegisterSelector.OPERAND,