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[pull] master from chipsalliance:master #13

Merged
merged 299 commits into from
Aug 21, 2024
Merged

[pull] master from chipsalliance:master #13

merged 299 commits into from
Aug 21, 2024

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jerryz123 and others added 30 commits September 26, 2023 16:14
@jerryz123
Support CloneCluster
0a00146
@jerryz123
Rename Element to HierarchicalElement
8f220f1
@jerryz123
Add set_vconfig to vector-unit
ad37acb
@jerryz123
Propagate request size/cmd to TLB resp
bff48a8
@jerryz123
Add SimpleHellaCacheIF mask
d8f6caf
@poemonsense
Fix the missing flow argument in TileLink/ToAXI4 (#3505)
71a1b6f 
`flow` must be explicitly passed to `Queue.irrevocable` to avoid
mismatching the arguments.
@poemonsense
Fix the missing DontCare in TileLink Edges/Delayer (#3504)
bb74155 
* add DontCare for user/echo bits in Channel A/C/D
* add DontCare for messages without any data payload
@sequencer
Bump flake dependencies (#3506)
4fed21e 
* bump flake

* remove legacy firtool option
@jerryz123
Switch to SortedMap for tile node maps
516288f
@jerryz123
Add tile_reset_domain alias to element_reset_domain in TilePRCIDomain
fd51b74
@jerryz123
Switch to separate cluster-local bus locations
f745cff
@sequencer
Add documentation to DCache about datapath of meta/data arbiter (#3510)
2a190d2
@jerryz123
Generalize WithNBigCores to support clustered cores
ef1d671
@jerryz123
Rename trace crossing nodes to crossing nodes
e0ea903
@jerryz123
Fix int clock crossings to use CLINT/PLIC domains
d48b45d
@jerryz123
Fix any unassigned clocks due to removal of implicit clock from BaseS…
8881ccd 
…ubsystem
@jerryz123
Fix intsynccrossings not receiving a clock
0e88fc0
@jerryz123
Add SimpleLazyRawModule
f85496e
@jerryz123
Synchronize ext-ints within the ibus domain
59e86fd
@jerryz123
Fix RoCCCSRIO bidir
b47fdf9
@jerryz123
Merge pull request #3516 from chipsalliance/jerryz123-patch-2
c60ad43 
Fix CSRIO bidir connection
@sequencer
Remove Chisel 3.6 support (#3515)
8907e63
@abejgonzalez
Add DelayQueue variations
b2b78fd
@abejgonzalez
Add docstrings
4dc6305
@jerryz123
Merge pull request #3520 from abejgonzalez/delay-queue
04cbdf3 
Add DelayQueue
@sequencer @SihaoLiu
Fix r_pte update condition when S2 PTE cache hit (#3525) (#3526)
5087e53 
Co-authored-by: Sihao Liu <sihao@cs.ucla.edu>
@sequencer
add sonatype snapshots repo for test chisel releases (#3527)
180e4bc
@sequencer
remove torture
1101d21
@sequencer
move cde and hardfloat to dependencies folder
b0a3b66
@sequencer
add support to build chisel from source
7b01955
jerryz123 and others added 28 commits June 30, 2024 14:12
@jerryz123
Clean up TileAttachConfig | add atTileIds method
0464c21
@jerryz123
Merge pull request #3655 from chipsalliance/split-configs
f50b0db 
Move rocket-related config fragments to rocket/Configs.scala
@ksungkeun84
Add IO Connections for Custom User Field in TL Channels within Xbar
54ff555 
 DontCare should come first before waiveAll so that matching userfield
 bewteen bundles can be connected
 Please refer to the issue page below.
 ucb-bar/chipyard#1888
@ksungkeun84
Fix for compilation error in PhysicallFilter
afe77ac 
I think this module is not tested during Chisel version is updated.
I fixed compiler error by chiselTypeOf
@jerryz123
Merge pull request #3637 from ksungkeun84/master
4b33216 
Add IO Connections for Custom User Field in TL Channels within Xbar
@jerryz123
Properly generate zvfh isa string
286e842
@jerryz123
Fix zvfh capitalization
e53bbfc
@jerryz123
Fix FP16 storegen bug
04d4271
@sequencer
bug fix to io.out.bits.store
794c5b1
@sequencer
Merge pull request #3659 from chipsalliance/zvfh
306467d 
Fix support for vector units with Zvfh
@jerryz123
Support vector extensions
ee7f6a6
@sequencer
Merge pull request #3665 from chipsalliance/v_exts
3e20954 
Support vector extensions
@jerryz123
Add support for zba/zbb/zbs-enabled tiles
1aa0104
@jerryz123
Revert to single global ALU
c68371e
@jerryz123
Fix rv64uzba test names
37cfd6f
@jerryz123
Support Zba in rocket
90da5bc
@jerryz123
Add Zbb support
83e8c6b
@jerryz123
Support Zbs extension
51a5485
@jerryz123
Fix rv32b
09bbf5c
@jerryz123
Add b-ext tests to CI
1dbaf6d
@jerryz123
Set 'b' in isaStr if zba+zbb+zbs
7e16264
@jerryz123
Add HugeCore config that adds Zfh/Zba/Zbb/Zbs
48037e9
@jerryz123
Disable ma_data rv32 tests in CI, rocket does not support misaligned …
044a434 
…load/store
@sequencer
Merge pull request #3667 from chipsalliance/b_ext
7c32936 
B ext
@jerryz123
Prevent bypasses from vector instructions
49158aa
@jerryz123
Fix bit indices for rd when computing AVL for vsets
72690b0
@sequencer
Merge pull request #3670 from chipsalliance/vec_bypasses
14b81e4 
Prevent bypasses from vector instructions | fix vsets
@jerryz123
Merge pull request #3675 from chipsalliance/dev
cff28b8 
Sync dev to master
@pull pull bot added the ⤵️ pull label Aug 21, 2024
@pull pull bot merged commit cff28b8 into EECS-NTNU:master Aug 21, 2024
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