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Set SYSRESETREQ repeatedly on M55+M85+M52 #214

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Set SYSRESETREQ repeatedly on M55+M85+M52 #214

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20 changes: 11 additions & 9 deletions CMSIS/Core/Include/core_cm52.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4112,16 +4112,18 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */

for(;;) /* wait until reset */
/* SYSRESETREQ needs to be set repeatedly as it is cleared as soon as the CPU's P-channel
* enters WARM_RST state, but another device can deny the transition preventing the
* actual reset. Such denials are usually transient - we need to re-assert SYSRESETREQ
* to retry.
*/
for(;;)
{
__NOP();
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
}
}

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20 changes: 11 additions & 9 deletions CMSIS/Core/Include/core_cm55.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4238,16 +4238,18 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */

for(;;) /* wait until reset */
/* SYSRESETREQ needs to be set repeatedly as it is cleared as soon as the CPU's P-channel
* enters WARM_RST state, but another device can deny the transition preventing the
* actual reset. Such denials are usually transient - we need to re-assert SYSRESETREQ
* to retry.
*/
for(;;)
{
__NOP();
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
}
}

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20 changes: 11 additions & 9 deletions CMSIS/Core/Include/core_cm85.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4262,16 +4262,18 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */

for(;;) /* wait until reset */
/* SYSRESETREQ needs to be set repeatedly as it is cleared as soon as the CPU's P-channel
* enters WARM_RST state, but another device can deny the transition preventing the
* actual reset. Such denials are usually transient - we need to re-assert SYSRESETREQ
* to retry.
*/
for(;;)
{
__NOP();
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
}
}

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