diff --git a/boards/nordic/nrf54l09pdk/Kconfig.defconfig b/boards/nordic/nrf54l09pdk/Kconfig.defconfig
index e495d3e67ce8..44589c9b35b7 100644
--- a/boards/nordic/nrf54l09pdk/Kconfig.defconfig
+++ b/boards/nordic/nrf54l09pdk/Kconfig.defconfig
@@ -9,9 +9,6 @@ config BT_CTLR
 config ROM_START_OFFSET
 	default 0x800 if BOOTLOADER_MCUBOOT
 
-config SOC_NRF54LX_SKIP_CLOCK_CONFIG
-	default y
-
 config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE
 	default y
 
diff --git a/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi b/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi
index c258cb2f4b77..0bdab1b8851d 100644
--- a/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi
+++ b/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi
@@ -27,6 +27,11 @@
 	status = "okay";
 };
 
+&hfpll {
+	/* For now use 64 MHz clock for CPU and fast peripherals. */
+	clock-frequency = <DT_FREQ_M(64)>;
+};
+
 &lfxo {
 	load-capacitors = "internal";
 	load-capacitance-femtofarad = <15500>;
diff --git a/boards/nordic/nrf54l20pdk/Kconfig.defconfig b/boards/nordic/nrf54l20pdk/Kconfig.defconfig
index f6987b800879..406a65c88269 100644
--- a/boards/nordic/nrf54l20pdk/Kconfig.defconfig
+++ b/boards/nordic/nrf54l20pdk/Kconfig.defconfig
@@ -6,9 +6,6 @@ if BOARD_NRF54L20PDK_NRF54L20_CPUAPP
 config ROM_START_OFFSET
 	default 0x800 if BOOTLOADER_MCUBOOT
 
-config SOC_NRF54LX_SKIP_CLOCK_CONFIG
-	default y
-
 config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE
 	default y
 
diff --git a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi
index cdf6d62a30a7..0d3c1fe98e99 100644
--- a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi
+++ b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi
@@ -27,6 +27,11 @@
 	status = "okay";
 };
 
+&hfpll {
+	/* For now use 64 MHz clock for CPU and fast peripherals. */
+	clock-frequency = <DT_FREQ_M(64)>;
+};
+
 &lfxo {
 	load-capacitors = "internal";
 	load-capacitance-femtofarad = <15500>;
diff --git a/dts/common/nordic/nrf54l09.dtsi b/dts/common/nordic/nrf54l09.dtsi
index 37acf9d34cb9..69457461535b 100644
--- a/dts/common/nordic/nrf54l09.dtsi
+++ b/dts/common/nordic/nrf54l09.dtsi
@@ -27,7 +27,7 @@
 			compatible = "arm,cortex-m33f";
 			reg = <0>;
 			device_type = "cpu";
-			clock-frequency = <DT_FREQ_M(64)>;
+			clocks = <&hfpll>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			itm: itm@e0000000 {
diff --git a/dts/common/nordic/nrf54l20.dtsi b/dts/common/nordic/nrf54l20.dtsi
index e5b019deff93..54e431295afa 100644
--- a/dts/common/nordic/nrf54l20.dtsi
+++ b/dts/common/nordic/nrf54l20.dtsi
@@ -23,7 +23,7 @@
 			compatible = "arm,cortex-m33f";
 			reg = <0>;
 			device_type = "cpu";
-			clock-frequency = <DT_FREQ_M(128)>;
+			clocks = <&hfpll>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			itm: itm@e0000000 {
diff --git a/dts/common/nordic/nrf54l_05_10_15.dtsi b/dts/common/nordic/nrf54l_05_10_15.dtsi
index 633b1d425e47..c74dd16f9a57 100644
--- a/dts/common/nordic/nrf54l_05_10_15.dtsi
+++ b/dts/common/nordic/nrf54l_05_10_15.dtsi
@@ -27,7 +27,7 @@
 			compatible = "arm,cortex-m33f";
 			reg = <0>;
 			device_type = "cpu";
-			clock-frequency = <DT_FREQ_M(128)>;
+			clocks = <&hfpll>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			itm: itm@e0000000 {
@@ -41,7 +41,7 @@
 			compatible = "nordic,vpr";
 			reg = <1>;
 			device_type = "cpu";
-			clock-frequency = <DT_FREQ_M(128)>;
+			clocks = <&hfpll>;
 			riscv,isa = "rv32emc";
 			nordic,bus-width = <32>;
 		};
diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt
index 91c694878cae..3e77e1175d06 100644
--- a/modules/hal_nordic/nrfx/CMakeLists.txt
+++ b/modules/hal_nordic/nrfx/CMakeLists.txt
@@ -183,7 +183,10 @@ if(DEFINED uicr_path)
 endif()
 
 if(CONFIG_SOC_NRF54L_CPUAPP_COMMON)
-	dt_prop(clock_frequency PATH "/cpus/cpu@0" PROPERTY "clock-frequency")
+	# Ideally, hfpll should taken as a phandle from clocks property from cpu but it
+	# seems that there is no such option in DT cmake functions. Assuming that nrf54l
+	# is using hfpll as CPU clock source (true for all existing devices).
+	dt_prop(clock_frequency PATH "/clocks/hfpll" PROPERTY "clock-frequency")
 	math(EXPR clock_frequency_mhz "${clock_frequency} / 1000000")
 	zephyr_compile_definitions("NRF_CONFIG_CPU_FREQ_MHZ=${clock_frequency_mhz}")
 endif()
diff --git a/soc/nordic/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c
index abb0f778ac33..5c24df49d54d 100644
--- a/soc/nordic/nrf54l/soc.c
+++ b/soc/nordic/nrf54l/soc.c
@@ -32,6 +32,7 @@
 
 #include <nrf_erratas.h>
 #include <system_nrf54l.h>
+#include <zephyr/drivers/clock_control/nrf_clock_control.h>
 
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
@@ -43,9 +44,9 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 static int nordicsemi_nrf54l_init(void)
 {
 	/* Update the SystemCoreClock global variable with current core clock
-	 * retrieved from hardware state.
+	 * retrieved from the DT.
 	 */
-	SystemCoreClockUpdate();
+	SystemCoreClock = NRF_PERIPH_GET_FREQUENCY(DT_NODELABEL(cpu));
 
 #if defined(NRF_APPLICATION)
 	/* Enable ICACHE */