From 50a31733bf3e8568a9931f345892df4074b87e03 Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Thu, 17 Oct 2024 14:23:16 -0700 Subject: [PATCH 1/2] boards: add USB HS 2.0 support for the Nucleo u5a5jz-q board (Issue #79823) This board has the required clock crystal (X4) and jumper settings present to enable the USB 2.0 HS support. * Enable the HSE clock (16MHz) * Flip the PLL1 configuration over to use the HSE clock, but still outputting 160MHz to sysclk/apbclk. * Add the USB HS device tree node. * Update the board documentation. Signed-off-by: Adrian Chadd --- boards/st/nucleo_u5a5zj_q/doc/index.rst | 13 +++++++++++-- .../nucleo_u5a5zj_q-common.dtsi | 19 ++++++++++--------- boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts | 6 ++++++ .../st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml | 1 + 4 files changed, 28 insertions(+), 11 deletions(-) diff --git a/boards/st/nucleo_u5a5zj_q/doc/index.rst b/boards/st/nucleo_u5a5zj_q/doc/index.rst index ea919c4f10ee..794a2351d825 100644 --- a/boards/st/nucleo_u5a5zj_q/doc/index.rst +++ b/boards/st/nucleo_u5a5zj_q/doc/index.rst @@ -204,6 +204,8 @@ The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware f +-----------+------------+-------------------------------------+ | RTC | on-chip | rtc | +-----------+------------+-------------------------------------+ +| USB | on-chip | USB 2.0 HS | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -245,13 +247,15 @@ Default Zephyr Peripheral Mapping: - UART_2_TX : PD5 - UART_2_RX : PD6 - USER_PB : PC13 +- USB_DM : PA11 +- USB_DP : PA12 System Clock ------------ Nucleo U5A5ZJ Q System Clock could be driven by internal or external oscillator, as well as main PLL clock. By default System clock is driven by PLL clock at -160MHz, driven by 4MHz medium speed internal oscillator. +160MHz, driven by the 16MHz high speed oscillator. Serial Port ----------- @@ -259,13 +263,18 @@ Serial Port Nucleo U5A5ZJ Q board has 6 U(S)ARTs. The Zephyr console output is assigned to USART1. Default settings are 115200 8N1. - Backup SRAM ----------- In order to test backup SRAM you may want to disconnect VBAT from VDD. You can do it by removing ``SB50`` jumper on the back side of the board. +Using USB +--------- + +USB 2.0 high speed (HS) operation requires the HSE clock source to be populated +and enabled. The Nucleo U5A5ZJ-Q includes the 16MHz oscillator and required +jumper settings. Programming and Debugging ************************* diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi index ecc9e862c990..fcb460c002c6 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi @@ -55,22 +55,23 @@ status = "okay"; }; -&clk_lse { +/* This board has a 16MHz crystal attached */ +&clk_hse { + clock-frequency = ; status = "okay"; }; -&clk_msis { +&clk_lse { status = "okay"; - msi-range = <4>; - msi-pll-mode; }; &pll1 { - div-m = <1>; - mul-n = <80>; - div-q = <2>; - div-r = <2>; - clocks = <&clk_msis>; + /* HSE 16MHz source, outputting 160MHz to sysclk and apbclk */ + div-m = <4>; /* input divisor */ + mul-n = <80>; /* VCO multiplication factor */ + div-q = <2>; /* system clock divisor */ + div-r = <2>; /* peripheral clock divisor */ + clocks = <&clk_hse>; status = "okay"; }; diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts index a9907afe6142..e34b10024ab0 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts @@ -74,3 +74,9 @@ &gpdma1 { status = "okay"; }; + +zephyr_udc0: &usbotg_hs { + pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml index cd9370804141..57c0712ffedb 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml @@ -21,5 +21,6 @@ supported: - backup_sram - dma - rtc + - usb_device ram: 2450 flash: 4096 From e21b99c6c53b151cf1dd8ce36a3aa620f1c9b1dc Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Thu, 17 Oct 2024 14:29:21 -0700 Subject: [PATCH 2/2] dts: include: arm: st: usb: Add USB PHY clock rate support for STM32U5xxx The existing code assumes that the HSE clock is a 16MHz crystal, however the hardware allows for a list of possible HSE clock values. Add them here as an enum, configure it for the STM32U595 chipset (which is the only device I have access to for testing). This addresses Issue #79825 . * Rename USBPHYC_SEL -> OTGHS_SEL which matches the definition in the stm32u5 CCIPR2 register (RM0456 Rev 5, Section 11.8.47). * Add a list of possible values to use in the DT bindings directory * Add a new PHY (st,stm32-otghs-phy) with an enum list matching the above list * Add support in the USB driver for checking the clock-cfg entry and compiling in the correct clock rate. * And also handle an out of enum configuration by failing compilation. Signed-off-by: Adrian Chadd --- drivers/usb/device/usb_dc_stm32.c | 22 +++++++++++++--- dts/arm/st/u5/stm32u5.dtsi | 1 + dts/arm/st/u5/stm32u595.dtsi | 6 ++--- dts/bindings/phy/st,stm32u5-otghs-phy.yaml | 26 +++++++++++++++++++ .../zephyr/dt-bindings/clock/stm32u5_clock.h | 2 +- .../dt-bindings/phy/stm32u5_otg_hs_phy.h | 16 ++++++++++++ 6 files changed, 66 insertions(+), 7 deletions(-) create mode 100644 dts/bindings/phy/st,stm32u5-otghs-phy.yaml create mode 100644 include/zephyr/dt-bindings/phy/stm32u5_otg_hs_phy.h diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c index b5fc75c3c2ea..658f99d3ce24 100644 --- a/drivers/usb/device/usb_dc_stm32.c +++ b/drivers/usb/device/usb_dc_stm32.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include "stm32_hsem.h" @@ -36,6 +37,21 @@ LOG_MODULE_REGISTER(usb_dc_stm32); #error "Only one interface should be enabled at a time, OTG FS or OTG HS" #endif +/* + * Some STM32U5xx parts support a USB HS PHY which is clocked by the HSE clock or PLL1_P + * clock directly. This requires specific configuration. + */ +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32u5_otghs_phy) +#if DT_NODE_HAS_PROP(DT_PHANDLE_BY_IDX(DT_NODELABEL(usbotg_hs), phys, 0), clock_cfg) +#define OTG_HS_PHY_REFERENCE_CLOCK \ + _CONCAT(SYSCFG_OTG_HS_PHY_CLK_SELECT_, \ + DT_PROP(DT_PHANDLE(DT_NODELABEL(usbotg_hs), phys), clock_cfg)) +#else +#define OTG_HS_PHY_REFERENCE_CLOCK SYSCFG_OTG_HS_PHY_CLK_SELECT_1 +#endif + +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32u5_otghs_phy) */ + /* * Vbus sensing is determined based on the presence of the hardware detection * pin(s) in the device tree. E.g: pinctrl-0 = <&usb_otg_fs_vbus_pa9 ...>; @@ -217,7 +233,7 @@ static int usb_dc_stm32_clock_enable(void) return -ENODEV; } -#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) && defined(CONFIG_SOC_SERIES_STM32U5X) +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32u5_otghs_phy) /* Sequence to enable the power of the OTG HS on a stm32U5 serie : Enable VDDUSB */ bool pwr_clk = LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PWR); @@ -246,7 +262,7 @@ static int usb_dc_stm32_clock_enable(void) /* Set the OTG PHY reference clock selection (through SYSCFG) block */ LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_SYSCFG); - HAL_SYSCFG_SetOTGPHYReferenceClockSelection(SYSCFG_OTG_HS_PHY_CLK_SELECT_1); + HAL_SYSCFG_SetOTGPHYReferenceClockSelection(OTG_HS_PHY_REFERENCE_CLOCK); /* Configuring the SYSCFG registers OTG_HS PHY : OTG_HS PHY enable*/ HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE); #elif defined(PWR_USBSCR_USB33SV) || defined(PWR_SVMCR_USV) @@ -333,7 +349,7 @@ static int usb_dc_stm32_clock_disable(void) LOG_ERR("Unable to disable USB clock"); return -EIO; } -#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) && defined(CONFIG_SOC_SERIES_STM32U5X) +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32u5_otghs_phy) LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_USBPHY); #endif diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi index 9f694d600a3f..d227d7d8f023 100644 --- a/dts/arm/st/u5/stm32u5.dtsi +++ b/dts/arm/st/u5/stm32u5.dtsi @@ -20,6 +20,7 @@ #include #include #include +#include #include / { diff --git a/dts/arm/st/u5/stm32u595.dtsi b/dts/arm/st/u5/stm32u595.dtsi index c0c856dc2738..7395dcbc172a 100644 --- a/dts/arm/st/u5/stm32u595.dtsi +++ b/dts/arm/st/u5/stm32u595.dtsi @@ -107,15 +107,15 @@ ram-size = <4096>; maximum-speed = "high-speed"; clocks = <&rcc STM32_CLOCK(AHB2, 15U)>, - <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>; + <&rcc STM32_SRC_HSI48 OTGHS_SEL(0)>; phys = <&otghs_phy>; status = "disabled"; }; }; otghs_phy: otghs_phy { - /* Clock source defined by USBPHYC_SEL in */ - compatible = "usb-nop-xceiv"; + /* Clock source defined by OTGHS_SEL() in usbotg_hs `clocks` */ + compatible = "st,stm32u5-otghs-phy"; #phy-cells = <0>; }; diff --git a/dts/bindings/phy/st,stm32u5-otghs-phy.yaml b/dts/bindings/phy/st,stm32u5-otghs-phy.yaml new file mode 100644 index 000000000000..4df4ac983735 --- /dev/null +++ b/dts/bindings/phy/st,stm32u5-otghs-phy.yaml @@ -0,0 +1,26 @@ +# Copyright (c) 2024 Meta +# SPDX-License-Identifier: Apache-2.0 + +description: | + This binding is to be used by the STM32U5xx transceivers which are built-in + with USB HS PHY IP and a configurable HSE clock source. + +compatible: "st,stm32u5-otghs-phy" + +include: phy-controller.yaml + +properties: + "#phy-cells": + const: 0 + + clock-cfg: + type: int + enum: + - 1 # OTGHS_PHY_CLK_16MHZ + - 2 # OTGHS_PHY_CLK_19P2MHZ + - 3 # OTGHS_PHY_CLK_20MHZ + - 4 # OTGHS_PHY_CLK_24MHZ + - 5 # OTGHS_PHY_CLK_26MHZ + - 6 # OTGHS_PHY_CLK_32MHZ + description: | + The clock source speed configuration for this PHY. diff --git a/include/zephyr/dt-bindings/clock/stm32u5_clock.h b/include/zephyr/dt-bindings/clock/stm32u5_clock.h index 4b9b563121e9..4fd9214eea27 100644 --- a/include/zephyr/dt-bindings/clock/stm32u5_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32u5_clock.h @@ -122,7 +122,7 @@ #define HSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR2_REG) #define I2C5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR2_REG) #define I2C6_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR2_REG) -#define USBPHYC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR2_REG) +#define OTGHS_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR2_REG) /** CCIPR3 devices */ #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG) #define SPI3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR3_REG) diff --git a/include/zephyr/dt-bindings/phy/stm32u5_otg_hs_phy.h b/include/zephyr/dt-bindings/phy/stm32u5_otg_hs_phy.h new file mode 100644 index 000000000000..abdb78240aec --- /dev/null +++ b/include/zephyr/dt-bindings/phy/stm32u5_otg_hs_phy.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Meta + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PHY_STM32U5_OTG_HS_PHY_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PHY_STM32U5_OTG_HS_PHY_H_ + +#define OTGHS_PHY_CLK_16MHZ 1 +#define OTGHS_PHY_CLK_19P2MHZ 2 +#define OTGHS_PHY_CLK_20MHZ 3 +#define OTGHS_PHY_CLK_24MHZ 4 +#define OTGHS_PHY_CLK_26MHZ 5 +#define OTGHS_PHY_CLK_32MHZ 6 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PHY_STM32U5_OTG_HS_PHY_H_ */