diff --git a/dts/arm64/intel/intel_socfpga_agilex5.dtsi b/dts/arm64/intel/intel_socfpga_agilex5.dtsi
index c7c9b53ebfc8..ed62369c9269 100644
--- a/dts/arm64/intel/intel_socfpga_agilex5.dtsi
+++ b/dts/arm64/intel/intel_socfpga_agilex5.dtsi
@@ -128,7 +128,7 @@
 			<0x10B92000 0x1000>;
 		reg-names = "reg_base", "combo_phy";
 		clock-frequency = <200000000>;
-		power_delay_ms = <1000>;
+		power-delay-ms = <1000>;
 		resets = <&reset RSTMGR_SDMMC_RSTLINE>,
 			<&reset RSTMGR_SDMMCECC_RSTLINE>,
 			<&reset RSTMGR_SOFTPHY_RSTLINE>;
diff --git a/dts/bindings/sdhc/cdns,sdhc.yaml b/dts/bindings/sdhc/cdns,sdhc.yaml
index 536b9c4bd58a..5d3af2f4cd11 100644
--- a/dts/bindings/sdhc/cdns,sdhc.yaml
+++ b/dts/bindings/sdhc/cdns,sdhc.yaml
@@ -14,7 +14,7 @@ properties:
   reg:
     required: true
     description: register space
-  power_delay_ms:
+  power-delay-ms:
     type: int
     required: true
     description: delay required to switch on the SDHC
diff --git a/dts/bindings/sdhc/nxp,imx-usdhc.yaml b/dts/bindings/sdhc/nxp,imx-usdhc.yaml
index bccdf51d7230..4e217d0c7dbb 100644
--- a/dts/bindings/sdhc/nxp,imx-usdhc.yaml
+++ b/dts/bindings/sdhc/nxp,imx-usdhc.yaml
@@ -29,7 +29,7 @@ properties:
     description: |
       Number of words used as write watermark level in FIFO queue for USDHC
 
-  max_current_330:
+  max-current-330:
     type: int
     default: 0
     description: |