From 960de32805584f33dc74cc07feceb2390aca47b1 Mon Sep 17 00:00:00 2001 From: Ioannis Glaropoulos Date: Tue, 19 Jun 2018 15:05:41 +0200 Subject: [PATCH] arch: arm: move ARMv7-m specific content in corresponding header file This commit moves the macro definitions and convenience wrappers for ARM MPU that are specific to ARMv6-m, and ARMv7-m to an arch-specific MPU header file. It leaves only the generic content in arm_mpu.h, i.e. the content that is supposed to be common for ARMv8-M MPU. Signed-off-by: Ioannis Glaropoulos --- include/arch/arm/arch.h | 30 ---- include/arch/arm/cortex_m/mpu/arm_mpu.h | 146 +++++--------------- include/arch/arm/cortex_m/mpu/arm_mpu_v7m.h | 124 +++++++++++++++++ 3 files changed, 160 insertions(+), 140 deletions(-) create mode 100644 include/arch/arm/cortex_m/mpu/arm_mpu_v7m.h diff --git a/include/arch/arm/arch.h b/include/arch/arm/arch.h index 2210cbffc59b..bf5428b39809 100644 --- a/include/arch/arm/arch.h +++ b/include/arch/arm/arch.h @@ -258,36 +258,6 @@ extern "C" { #ifdef CONFIG_ARM_MPU #ifndef _ASMLANGUAGE #include - -#define K_MEM_PARTITION_P_NA_U_NA (NO_ACCESS | MPU_RASR_XN_Msk) -#define K_MEM_PARTITION_P_RW_U_RW (P_RW_U_RW | MPU_RASR_XN_Msk) -#define K_MEM_PARTITION_P_RW_U_RO (P_RW_U_RO | MPU_RASR_XN_Msk) -#define K_MEM_PARTITION_P_RW_U_NA (P_RW_U_NA | MPU_RASR_XN_Msk) -#define K_MEM_PARTITION_P_RO_U_RO (P_RO_U_RO | MPU_RASR_XN_Msk) -#define K_MEM_PARTITION_P_RO_U_NA (P_RO_U_NA | MPU_RASR_XN_Msk) - -/* Execution-allowed attributes */ -#define K_MEM_PARTITION_P_RWX_U_RWX (P_RW_U_RW) -#define K_MEM_PARTITION_P_RWX_U_RX (P_RW_U_RO) -#define K_MEM_PARTITION_P_RX_U_RX (P_RO_U_RO) - -#define K_MEM_PARTITION_IS_WRITABLE(attr) \ - ({ \ - int __is_writable__; \ - switch (attr) { \ - case P_RW_U_RW: \ - case P_RW_U_RO: \ - case P_RW_U_NA: \ - __is_writable__ = 1; \ - break; \ - default: \ - __is_writable__ = 0; \ - } \ - __is_writable__; \ - }) -#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \ - (!((attr) & (MPU_RASR_XN_Msk))) - #endif /* _ASMLANGUAGE */ #define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \ BUILD_ASSERT_MSG(!(((size) & ((size) - 1))) && (size) >= 32 && \ diff --git a/include/arch/arm/cortex_m/mpu/arm_mpu.h b/include/arch/arm/cortex_m/mpu/arm_mpu.h index 458bf7fbc94a..5f5f48481fe9 100644 --- a/include/arch/arm/cortex_m/mpu/arm_mpu.h +++ b/include/arch/arm/cortex_m/mpu/arm_mpu.h @@ -9,120 +9,46 @@ #include #include -/* ARM MPU RASR Register */ - -/* Privileged No Access, Unprivileged No Access */ -#define NO_ACCESS ((0x0 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged No Access, Unprivileged No Access */ -#define P_NA_U_NA ((0x0 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Write, Unprivileged No Access */ -#define P_RW_U_NA ((0x1 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Write, Unprivileged Read Only */ -#define P_RW_U_RO ((0x2 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Write, Unprivileged Read Write */ -#define P_RW_U_RW ((0x3 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Write, Unprivileged Read Write */ -#define FULL_ACCESS ((0x3 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Only, Unprivileged No Access */ -#define P_RO_U_NA ((0x5 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Only, Unprivileged Read Only */ -#define P_RO_U_RO ((0x6 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Only, Unprivileged Read Only */ -#define RO ((0x7 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) - -/* The following definitions are for internal use in this file. */ -#define STRONGLY_ORDERED_SHAREABLE MPU_RASR_S_Msk -#define DEVICE_SHAREABLE (MPU_RASR_B_Msk | MPU_RASR_S_Msk) -#define NORMAL_OUTER_INNER_WRITE_THROUGH_SHAREABLE \ - (MPU_RASR_C_Msk | MPU_RASR_S_Msk) -#define NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE MPU_RASR_C_Msk -#define NORMAL_OUTER_INNER_WRITE_BACK_SHAREABLE \ - (MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk) -#define NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE \ - (MPU_RASR_C_Msk | MPU_RASR_B_Msk) -#define NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE \ - ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_S_Msk) -#define NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE \ - (1 << MPU_RASR_TEX_Pos) -#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_SHAREABLE \ - ((1 << MPU_RASR_TEX_Pos) |\ - MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk) -#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NONSHAREABLE \ - ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_S_Msk) -#define DEVICE_NON_SHAREABLE (2 << MPU_RASR_TEX_Pos) - -/* Some helper defines for common regions */ -#define REGION_USER_RAM_ATTR(size) \ - (NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \ - MPU_RASR_XN_Msk | size | FULL_ACCESS) -#define REGION_RAM_ATTR(size) \ - (NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \ - MPU_RASR_XN_Msk | size | P_RW_U_NA) -#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE) -#define REGION_FLASH_ATTR(size) \ - (NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | size | \ - P_RW_U_RO) -#else -#define REGION_FLASH_ATTR(size) \ - (NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | size | RO) +#if defined(CONFIG_CPU_CORTEX_M0PLUS) || \ + defined(CONFIG_CPU_CORTEX_M3) || \ + defined(CONFIG_CPU_CORTEX_M4) || \ + defined(CONFIG_CPU_CORTEX_M7) +#include #endif -#define REGION_PPB_ATTR(size) (STRONGLY_ORDERED_SHAREABLE | size | P_RW_U_NA) -#define REGION_IO_ATTR(size) (DEVICE_NON_SHAREABLE | size | P_RW_U_NA) -#define SUB_REGION_0_DISABLED ((0x01 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_1_DISABLED ((0x02 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_2_DISABLED ((0x04 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_3_DISABLED ((0x08 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_4_DISABLED ((0x10 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_5_DISABLED ((0x20 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_6_DISABLED ((0x40 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_7_DISABLED ((0x80 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#ifdef CONFIG_USERSPACE +#ifndef _ASMLANGUAGE +/* Read-Write access permission attributes */ +#define K_MEM_PARTITION_P_NA_U_NA (NO_ACCESS | NOT_EXEC) +#define K_MEM_PARTITION_P_RW_U_RW (P_RW_U_RW | NOT_EXEC) +#define K_MEM_PARTITION_P_RW_U_RO (P_RW_U_RO | NOT_EXEC) +#define K_MEM_PARTITION_P_RW_U_NA (P_RW_U_NA | NOT_EXEC) +#define K_MEM_PARTITION_P_RO_U_RO (P_RO_U_RO | NOT_EXEC) +#define K_MEM_PARTITION_P_RO_U_NA (P_RO_U_NA | NOT_EXEC) -#define REGION_32B ((0x04 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_64B ((0x05 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_128B ((0x06 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_256B ((0x07 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_512B ((0x08 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_1K ((0x09 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_2K ((0x0A << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_4K ((0x0B << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_8K ((0x0C << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_16K ((0x0D << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_32K ((0x0E << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_64K ((0x0F << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_128K ((0x10 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_256K ((0x11 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_512K ((0x12 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_1M ((0x13 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_2M ((0x14 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_4M ((0x15 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_8M ((0x16 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_16M ((0x17 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_32M ((0x18 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_64M ((0x19 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_128M ((0x1A << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_256M ((0x1B << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_512M ((0x1C << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_1G ((0x1D << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_2G ((0x1E << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) -#define REGION_4G ((0x1F << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) - -/* Region definition data structure */ -struct arm_mpu_region { - /* Region Base Address */ - u32_t base; - /* Region Name */ - const char *name; - /* Region Attributes */ - u32_t attr; -}; +/* Execution-allowed attributes */ +#define K_MEM_PARTITION_P_RWX_U_RWX (P_RW_U_RW) +#define K_MEM_PARTITION_P_RWX_U_RX (P_RW_U_RO) +#define K_MEM_PARTITION_P_RX_U_RX (P_RO_U_RO) -#define MPU_REGION_ENTRY(_name, _base, _attr) \ - {\ - .name = _name, \ - .base = _base, \ - .attr = _attr, \ - } +#define K_MEM_PARTITION_IS_WRITABLE(attr) \ + ({ \ + int __is_writable__; \ + switch (attr) { \ + case P_RW_U_RW: \ + case P_RW_U_RO: \ + case P_RW_U_NA: \ + __is_writable__ = 1; \ + break; \ + default: \ + __is_writable__ = 0; \ + } \ + __is_writable__; \ + }) +#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \ + (!((attr) & (NOT_EXEC))) +#endif /* _ASMLANGUAGE */ +#endif /* USERSPACE */ /* MPU configuration data structure */ struct arm_mpu_config { diff --git a/include/arch/arm/cortex_m/mpu/arm_mpu_v7m.h b/include/arch/arm/cortex_m/mpu/arm_mpu_v7m.h new file mode 100644 index 000000000000..a36a31049c24 --- /dev/null +++ b/include/arch/arm/cortex_m/mpu/arm_mpu_v7m.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2018 Linaro Limited. + * Copyright (c) 2018 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Privileged No Access, Unprivileged No Access */ +#define NO_ACCESS ((0x0 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged No Access, Unprivileged No Access */ +#define P_NA_U_NA ((0x0 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Write, Unprivileged No Access */ +#define P_RW_U_NA ((0x1 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Write, Unprivileged Read Only */ +#define P_RW_U_RO ((0x2 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Write, Unprivileged Read Write */ +#define P_RW_U_RW ((0x3 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Write, Unprivileged Read Write */ +#define FULL_ACCESS ((0x3 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Only, Unprivileged No Access */ +#define P_RO_U_NA ((0x5 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Only, Unprivileged Read Only */ +#define P_RO_U_RO ((0x6 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Only, Unprivileged Read Only */ +#define RO ((0x7 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) + +/* Attribute flag for not-allowing execution (eXecute Never) */ +#define NOT_EXEC MPU_RASR_XN_Msk + +/* The following definitions are for internal use in arm_mpu.h. */ +#define STRONGLY_ORDERED_SHAREABLE MPU_RASR_S_Msk +#define DEVICE_SHAREABLE (MPU_RASR_B_Msk | MPU_RASR_S_Msk) +#define NORMAL_OUTER_INNER_WRITE_THROUGH_SHAREABLE \ + (MPU_RASR_C_Msk | MPU_RASR_S_Msk) +#define NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE MPU_RASR_C_Msk +#define NORMAL_OUTER_INNER_WRITE_BACK_SHAREABLE \ + (MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk) +#define NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE \ + (MPU_RASR_C_Msk | MPU_RASR_B_Msk) +#define NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE \ + ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_S_Msk) +#define NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE \ + (1 << MPU_RASR_TEX_Pos) +#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_SHAREABLE \ + ((1 << MPU_RASR_TEX_Pos) |\ + MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk) +#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NONSHAREABLE \ + ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_S_Msk) +#define DEVICE_NON_SHAREABLE (2 << MPU_RASR_TEX_Pos) + +/* Bit-masks to disable sub-regions. */ +#define SUB_REGION_0_DISABLED ((0x01 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_1_DISABLED ((0x02 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_2_DISABLED ((0x04 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_3_DISABLED ((0x08 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_4_DISABLED ((0x10 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_5_DISABLED ((0x20 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_6_DISABLED ((0x40 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_7_DISABLED ((0x80 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) + +#define REGION_32B ((0x04 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_64B ((0x05 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_128B ((0x06 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_256B ((0x07 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_512B ((0x08 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_1K ((0x09 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_2K ((0x0A << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_4K ((0x0B << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_8K ((0x0C << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_16K ((0x0D << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_32K ((0x0E << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_64K ((0x0F << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_128K ((0x10 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_256K ((0x11 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_512K ((0x12 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_1M ((0x13 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_2M ((0x14 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_4M ((0x15 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_8M ((0x16 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_16M ((0x17 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_32M ((0x18 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_64M ((0x19 << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_128M ((0x1A << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_256M ((0x1B << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_512M ((0x1C << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_1G ((0x1D << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_2G ((0x1E << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) +#define REGION_4G ((0x1F << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) + +/* Some helper defines for common regions */ +#define REGION_USER_RAM_ATTR(size) \ + (NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \ + MPU_RASR_XN_Msk | size | FULL_ACCESS) +#define REGION_RAM_ATTR(size) \ + (NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \ + MPU_RASR_XN_Msk | size | P_RW_U_NA) +#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE) +#define REGION_FLASH_ATTR(size) \ + (NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | size | \ + P_RW_U_RO) +#else +#define REGION_FLASH_ATTR(size) \ + (NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | size | RO) +#endif +#define REGION_PPB_ATTR(size) (STRONGLY_ORDERED_SHAREABLE | size | P_RW_U_NA) +#define REGION_IO_ATTR(size) (DEVICE_NON_SHAREABLE | size | P_RW_U_NA) + + +/* Region definition data structure */ +struct arm_mpu_region { + /* Region Base Address */ + u32_t base; + /* Region Name */ + const char *name; + /* Region Attributes */ + u32_t attr; +}; + +#define MPU_REGION_ENTRY(_name, _base, _attr) \ + {\ + .name = _name, \ + .base = _base, \ + .attr = _attr, \ + }