diff --git a/boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig b/boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig
index 1592bf8722b5..959ea3fbc277 100644
--- a/boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig
+++ b/boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig
@@ -28,6 +28,7 @@ CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
 # the 8MHz clock signal coming from integrated STLink
 CONFIG_CLOCK_STM32_HSE_BYPASS=y
 # produce 72MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_XTPRE=n
 CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
 CONFIG_CLOCK_STM32_AHB_PRESCALER=1
 # APB1 clock must not to exceed 36MHz limit
diff --git a/boards/arm/olimexino_stm32/olimexino_stm32_defconfig b/boards/arm/olimexino_stm32/olimexino_stm32_defconfig
index 25e902ce7b20..a4bc719139f1 100644
--- a/boards/arm/olimexino_stm32/olimexino_stm32_defconfig
+++ b/boards/arm/olimexino_stm32/olimexino_stm32_defconfig
@@ -32,6 +32,7 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
 # use HSE as PLL input
 CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
 # produce 72MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_XTPRE=n
 CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
 CONFIG_CLOCK_STM32_AHB_PRESCALER=1
 # APB1 clock must not to exceed 36MHz limit
diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig b/boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig
index f584392ba22f..8992599f56c2 100644
--- a/boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig
+++ b/boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig
@@ -38,6 +38,7 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
 # use HSE as PLL input
 CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
 # produce 72MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_XTPRE=n
 CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
 CONFIG_CLOCK_STM32_AHB_PRESCALER=1
 
diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig b/boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig
index 83f874138332..e2fc412b6dc6 100644
--- a/boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig
+++ b/boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig
@@ -33,6 +33,7 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
 # use HSE as PLL input
 CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
 # produce 72MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_XTPRE=n
 CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
 CONFIG_CLOCK_STM32_AHB_PRESCALER=1
 
diff --git a/drivers/clock_control/Kconfig.stm32f1 b/drivers/clock_control/Kconfig.stm32f1
index 12690895d279..d5ec7e077493 100644
--- a/drivers/clock_control/Kconfig.stm32f1
+++ b/drivers/clock_control/Kconfig.stm32f1
@@ -5,6 +5,12 @@
 
 if SOC_SERIES_STM32F1X
 
+config CLOCK_STM32_PLL_XTPRE
+	bool "HSE to PLL /2 prescaler"
+	depends on SOC_STM32F10X_DENSITY_DEVICE && CLOCK_STM32_PLL_SRC_HSE
+	help
+	  Enable this option to enable /2 prescaler on HSE to PLL clock signal
+
 config CLOCK_STM32_PLL_MULTIPLIER
 	int "PLL multiplier"
 	depends on CLOCK_STM32_SYSCLK_SRC_PLL
@@ -18,7 +24,7 @@ config CLOCK_STM32_PLL_MULTIPLIER
 
 config CLOCK_STM32_PLL_PREDIV1
 	int "PREDIV1 Prescaler"
-	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL
 	default 1
 	range 1 16
 	help
diff --git a/drivers/clock_control/clock_stm32f1.c b/drivers/clock_control/clock_stm32f1.c
index 27427cbc99df..e5f919794253 100644
--- a/drivers/clock_control/clock_stm32f1.c
+++ b/drivers/clock_control/clock_stm32f1.c
@@ -36,16 +36,40 @@
 void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
 {
 	/*
+	 * PLLMUL on SOC_STM32F10X_DENSITY_DEVICE
 	 * 2  -> LL_RCC_PLL_MUL_2  -> 0x00000000
 	 * 3  -> LL_RCC_PLL_MUL_3  -> 0x00040000
 	 * 4  -> LL_RCC_PLL_MUL_4  -> 0x00080000
 	 * ...
 	 * 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
 	 *
+	 * PLLMUL on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
+	 * 4  -> LL_RCC_PLL_MUL_4   -> 0x00080000
+	 * ...
+	 * 9  -> LL_RCC_PLL_MUL_9   -> 0x001C0000
+	 * 13 -> LL_RCC_PLL_MUL_6_5 -> 0x00340000
 	 */
 	pllinit->PLLMul = ((CONFIG_CLOCK_STM32_PLL_MULTIPLIER - 2)
 					<< RCC_CFGR_PLLMULL_Pos);
 
+#ifdef CONFIG_SOC_STM32F10X_DENSITY_DEVICE
+	/* PLL prediv */
+#ifdef CONFIG_CLOCK_STM32_PLL_XTPRE
+	/*
+	 * SOC_STM32F10X_DENSITY_DEVICE:
+	 * PLLXPTRE (depends on PLL source HSE)
+	 * HSE/2 used as PLL source
+	 */
+	pllinit->Prediv = LL_RCC_PREDIV_DIV_2;
+#else
+	/*
+	 * SOC_STM32F10X_DENSITY_DEVICE:
+	 * PLLXPTRE (depends on PLL source HSE)
+	 * HSE used as direct PLL source
+	 */
+	pllinit->Prediv = LL_RCC_PREDIV_DIV_1;
+#endif /* CONFIG_CLOCK_STM32_PLL_XTPRE */
+#else
 	/*
 	 * SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
 	 * 1  -> LL_RCC_PREDIV_DIV_1  -> 0x00000000
@@ -55,6 +79,7 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
 	 * 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
 	 */
 	pllinit->Prediv = CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1;
+#endif /* CONFIG_SOC_STM32F10X_DENSITY_DEVICE */
 }
 
 #endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */