From d50061f78e0ee8d83774c0541a2f3f85b88a461f Mon Sep 17 00:00:00 2001
From: serge-sans-paille <serge.guelton@telecom-bretagne.eu>
Date: Tue, 15 Oct 2024 15:58:07 +0200
Subject: [PATCH] Fix clang-17 miscompilation of __riscv_vreinterpret_u8m8

Fix #1059
---
 include/xsimd/types/xsimd_rvv_register.hpp | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/xsimd/types/xsimd_rvv_register.hpp b/include/xsimd/types/xsimd_rvv_register.hpp
index 8887f8a0b..70d760e23 100644
--- a/include/xsimd/types/xsimd_rvv_register.hpp
+++ b/include/xsimd/types/xsimd_rvv_register.hpp
@@ -125,6 +125,15 @@ namespace xsimd
 #undef XSIMD_RVV_MAKE_TYPES
 #undef XSIMD_RVV_MAKE_TYPE
 
+            // Specialization needed for #1058
+            template <>
+            XSIMD_INLINE rvv_type_info<int8_t, rvv_width_m1 * 8>::type
+            rvv_type_info<int8_t, rvv_width_m1 * 8>::bitcast<__rvv_uint8m8_t>(
+                __rvv_uint8m8_t x) noexcept
+            {
+                return __riscv_vreinterpret_i8m8(x);
+            }
+
             // rvv_blob is storage-type abstraction for a vector register.
             template <class T, size_t Width>
             struct rvv_blob : public rvv_type_info<T, Width>