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SAM7.lst
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ARM Macro Assembler Page 1
1 00000000 ;/******************************************************
***********************/
2 00000000 ;/* SAM7.S: Startup file for Atmel AT91SAM7 device serie
s */
3 00000000 ;/******************************************************
***********************/
4 00000000 ;/* <<< Use Configuration Wizard in Context Menu >>>
*/
5 00000000 ;/******************************************************
***********************/
6 00000000 ;/* This file is part of the uVision/ARM development too
ls. */
7 00000000 ;/* Copyright (c) 2005-2006 Keil Software. All rights re
served. */
8 00000000 ;/* This software may only be used under the terms of a
valid, current, */
9 00000000 ;/* end user licence from KEIL for a compatible version
of KEIL software */
10 00000000 ;/* development tools. Nothing else gives you the right
to use this software. */
11 00000000 ;/******************************************************
***********************/
12 00000000
13 00000000
14 00000000 ;/*
15 00000000 ; * The SAM7.S code is executed after CPU Reset. This f
ile may be
16 00000000 ; * translated with the following SET symbols. In uVisi
on these SET
17 00000000 ; * symbols are entered under Options - ASM - Define.
18 00000000 ; *
19 00000000 ; * REMAP: when set the startup code remaps exception v
ectors from
20 00000000 ; * on-chip RAM to address 0.
21 00000000 ; *
22 00000000 ; * RAM_INTVEC: when set the startup code copies except
ion vectors
23 00000000 ; * from on-chip Flash to on-chip RAM.
24 00000000 ; */
25 00000000
26 00000000
27 00000000 ; Standard definitions of Mode bits and Interrupt (I & F
) flags in PSRs
28 00000000
29 00000000 00000010
Mode_USR
EQU 0x10
30 00000000 00000011
Mode_FIQ
EQU 0x11
31 00000000 00000012
Mode_IRQ
EQU 0x12
32 00000000 00000013
Mode_SVC
EQU 0x13
33 00000000 00000017
Mode_ABT
EQU 0x17
ARM Macro Assembler Page 2
34 00000000 0000001B
Mode_UND
EQU 0x1B
35 00000000 0000001F
Mode_SYS
EQU 0x1F
36 00000000
37 00000000 00000080
I_Bit EQU 0x80 ; when I bit is set
, IRQ is disabled
38 00000000 00000040
F_Bit EQU 0x40 ; when F bit is set
, FIQ is disabled
39 00000000
40 00000000
41 00000000 ; Internal Memory Base Addresses
42 00000000 00100000
FLASH_BASE
EQU 0x00100000
43 00000000 00200000
RAM_BASE
EQU 0x00200000
44 00000000
45 00000000
46 00000000 ;// <h> Stack Configuration (Stack Sizes in Bytes)
47 00000000 ;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
48 00000000 ;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
49 00000000 ;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
50 00000000 ;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
51 00000000 ;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
52 00000000 ;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
53 00000000 ;// </h>
54 00000000
55 00000000 00000000
UND_Stack_Size
EQU 0x00000000
56 00000000 00000008
SVC_Stack_Size
EQU 0x00000008
57 00000000 00000000
ABT_Stack_Size
EQU 0x00000000
58 00000000 00000000
FIQ_Stack_Size
EQU 0x00000000
59 00000000 00001580
IRQ_Stack_Size
EQU 0x00001580
60 00000000 00000600
USR_Stack_Size
EQU 0x00000600
61 00000000
63 00000000 00001588
ISR_Stack_Size
EQU (UND_Stack_Size + SVC_Stack_Siz
e + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size
)
64 00000000
65 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
ARM Macro Assembler Page 3
=3
66 00000000
67 00000000 Stack_Mem
SPACE USR_Stack_Size
68 00000600 __initial_sp
SPACE ISR_Stack_Size
69 00001B88 Stack_Top
70 00001B88
71 00001B88
72 00001B88 ;// <h> Heap Configuration
73 00001B88 ;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
74 00001B88 ;// </h>
75 00001B88
76 00001B88 00000000
Heap_Size
EQU 0x00000000
77 00001B88
78 00001B88 AREA HEAP, NOINIT, READWRITE, ALIGN=
3
79 00000000 __heap_base
80 00000000 Heap_Mem
SPACE Heap_Size
81 00000000 __heap_limit
82 00000000
83 00000000
84 00000000 ; Reset Controller (RSTC) definitions
85 00000000 FFFFFD00
RSTC_BASE
EQU 0xFFFFFD00 ; RSTC Base Address
86 00000000 00000008
RSTC_MR EQU 0x08 ; RSTC_MR Offset
87 00000000
88 00000000 ;/*
89 00000000 ;// <e> Reset Controller (RSTC)
90 00000000 ;// <o1.0> URSTEN: User Reset Enable
91 00000000 ;// <i> Enables NRST Pin to generate Reset
92 00000000 ;// <o1.8..11> ERSTL: External Reset Length <0-15>
93 00000000 ;// <i> External Reset Time in 2^(ERSTL+1)
Slow Clock Cycles
94 00000000 ;// </e>
95 00000000 ;*/
96 00000000 00000001
RSTC_SETUP
EQU 1
97 00000000 A5000401
RSTC_MR_Val
EQU 0xA5000401
98 00000000
99 00000000
100 00000000 ; Embedded Flash Controller (EFC) definitions
101 00000000 FFFFFF00
EFC_BASE
EQU 0xFFFFFF00 ; EFC Base Address
102 00000000 00000060
EFC0_FMR
EQU 0x60 ; EFC0_FMR Offset
103 00000000 00000070
EFC1_FMR
ARM Macro Assembler Page 4
EQU 0x70 ; EFC1_FMR Offset
104 00000000
105 00000000 ;// <e> Embedded Flash Controller 0 (EFC0)
106 00000000 ;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <
0-255>
107 00000000 ;// <i> Number of Master Clock Cycles in 1
us
108 00000000 ;// <o1.8..9> FWS: Flash Wait State
109 00000000 ;// <0=> Read: 1 cycle / Write: 2 cycles
110 00000000 ;// <1=> Read: 2 cycle / Write: 3 cycles
111 00000000 ;// <2=> Read: 3 cycle / Write: 4 cycles
112 00000000 ;// <3=> Read: 4 cycle / Write: 4 cycles
113 00000000 ;// </e>
114 00000000 00000001
EFC0_SETUP
EQU 1
115 00000000 00320100
EFC0_FMR_Val
EQU 0x00320100
116 00000000
117 00000000 ;// <e> Embedded Flash Controller 1 (EFC1)
118 00000000 ;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <
0-255>
119 00000000 ;// <i> Number of Master Clock Cycles in 1
us
120 00000000 ;// <o1.8..9> FWS: Flash Wait State
121 00000000 ;// <0=> Read: 1 cycle / Write: 2 cycles
122 00000000 ;// <1=> Read: 2 cycle / Write: 3 cycles
123 00000000 ;// <2=> Read: 3 cycle / Write: 4 cycles
124 00000000 ;// <3=> Read: 4 cycle / Write: 4 cycles
125 00000000 ;// </e>
126 00000000 00000000
EFC1_SETUP
EQU 0
127 00000000 00320100
EFC1_FMR_Val
EQU 0x00320100
128 00000000
129 00000000
130 00000000 ; Watchdog Timer (WDT) definitions
131 00000000 FFFFFD40
WDT_BASE
EQU 0xFFFFFD40 ; WDT Base Address
132 00000000 00000004
WDT_MR EQU 0x04 ; WDT_MR Offset
133 00000000
134 00000000 ;// <e> Watchdog Timer (WDT)
135 00000000 ;// <o1.0..11> WDV: Watchdog Counter Value <0-4095>
136 00000000 ;// <o1.16..27> WDD: Watchdog Delta Value <0-4095>
137 00000000 ;// <o1.12> WDFIEN: Watchdog Fault Interrupt Enabl
e
138 00000000 ;// <o1.13> WDRSTEN: Watchdog Reset Enable
139 00000000 ;// <o1.14> WDRPROC: Watchdog Reset Processor
140 00000000 ;// <o1.28> WDDBGHLT: Watchdog Debug Halt
141 00000000 ;// <o1.29> WDIDLEHLT: Watchdog Idle Halt
142 00000000 ;// <o1.15> WDDIS: Watchdog Disable
143 00000000 ;// </e>
144 00000000 00000001
WDT_SETUP
ARM Macro Assembler Page 5
EQU 1
145 00000000 00008000
WDT_MR_Val
EQU 0x00008000
146 00000000
147 00000000
148 00000000 ; Power Mangement Controller (PMC) definitions
149 00000000 FFFFFC00
PMC_BASE
EQU 0xFFFFFC00 ; PMC Base Address
150 00000000 00000020
PMC_MOR EQU 0x20 ; PMC_MOR Offset
151 00000000 00000024
PMC_MCFR
EQU 0x24 ; PMC_MCFR Offset
152 00000000 0000002C
PMC_PLLR
EQU 0x2C ; PMC_PLLR Offset
153 00000000 00000030
PMC_MCKR
EQU 0x30 ; PMC_MCKR Offset
154 00000000 00000068
PMC_SR EQU 0x68 ; PMC_SR Offset
155 00000000 00000001
PMC_MOSCEN
EQU (1<<0) ; Main Oscillator E
nable
156 00000000 00000002
PMC_OSCBYPASS
EQU (1<<1) ; Main Oscillator B
ypass
157 00000000 0000FF00
PMC_OSCOUNT
EQU (0xFF<<8) ; Main OScillator S
tart-up Time
158 00000000 000000FF
PMC_DIV EQU (0xFF<<0) ; PLL Divider
159 00000000 00003F00
PMC_PLLCOUNT
EQU (0x3F<<8) ; PLL Lock Counter
160 00000000 0000C000
PMC_OUT EQU (0x03<<14) ; PLL Clock Frequen
cy Range
161 00000000 07FF0000
PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier
162 00000000 30000000
PMC_USBDIV
EQU (0x03<<28) ; USB Clock Divider
163 00000000 00000003
PMC_CSS EQU (3<<0) ; Clock Source Sele
ction
164 00000000 0000001C
PMC_PRES
EQU (7<<2) ; Prescaler Selecti
on
165 00000000 00000001
PMC_MOSCS
EQU (1<<0) ; Main Oscillator S
ARM Macro Assembler Page 6
table
166 00000000 00000004
PMC_LOCK
EQU (1<<2) ; PLL Lock Status
167 00000000 00000008
PMC_MCKRDY
EQU (1<<3) ; Master Clock Stat
us
168 00000000
169 00000000 ;// <e> Power Mangement Controller (PMC)
170 00000000 ;// <h> Main Oscillator
171 00000000 ;// <o1.0> MOSCEN: Main Oscillator Enable
172 00000000 ;// <o1.1> OSCBYPASS: Oscillator Bypass
173 00000000 ;// <o1.8..15> OSCCOUNT: Main Oscillator Startup Ti
me <0-255>
174 00000000 ;// </h>
175 00000000 ;// <h> Phase Locked Loop (PLL)
176 00000000 ;// <o2.0..7> DIV: PLL Divider <0-255>
177 00000000 ;// <o2.16..26> MUL: PLL Multiplier <0-2047>
178 00000000 ;// <i> PLL Output is multiplied by MUL+
1
179 00000000 ;// <o2.14..15> OUT: PLL Clock Frequency Range
180 00000000 ;// <0=> 80..160MHz <1=> Reserved
181 00000000 ;// <2=> 150..220MHz <3=> Reserved
182 00000000 ;// <o2.8..13> PLLCOUNT: PLL Lock Counter <0-63>
183 00000000 ;// <o2.28..29> USBDIV: USB Clock Divider
184 00000000 ;// <0=> None <1=> 2 <2=> 4 <3=> Rese
rved
185 00000000 ;// </h>
186 00000000 ;// <o3.0..1> CSS: Clock Source Selection
187 00000000 ;// <0=> Slow Clock
188 00000000 ;// <1=> Main Clock
189 00000000 ;// <2=> Reserved
190 00000000 ;// <3=> PLL Clock
191 00000000 ;// <o3.2..4> PRES: Prescaler
192 00000000 ;// <0=> None
193 00000000 ;// <1=> Clock / 2 <2=> Clock / 4
194 00000000 ;// <3=> Clock / 8 <4=> Clock / 16
195 00000000 ;// <5=> Clock / 32 <6=> Clock / 64
196 00000000 ;// <7=> Reserved
197 00000000 ;// </e>
198 00000000 00000001
PMC_SETUP
EQU 1
199 00000000 00000601
PMC_MOR_Val
EQU 0x00000601
200 00000000 00191C05
PMC_PLLR_Val
EQU 0x00191C05
201 00000000 00000007
PMC_MCKR_Val
EQU 0x00000007
202 00000000
203 00000000
204 00000000 PRESERVE8
205 00000000
206 00000000
207 00000000 ; Area Definition and Entry Point
ARM Macro Assembler Page 7
208 00000000 ; Startup Code must be linked first at Address at which
it expects to run.
209 00000000
210 00000000 AREA RESET, CODE, READONLY
211 00000000 ARM
212 00000000
213 00000000
214 00000000 ; Exception Vectors
215 00000000 ; Mapped to Address 0.
216 00000000 ; Absolute addressing mode must be used.
217 00000000 ; Dummy Handlers are implemented as infinite loops whic
h can be modified.
218 00000000
219 00000000 E59FF018
Vectors LDR PC,Reset_Addr
220 00000004 E59FF018 LDR PC,Undef_Addr
221 00000008 E59FF018 LDR PC,SWI_Addr
222 0000000C E59FF018 LDR PC,PAbt_Addr
223 00000010 E59FF018 LDR PC,DAbt_Addr
224 00000014 E1A00000 NOP ; Reserved Vector
225 00000018 ; LDR PC,IRQ_Addr
226 00000018 E51FFF20 LDR PC,[PC,#-0xF20] ; Vector From A
IC_IVR
227 0000001C ; LDR PC,FIQ_Addr
228 0000001C E51FFF20 LDR PC,[PC,#-0xF20] ; Vector From A
IC_FVR
229 00000020
230 00000020 00000000
Reset_Addr
DCD Reset_Handler
231 00000024 00000000
Undef_Addr
DCD Undef_Handler
232 00000028 00000000
SWI_Addr
DCD SWI_Handler
233 0000002C 00000000
PAbt_Addr
DCD PAbt_Handler
234 00000030 00000000
DAbt_Addr
DCD DAbt_Handler
235 00000034 00000000 DCD 0 ; Reserved Address
236 00000038 00000000
IRQ_Addr
DCD IRQ_Handler
237 0000003C 00000000
FIQ_Addr
DCD FIQ_Handler
238 00000040
239 00000040 EAFFFFFE
Undef_Handler
B Undef_Handler
240 00000044 EAFFFFFE
SWI_Handler
B SWI_Handler
241 00000048 EAFFFFFE
PAbt_Handler
B PAbt_Handler
ARM Macro Assembler Page 8
242 0000004C EAFFFFFE
DAbt_Handler
B DAbt_Handler
243 00000050 EAFFFFFE
IRQ_Handler
B IRQ_Handler
244 00000054 EAFFFFFE
FIQ_Handler
B FIQ_Handler
245 00000058
246 00000058
247 00000058 ; Reset Handler
248 00000058
249 00000058 EXPORT Reset_Handler
250 00000058 Reset_Handler
251 00000058
252 00000058
253 00000058 ; Setup RSTC
254 00000058 IF RSTC_SETUP != 0
255 00000058 E59F00C8 LDR R0, =RSTC_BASE
256 0000005C E59F10C8 LDR R1, =RSTC_MR_Val
257 00000060 E5801008 STR R1, [R0, #RSTC_MR]
258 00000064 ENDIF
259 00000064
260 00000064
261 00000064 ; Setup EFC0
262 00000064 IF EFC0_SETUP != 0
263 00000064 E59F00C4 LDR R0, =EFC_BASE
264 00000068 E59F10C4 LDR R1, =EFC0_FMR_Val
265 0000006C E5801060 STR R1, [R0, #EFC0_FMR]
266 00000070 ENDIF
267 00000070
268 00000070 ; Setup EFC1
269 00000070 IF EFC1_SETUP != 0
273 ENDIF
274 00000070
275 00000070 ; Setup WDT
276 00000070 IF WDT_SETUP != 0
277 00000070 E59F00C0 LDR R0, =WDT_BASE
278 00000074 E3A01902 LDR R1, =WDT_MR_Val
279 00000078 E5801004 STR R1, [R0, #WDT_MR]
280 0000007C ENDIF
281 0000007C
282 0000007C
283 0000007C ; Setup PMC
284 0000007C IF PMC_SETUP != 0
285 0000007C E59F00B8 LDR R0, =PMC_BASE
286 00000080
287 00000080 ; Setup Main Oscillator
288 00000080 E59F10B8 LDR R1, =PMC_MOR_Val
289 00000084 E5801020 STR R1, [R0, #PMC_MOR]
290 00000088
291 00000088 ; Wait until Main Oscillator is stablilized
292 00000088 IF (PMC_MOR_Val:AND:PMC_MOSCEN) !=
0
293 00000088 E5902068
MOSCS_Loop
LDR R2, [R0, #PMC_SR]
294 0000008C E2122001 ANDS R2, R2, #PMC_MOSCS
ARM Macro Assembler Page 9
295 00000090 0AFFFFFC BEQ MOSCS_Loop
296 00000094 ENDIF
297 00000094
298 00000094 ; Setup the PLL
299 00000094 IF (PMC_PLLR_Val:AND:PMC_MUL) != 0
300 00000094 E59F10A8 LDR R1, =PMC_PLLR_Val
301 00000098 E580102C STR R1, [R0, #PMC_PLLR]
302 0000009C
303 0000009C ; Wait until PLL is stabilized
304 0000009C E5902068
PLL_Loop
LDR R2, [R0, #PMC_SR]
305 000000A0 E2122004 ANDS R2, R2, #PMC_LOCK
306 000000A4 0AFFFFFC BEQ PLL_Loop
307 000000A8 ENDIF
308 000000A8
309 000000A8 ; Select Clock
310 000000A8 IF (PMC_MCKR_Val:AND:PMC_CSS) == 1
; Main Clock Select
ed
334 ENDIF ; Select Clock
335 000000D4 ENDIF ; PMC_SETUP
336 000000D4
337 000000D4
338 000000D4 ; Copy Exception Vectors to Internal RAM
339 000000D4
340 000000D4 IF :DEF:RAM_INTVEC
347 ENDIF
348 000000D4
349 000000D4
350 000000D4 ; Remap on-chip RAM to address 0
351 000000D4
352 000000D4 FFFFFF00
MC_BASE EQU 0xFFFFFF00 ; MC Base Address
353 000000D4 00000000
MC_RCR EQU 0x00 ; MC_RCR Offset
354 000000D4
355 000000D4 IF :DEF:REMAP
359 ENDIF
360 000000D4
361 000000D4
362 000000D4 ; Setup Stack for each mode
363 000000D4
364 000000D4 E59F006C LDR R0, =Stack_Top
365 000000D8
366 000000D8 ; Enter Undefined Instruction Mode and set its Stack Po
inter
367 000000D8 E321F0DB MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F
_Bit
368 000000DC E1A0D000 MOV SP, R0
369 000000E0 E2400000 SUB R0, R0, #UND_Stack_Size
370 000000E4
371 000000E4 ; Enter Abort Mode and set its Stack Pointer
372 000000E4 E321F0D7 MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F
_Bit
373 000000E8 E1A0D000 MOV SP, R0
374 000000EC E2400000 SUB R0, R0, #ABT_Stack_Size
375 000000F0
ARM Macro Assembler Page 10
376 000000F0 ; Enter FIQ Mode and set its Stack Pointer
377 000000F0 E321F0D1 MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F
_Bit
378 000000F4 E1A0D000 MOV SP, R0
379 000000F8 E2400000 SUB R0, R0, #FIQ_Stack_Size
380 000000FC
381 000000FC ; Enter IRQ Mode and set its Stack Pointer
382 000000FC E321F0D2 MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F
_Bit
383 00000100 E1A0D000 MOV SP, R0
384 00000104 E2400D56 SUB R0, R0, #IRQ_Stack_Size
385 00000108
386 00000108 ; Enter Supervisor Mode and set its Stack Pointer
387 00000108 E321F0D3 MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F
_Bit
388 0000010C E1A0D000 MOV SP, R0
389 00000110 E2400008 SUB R0, R0, #SVC_Stack_Size
390 00000114
391 00000114 ; Enter User Mode and set its Stack Pointer
392 00000114 E321F010 MSR CPSR_c, #Mode_USR
393 00000118 IF :DEF:__MICROLIB
398 00000118
399 00000118 E1A0D000 MOV SP, R0
400 0000011C E24DAC06 SUB SL, SP, #USR_Stack_Size
401 00000120
402 00000120 ENDIF
403 00000120
404 00000120
405 00000120 ; Enter the C code
406 00000120
407 00000120 IMPORT __main
408 00000120 E59F0024 LDR R0, =__main
409 00000124 E12FFF10 BX R0
410 00000128
411 00000128
412 00000128 IF :DEF:__MICROLIB
418 00000128 ; User Initial Stack & Heap
419 00000128 FFFFFD00
A5000401
FFFFFF00
00320100
FFFFFD40
FFFFFC00
00000601
00191C05
00000000
00000000 AREA |.text|, CODE, READONLY
420 00000000
421 00000000 IMPORT __use_two_region_memory
422 00000000 EXPORT __user_initial_stackheap
423 00000000 __user_initial_stackheap
424 00000000
425 00000000 E59F000C LDR R0, = Heap_Mem
426 00000004 E59F100C LDR R1, =(Stack_Mem + USR_Stack_Siz
e)
427 00000008 E59F2004 LDR R2, = (Heap_Mem + Heap_Siz
e)
428 0000000C E59F3008 LDR R3, = Stack_Mem
429 00000010 E12FFF1E BX LR
ARM Macro Assembler Page 11
430 00000014 ENDIF
431 00000014
432 00000014
433 00000014 END
00000000
00000600
00000000
Command Line: --debug --xref --apcs=interwork --depend=.\Outputs\SAM7.d -o.\Out
puts\SAM7.o -ID:\KEIL4\ARM\INC -ID:\KEIL4\ARM\INC\Atmel\SAM7S --list=.\SAM7.lst
Drivers\SAM7.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
STACK 00000000
Symbol: STACK
Definitions
At line 65 in file Drivers\SAM7.s
Uses
None
Comment: STACK unused
Stack_Mem 00000000
Symbol: Stack_Mem
Definitions
At line 67 in file Drivers\SAM7.s
Uses
At line 426 in file Drivers\SAM7.s
At line 428 in file Drivers\SAM7.s
Stack_Top 00001B88
Symbol: Stack_Top
Definitions
At line 69 in file Drivers\SAM7.s
Uses
At line 364 in file Drivers\SAM7.s
Comment: Stack_Top used once
__initial_sp 00000600
Symbol: __initial_sp
Definitions
At line 68 in file Drivers\SAM7.s
Uses
None
Comment: __initial_sp unused
4 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
HEAP 00000000
Symbol: HEAP
Definitions
At line 78 in file Drivers\SAM7.s
Uses
None
Comment: HEAP unused
Heap_Mem 00000000
Symbol: Heap_Mem
Definitions
At line 80 in file Drivers\SAM7.s
Uses
At line 425 in file Drivers\SAM7.s
At line 427 in file Drivers\SAM7.s
__heap_base 00000000
Symbol: __heap_base
Definitions
At line 79 in file Drivers\SAM7.s
Uses
None
Comment: __heap_base unused
__heap_limit 00000000
Symbol: __heap_limit
Definitions
At line 81 in file Drivers\SAM7.s
Uses
None
Comment: __heap_limit unused
4 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
DAbt_Addr 00000030
Symbol: DAbt_Addr
Definitions
At line 234 in file Drivers\SAM7.s
Uses
At line 223 in file Drivers\SAM7.s
Comment: DAbt_Addr used once
DAbt_Handler 0000004C
Symbol: DAbt_Handler
Definitions
At line 242 in file Drivers\SAM7.s
Uses
At line 234 in file Drivers\SAM7.s
At line 242 in file Drivers\SAM7.s
FIQ_Addr 0000003C
Symbol: FIQ_Addr
Definitions
At line 237 in file Drivers\SAM7.s
Uses
None
Comment: FIQ_Addr unused
FIQ_Handler 00000054
Symbol: FIQ_Handler
Definitions
At line 244 in file Drivers\SAM7.s
Uses
At line 237 in file Drivers\SAM7.s
At line 244 in file Drivers\SAM7.s
IRQ_Addr 00000038
Symbol: IRQ_Addr
Definitions
At line 236 in file Drivers\SAM7.s
Uses
None
Comment: IRQ_Addr unused
IRQ_Handler 00000050
Symbol: IRQ_Handler
Definitions
At line 243 in file Drivers\SAM7.s
Uses
At line 236 in file Drivers\SAM7.s
At line 243 in file Drivers\SAM7.s
MOSCS_Loop 00000088
Symbol: MOSCS_Loop
Definitions
At line 293 in file Drivers\SAM7.s
Uses
At line 295 in file Drivers\SAM7.s
Comment: MOSCS_Loop used once
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
PAbt_Addr 0000002C
Symbol: PAbt_Addr
Definitions
At line 233 in file Drivers\SAM7.s
Uses
At line 222 in file Drivers\SAM7.s
Comment: PAbt_Addr used once
PAbt_Handler 00000048
Symbol: PAbt_Handler
Definitions
At line 241 in file Drivers\SAM7.s
Uses
At line 233 in file Drivers\SAM7.s
At line 241 in file Drivers\SAM7.s
PLL_Loop 0000009C
Symbol: PLL_Loop
Definitions
At line 304 in file Drivers\SAM7.s
Uses
At line 306 in file Drivers\SAM7.s
Comment: PLL_Loop used once
RESET 00000000
Symbol: RESET
Definitions
At line 210 in file Drivers\SAM7.s
Uses
None
Comment: RESET unused
Reset_Addr 00000020
Symbol: Reset_Addr
Definitions
At line 230 in file Drivers\SAM7.s
Uses
At line 219 in file Drivers\SAM7.s
Comment: Reset_Addr used once
Reset_Handler 00000058
Symbol: Reset_Handler
Definitions
At line 250 in file Drivers\SAM7.s
Uses
At line 230 in file Drivers\SAM7.s
At line 249 in file Drivers\SAM7.s
SWI_Addr 00000028
Symbol: SWI_Addr
Definitions
At line 232 in file Drivers\SAM7.s
Uses
At line 221 in file Drivers\SAM7.s
Comment: SWI_Addr used once
SWI_Handler 00000044
ARM Macro Assembler Page 3 Alphabetic symbol ordering
Relocatable symbols
Symbol: SWI_Handler
Definitions
At line 240 in file Drivers\SAM7.s
Uses
At line 232 in file Drivers\SAM7.s
At line 240 in file Drivers\SAM7.s
Undef_Addr 00000024
Symbol: Undef_Addr
Definitions
At line 231 in file Drivers\SAM7.s
Uses
At line 220 in file Drivers\SAM7.s
Comment: Undef_Addr used once
Undef_Handler 00000040
Symbol: Undef_Handler
Definitions
At line 239 in file Drivers\SAM7.s
Uses
At line 231 in file Drivers\SAM7.s
At line 239 in file Drivers\SAM7.s
Vectors 00000000
Symbol: Vectors
Definitions
At line 219 in file Drivers\SAM7.s
Uses
None
Comment: Vectors unused
WAIT_Rdy1 000000B4
Symbol: WAIT_Rdy1
Definitions
At line 326 in file Drivers\SAM7.s
Uses
At line 328 in file Drivers\SAM7.s
Comment: WAIT_Rdy1 used once
WAIT_Rdy2 000000C8
Symbol: WAIT_Rdy2
Definitions
At line 331 in file Drivers\SAM7.s
Uses
At line 333 in file Drivers\SAM7.s
Comment: WAIT_Rdy2 used once
20 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 419 in file Drivers\SAM7.s
Uses
None
Comment: .text unused
__user_initial_stackheap 00000000
Symbol: __user_initial_stackheap
Definitions
At line 423 in file Drivers\SAM7.s
Uses
At line 422 in file Drivers\SAM7.s
Comment: __user_initial_stackheap used once
2 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Absolute symbols
ABT_Stack_Size 00000000
Symbol: ABT_Stack_Size
Definitions
At line 57 in file Drivers\SAM7.s
Uses
At line 63 in file Drivers\SAM7.s
At line 374 in file Drivers\SAM7.s
EFC0_FMR 00000060
Symbol: EFC0_FMR
Definitions
At line 102 in file Drivers\SAM7.s
Uses
At line 265 in file Drivers\SAM7.s
Comment: EFC0_FMR used once
EFC0_FMR_Val 00320100
Symbol: EFC0_FMR_Val
Definitions
At line 115 in file Drivers\SAM7.s
Uses
At line 264 in file Drivers\SAM7.s
Comment: EFC0_FMR_Val used once
EFC0_SETUP 00000001
Symbol: EFC0_SETUP
Definitions
At line 114 in file Drivers\SAM7.s
Uses
At line 262 in file Drivers\SAM7.s
Comment: EFC0_SETUP used once
EFC1_FMR 00000070
Symbol: EFC1_FMR
Definitions
At line 103 in file Drivers\SAM7.s
Uses