****** START compiling System.Threading.Monitor:Exit(System.Object) (MethodHash=cb7d45e7) Generating code for Unix arm64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false OPTIONS: Jit invoked for ngen IL to import: IL_0000 02 ldarg.0 IL_0001 28 68 37 00 06 call 0x6003768 IL_0006 2a ret lvaSetClass: setting class for V00 to (0000000000420068) System.Object Arg #0 passed in register(s) x0 Parameter V00 ABI info: [00..08) reg x0 lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace. Local V01 should not be enregistered because: it is address exposed ; Initial local variable assignments ; ; V00 arg0 ref class-hnd ; V01 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" *************** In compInitDebuggingInfo() for System.Threading.Monitor:Exit(System.Object) getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 1 VarNum LVNum Name Beg End 0: 00h 00h V00 arg0 000h 007h info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.Monitor:Exit(System.Object) Jump targets: none New Basic Block BB01 [0000] created. BB01 [0000] [000..007) INLINER: during 'prejit' result 'PreJIT Success' reason 'PreJIT Success' for 'n/a' calling 'System.Threading.Monitor:Exit(System.Object)' INLINER: during 'prejit' result 'PreJIT Success' reason 'PreJIT Success' IL Code Size,Instr 7, 3, Basic Block count 1, Local Variable Num,Ref count 2, 1 for method System.Threading.Monitor:Exit(System.Object) OPTIONS: opts.MinOpts() == false Basic block list for 'System.Threading.Monitor:Exit(System.Object)' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..007) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..007) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Profile incorporation BBOPT not set *************** Finishing PHASE Profile incorporation [no changes] *************** Starting PHASE Canonicalize entry *************** Finishing PHASE Canonicalize entry [no changes] *************** Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.Monitor:Exit(System.Object)' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) call 06003768 (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT) In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 info.compCompHnd->canTailCall returned false for call [000001] CheckCanInline: fetching method info for inline candidate Release -- context 00000000004206E1 Class context: System.Threading.ObjectHeader INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.ObjectHeader:Release(System.Object)' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00000 ( 0x000[E-] ... ??? ) [000001] I-C-G------ * CALL void System.Threading.ObjectHeader:Release(System.Object) (exactContextHandle=0x00000000004206E1) [000000] ----------- arg0 \--* LCL_VAR ref V00 arg0 [ 0] 6 (0x006) ret STMT00001 ( 0x006[E-] ... ??? ) [000002] ----------- * RETURN void *************** Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..007) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..007) (return), preds={} succs={} ***** BB01 [0000] STMT00000 ( 0x000[E-] ... 0x006 ) [000001] I-C-G------ * CALL void System.Threading.ObjectHeader:Release(System.Object) (exactContextHandle=0x00000000004206E1) [000000] ----------- arg0 \--* LCL_VAR ref V00 arg0 ***** BB01 [0000] STMT00001 ( 0x006[E-] ... ??? ) [000002] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import [no changes] *************** Starting PHASE Morph - Init *************** Finishing PHASE Morph - Init [no changes] *************** Starting PHASE Morph - Inlining Expanding INLINE_CANDIDATE in statement STMT00000 in BB01: STMT00000 ( 0x000[E-] ... 0x006 ) [000001] I-C-G------ * CALL void System.Threading.ObjectHeader:Release(System.Object) (exactContextHandle=0x00000000004206E1) [000000] ----------- arg0 \--* LCL_VAR ref V00 arg0 IL argument #0: is a local var [000000] ----------- * LCL_VAR ref V00 arg0 Inlinee local #02 is pinned INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.ObjectHeader:Release(System.Object) set to 0x00000000004206E1: Invoking compiler for the inlinee method System.Threading.ObjectHeader:Release(System.Object) : IL to import: IL_0000 02 ldarg.0 IL_0001 72 61 10 00 70 ldstr 0x70001061 IL_0006 28 2b 07 00 06 call 0x600072B IL_000b 28 d7 36 00 06 call 0x60036D7 IL_0010 0a stloc.0 IL_0011 06 ldloc.0 IL_0012 06 ldloc.0 IL_0013 17 ldc.i4.1 IL_0014 59 sub IL_0015 1f 1f ldc.i4.s 0x1F IL_0017 63 shr IL_0018 60 or IL_0019 0a stloc.0 IL_001a 02 ldarg.0 IL_001b 28 ef 6f 00 06 call 0x6006FEF IL_0020 0c stloc.2 IL_0021 08 ldloc.2 IL_0022 e0 conv.u IL_0023 28 5c 37 00 06 call 0x600375C IL_0028 0d stloc.3 IL_0029 09 ldloc.3 IL_002a 4a ldind.i4 IL_002b 13 04 stloc.s 0x4 IL_002d 11 04 ldloc.s 0x4 IL_002f 20 ff ff 00 00 ldc.i4 0xFFFF IL_0034 5f and IL_0035 06 ldloc.0 IL_0036 33 37 bne.un.s 55 (IL_006f) IL_0038 11 04 ldloc.s 0x4 IL_003a 20 00 00 00 08 ldc.i4 0x8000000 IL_003f 5f and IL_0040 2d 2d brtrue.s 45 (IL_006f) IL_0042 11 04 ldloc.s 0x4 IL_0044 20 00 00 3f 00 ldc.i4 0x3F0000 IL_0049 5f and IL_004a 2d 0a brtrue.s 10 (IL_0056) IL_004c 11 04 ldloc.s 0x4 IL_004e 20 00 00 ff ff ldc.i4 0xFFFF0000 IL_0053 5f and IL_0054 2b 08 br.s 8 (IL_005e) IL_0056 11 04 ldloc.s 0x4 IL_0058 20 00 00 01 00 ldc.i4 0x10000 IL_005d 59 sub IL_005e 13 06 stloc.s 0x6 IL_0060 09 ldloc.3 IL_0061 11 06 ldloc.s 0x6 IL_0063 11 04 ldloc.s 0x4 IL_0065 28 12 37 00 06 call 0x6003712 IL_006a 11 04 ldloc.s 0x4 IL_006c 33 bb bne.un.s -69 (IL_0029) IL_006e 2a ret IL_006f 11 04 ldloc.s 0x4 IL_0071 12 05 ldloca.s 0x5 IL_0073 28 61 37 00 06 call 0x6003761 IL_0078 2d 06 brtrue.s 6 (IL_0080) IL_007a 73 ae 39 00 06 newobj 0x60039AE IL_007f 7a throw IL_0080 11 05 ldloc.s 0x5 IL_0082 28 72 37 00 06 call 0x6003772 IL_0087 0b stloc.1 IL_0088 16 ldc.i4.0 IL_0089 e0 conv.u IL_008a 0c stloc.2 IL_008b 07 ldloc.1 IL_008c 06 ldloc.0 IL_008d 6f e2 36 00 06 callvirt 0x60036E2 IL_0092 2a ret INLINER impTokenLookupContextHandle for System.Threading.ObjectHeader:Release(System.Object) is 0x00000000004206E1. *************** In compInitDebuggingInfo() for System.Threading.ObjectHeader:Release(System.Object) info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.ObjectHeader:Release(System.Object) Jump targets: IL_0029 IL_0056 IL_005e IL_006f IL_0080 New Basic Block BB01 [0001] created. BB01 [0001] [000..029) New Basic Block BB02 [0002] created. BB02 [0002] [029..038) New Basic Block BB03 [0003] created. BB03 [0003] [038..042) New Basic Block BB04 [0004] created. BB04 [0004] [042..04C) New Basic Block BB05 [0005] created. BB05 [0005] [04C..056) New Basic Block BB06 [0006] created. BB06 [0006] [056..05E) New Basic Block BB07 [0007] created. BB07 [0007] [05E..06E) New Basic Block BB08 [0008] created. BB08 [0008] [06E..06F) New Basic Block BB09 [0009] created. BB09 [0009] [06F..07A) New Basic Block BB10 [0010] created. BB10 [0010] [07A..080) New Basic Block BB11 [0011] created. BB11 [0011] [080..093) setting likelihood of BB01 -> BB02 to 1 setting likelihood of BB02 -> BB09 to 0.5 setting likelihood of BB02 -> BB03 to 0.5 setting likelihood of BB03 -> BB09 to 0.5 setting likelihood of BB03 -> BB04 to 0.5 setting likelihood of BB04 -> BB06 to 0.5 setting likelihood of BB04 -> BB05 to 0.5 setting likelihood of BB05 -> BB07 to 1 setting likelihood of BB06 -> BB07 to 1 setting likelihood of BB07 -> BB02 to 0.5 setting likelihood of BB07 -> BB08 to 0.5 setting likelihood of BB09 -> BB11 to 1 setting likelihood of BB09 -> BB10 to 0 Basic block list for 'System.Threading.ObjectHeader:Release(System.Object)' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [000..029)-> BB02(1) (always) BB02 [0002] 2 BB01,BB07 1 [029..038)-> BB09(0.5),BB03(0.5) ( cond ) bwd bwd-target BB03 [0003] 1 BB02 1 [038..042)-> BB09(0.5),BB04(0.5) ( cond ) bwd BB04 [0004] 1 BB03 1 [042..04C)-> BB06(0.5),BB05(0.5) ( cond ) bwd BB05 [0005] 1 BB04 1 [04C..056)-> BB07(1) (always) bwd BB06 [0006] 1 BB04 1 [056..05E)-> BB07(1) (always) bwd BB07 [0007] 2 BB05,BB06 1 [05E..06E)-> BB02(0.5),BB08(0.5) ( cond ) bwd bwd-src BB08 [0008] 1 BB07 1 [06E..06F) (return) BB09 [0009] 2 BB02,BB03 1 [06F..07A)-> BB11(1),BB10(0) ( cond ) BB10 [0010] 1 BB09 0 [07A..080) (throw ) rare BB11 [0011] 1 BB09 1 [080..093) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000001] Starting PHASE Pre-import *************** Inline @[000001] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [000..029)-> BB02(1) (always) BB02 [0002] 2 BB01,BB07 1 [029..038)-> BB09(0.5),BB03(0.5) ( cond ) bwd bwd-target BB03 [0003] 1 BB02 1 [038..042)-> BB09(0.5),BB04(0.5) ( cond ) bwd BB04 [0004] 1 BB03 1 [042..04C)-> BB06(0.5),BB05(0.5) ( cond ) bwd BB05 [0005] 1 BB04 1 [04C..056)-> BB07(1) (always) bwd BB06 [0006] 1 BB04 1 [056..05E)-> BB07(1) (always) bwd BB07 [0007] 2 BB05,BB06 1 [05E..06E)-> BB02(0.5),BB08(0.5) ( cond ) bwd bwd-src BB08 [0008] 1 BB07 1 [06E..06F) (return) BB09 [0009] 2 BB02,BB03 1 [06F..07A)-> BB11(1),BB10(0) ( cond ) BB10 [0010] 1 BB09 0 [07A..080) (throw ) rare BB11 [0011] 1 BB09 1 [080..093) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0001] [000..029) -> BB02(1) (always), preds={} succs={BB02} ------------ BB02 [0002] [029..038) -> BB09(0.5),BB03(0.5) (cond), preds={BB01,BB07} succs={BB03,BB09} ------------ BB03 [0003] [038..042) -> BB09(0.5),BB04(0.5) (cond), preds={BB02} succs={BB04,BB09} ------------ BB04 [0004] [042..04C) -> BB06(0.5),BB05(0.5) (cond), preds={BB03} succs={BB05,BB06} ------------ BB05 [0005] [04C..056) -> BB07(1) (always), preds={BB04} succs={BB07} ------------ BB06 [0006] [056..05E) -> BB07(1) (always), preds={BB04} succs={BB07} ------------ BB07 [0007] [05E..06E) -> BB02(0.5),BB08(0.5) (cond), preds={BB05,BB06} succs={BB08,BB02} ------------ BB08 [0008] [06E..06F) (return), preds={BB07} succs={} ------------ BB09 [0009] [06F..07A) -> BB11(1),BB10(0) (cond), preds={BB02,BB03} succs={BB10,BB11} ------------ BB10 [0010] [07A..080) (throw), preds={BB09} succs={} ------------ BB11 [0011] [080..093) (return), preds={BB09} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000001] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000001] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [000..029)-> BB02(1) (always) BB02 [0002] 2 BB01,BB07 1 [029..038)-> BB09(0.5),BB03(0.5) ( cond ) bwd bwd-target BB03 [0003] 1 BB02 1 [038..042)-> BB09(0.5),BB04(0.5) ( cond ) bwd BB04 [0004] 1 BB03 1 [042..04C)-> BB06(0.5),BB05(0.5) ( cond ) bwd BB05 [0005] 1 BB04 1 [04C..056)-> BB07(1) (always) bwd BB06 [0006] 1 BB04 1 [056..05E)-> BB07(1) (always) bwd BB07 [0007] 2 BB05,BB06 1 [05E..06E)-> BB02(0.5),BB08(0.5) ( cond ) bwd bwd-src BB08 [0008] 1 BB07 1 [06E..06F) (return) BB09 [0009] 2 BB02,BB03 1 [06F..07A)-> BB11(1),BB10(0) ( cond ) BB10 [0010] 1 BB09 0 [07A..080) (throw ) rare BB11 [0011] 1 BB09 1 [080..093) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0001] [000..029) -> BB02(1) (always), preds={} succs={BB02} ------------ BB02 [0002] [029..038) -> BB09(0.5),BB03(0.5) (cond), preds={BB01,BB07} succs={BB03,BB09} ------------ BB03 [0003] [038..042) -> BB09(0.5),BB04(0.5) (cond), preds={BB02} succs={BB04,BB09} ------------ BB04 [0004] [042..04C) -> BB06(0.5),BB05(0.5) (cond), preds={BB03} succs={BB05,BB06} ------------ BB05 [0005] [04C..056) -> BB07(1) (always), preds={BB04} succs={BB07} ------------ BB06 [0006] [056..05E) -> BB07(1) (always), preds={BB04} succs={BB07} ------------ BB07 [0007] [05E..06E) -> BB02(0.5),BB08(0.5) (cond), preds={BB05,BB06} succs={BB08,BB02} ------------ BB08 [0008] [06E..06F) (return), preds={BB07} succs={} ------------ BB09 [0009] [06F..07A) -> BB11(1),BB10(0) (cond), preds={BB02,BB03} succs={BB10,BB11} ------------ BB10 [0010] [07A..080) (throw), preds={BB09} succs={} ------------ BB11 [0011] [080..093) (return), preds={BB09} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000001] Starting PHASE Canonicalize entry *************** Inline @[000001] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000001] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.ObjectHeader:Release(System.Object)' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldstr 70001061 [ 2] 6 (0x006) call 0600072B In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 Named Intrinsic System.ArgumentNullException.ThrowIfNull: Recognized CheckCanInline: fetching method info for inline candidate ThrowIfNull -- context 0000000000420629 Class context: System.ArgumentNullException INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.ObjectHeader:Release(System.Object)' calling 'System.ArgumentNullException:ThrowIfNull(System.Object,System.String)' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' Named Intrinsic System.ArgumentNullException.ThrowIfNull: Recognized Named Intrinsic System.ArgumentNullException.ThrowIfNull: Recognized Named Intrinsic System.ArgumentNullException.ThrowIfNull: Recognized STMT00002 ( 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-] [000004] I-C-G------ * CALL void System.ArgumentNullException:ThrowIfNull(System.Object,System.String) (exactContextHandle=0x0000000000420629) [000000] ----------- arg0 +--* LCL_VAR ref V00 arg0 [000003] ----------- arg1 \--* CNS_STR ref [ 0] 11 (0x00b) call 060036D7 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 CheckCanInline: fetching method info for inline candidate get_CurrentManagedThreadIdUnchecked -- context 0000000000420721 Class context: System.Threading.ManagedThreadId INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.ObjectHeader:Release(System.Object)' calling 'System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00003 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000005] I-C-G------ * CALL int System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int (exactContextHandle=0x0000000000420721) [ 1] 16 (0x010) stloc.0 lvaGrabTemp returning 2 (V02 tmp1) (a long lifetime temp) called for Inline stloc first use temp. STMT00004 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000006] --C-------- \--* RET_EXPR int (for [000005]) [ 0] 17 (0x011) ldloc.0 [ 1] 18 (0x012) ldloc.0 [ 2] 19 (0x013) ldc.i4.1 1 [ 3] 20 (0x014) sub [ 2] 21 (0x015) ldc.i4.s 31 [ 3] 23 (0x017) shr [ 2] 24 (0x018) or [ 1] 25 (0x019) stloc.0 STMT00005 ( 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 [ 0] 26 (0x01a) ldarg.0 [ 1] 27 (0x01b) call 06006FEF In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 CheckCanInline: fetching method info for inline candidate GetMethodTableRef -- context 0000000000420301 Class context: System.Runtime.CompilerServices.RuntimeHelpers INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.ObjectHeader:Release(System.Object)' calling 'System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00006 ( 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000017] I-C-G------ * CALL byref System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref (exactContextHandle=0x0000000000420301) [000016] ----------- arg0 \--* LCL_VAR ref V00 arg0 [ 1] 32 (0x020) stloc.2 lvaGrabTemp returning 3 (V03 tmp2) (a long lifetime temp) called for Inline stloc first use temp. STMT00007 ( 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000018] --C-------- \--* RET_EXPR byref (for [000017]) [ 0] 33 (0x021) ldloc.2 [ 1] 34 (0x022) conv.u [ 1] 35 (0x023) call 0600375C In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0 CheckCanInline: fetching method info for inline candidate GetHeaderPtr -- context 00000000004206E1 Class context: System.Threading.ObjectHeader INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.ObjectHeader:Release(System.Object)' calling 'System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00008 ( 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000022] I-C-G------ * CALL long System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong (exactContextHandle=0x00000000004206E1) [000021] ---------U- arg0 \--* CAST long <- ulong <- byref [000020] ----------- \--* LCL_VAR byref V03 tmp2 [ 1] 40 (0x028) stloc.3 lvaGrabTemp returning 4 (V04 tmp3) (a long lifetime temp) called for Inline stloc first use temp. Marked V04 as a single def temp STMT00009 ( 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000023] --C-------- \--* RET_EXPR long (for [000022]) impImportBlockPending for BB02 Importing BB02 (PC=041) of 'System.Threading.ObjectHeader:Release(System.Object)' [ 0] 41 (0x029) ldloc.3 [ 1] 42 (0x02a) ldind.i4 [ 1] 43 (0x02b) stloc.s 4 lvaGrabTemp returning 5 (V05 tmp4) (a long lifetime temp) called for Inline stloc first use temp. Marked V05 as a single def temp STMT00010 ( 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 [ 0] 45 (0x02d) ldloc.s 4 [ 1] 47 (0x02f) ldc.i4 65535 [ 2] 52 (0x034) and fgMorphTree (after 0): [000031] ----------- * CAST int <- ushort <- int [000028] ----------- \--* LCL_VAR int V05 tmp4 Folding binary operator with a constant operand: [000030] ----------- * AND int [000028] ----------- +--* LCL_VAR int V05 tmp4 [000029] ----------- \--* CNS_INT int 0xFFFF Transformed into: [000031] ----------- * CAST int <- ushort <- int [000028] ----------- \--* LCL_VAR int V05 tmp4 [ 1] 53 (0x035) ldloc.0 [ 2] 54 (0x036) bne.un.s STMT00011 ( 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 impImportBlockPending for BB03 impImportBlockPending for BB09 Importing BB09 (PC=111) of 'System.Threading.ObjectHeader:Release(System.Object)' [ 0] 111 (0x06f) ldloc.s 4 [ 1] 113 (0x071) ldloca.s 5 lvaGrabTemp returning 6 (V06 tmp5) (a long lifetime temp) called for Inline ldloca(s) first use temp. [ 2] 115 (0x073) call 06003761 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ubyte, structSize is 0 CheckCanInline: fetching method info for inline candidate GetSyncEntryIndex -- context 00000000004206E1 Class context: System.Threading.ObjectHeader INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.ObjectHeader:Release(System.Object)' calling 'System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00012 ( 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000037] I-C-G------ * CALL int System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte (exactContextHandle=0x00000000004206E1) [000035] ----------- arg0 +--* LCL_VAR int V05 tmp4 [000036] ----------- arg1 \--* LCL_ADDR byref V06 tmp5 [+0] [ 1] 120 (0x078) brtrue.s STMT00013 ( 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000038] --C-------- +--* RET_EXPR int (for [000037]) [000039] ----------- \--* CNS_INT int 0 impImportBlockPending for BB10 impImportBlockPending for BB11 Importing BB11 (PC=128) of 'System.Threading.ObjectHeader:Release(System.Object)' [ 0] 128 (0x080) ldloc.s 5 [ 1] 130 (0x082) call 06003772 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 CheckCanInline: fetching method info for inline candidate GetLockObject -- context 00000000004207B9 Class context: System.Threading.SyncTable INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.ObjectHeader:Release(System.Object)' calling 'System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00014 ( 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000043] I-C-G------ * CALL ref System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock (exactContextHandle=0x00000000004207B9) [000042] ----------- arg0 \--* LCL_VAR int V06 tmp5 [ 1] 135 (0x087) stloc.1 lvaGrabTemp returning 7 (V07 tmp6) (a long lifetime temp) called for Inline stloc first use temp. Marked V07 as a single def temp lvaSetClass: setting class for V07 to (0000000000420708) System.Threading.Lock [exact] .... checking for GDV of IEnumerable... Named Intrinsic System.Threading.SyncTable.GetLockObject: Not recognized STMT00015 ( 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000044] --C-------- \--* RET_EXPR ref (for [000043]) [ 0] 136 (0x088) ldc.i4.0 0 [ 1] 137 (0x089) conv.u Folding long operator with constant nodes into a constant: [000047] ---------U- * CAST long <- ulong <- uint [000046] ----------- \--* CNS_INT int 0 Bashed to long constant: [000047] ----------- * CNS_INT long 0 [ 1] 138 (0x08a) stloc.2 STMT00016 ( 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 [ 0] 139 (0x08b) ldloc.1 [ 1] 140 (0x08c) ldloc.0 [ 2] 141 (0x08d) callvirt 060036E2 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is void, structSize is 0 CheckCanInline: fetching method info for inline candidate Exit -- context 0000000000420709 Class context: System.Threading.Lock INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.ObjectHeader:Release(System.Object)' calling 'System.Threading.Lock:Exit(int):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00017 ( 0x08B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000051] I-C-G------ * CALL nullcheck void System.Threading.Lock:Exit(int):this (exactContextHandle=0x0000000000420709) [000049] ----------- this +--* LCL_VAR ref V07 tmp6 [000050] ----------- arg1 \--* LCL_VAR int V02 tmp1 [ 0] 146 (0x092) ret Importing BB10 (PC=122) of 'System.Threading.ObjectHeader:Release(System.Object)' [ 0] 122 (0x07a) newobj lvaGrabTemp returning 8 (V08 tmp7) called for NewObj constructor temp. Named Intrinsic System.Threading.ObjectHeader.Release: Not recognized STMT00018 ( 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DA--------- * STORE_LCL_VAR ref V08 tmp7 [000053] ----------- \--* ALLOCOBJ ref [000052] H---------- \--* CNS_INT(h) long 0x420818 class Marked V08 as a single def local lvaSetClass: setting class for V08 to (0000000000420800) System.Threading.SynchronizationLockException [exact] 060039AE In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 CheckCanInline: fetching method info for inline candidate .ctor -- context 0000000000420801 Class context: System.Threading.SynchronizationLockException INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Threading.ObjectHeader:Release(System.Object)' calling 'System.Threading.SynchronizationLockException:.ctor():this' INLINER: Marking System.Threading.SynchronizationLockException:.ctor():this as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' STMT00019 ( ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 [ 1] 127 (0x07f) throw STMT00020 ( 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 Importing BB03 (PC=056) of 'System.Threading.ObjectHeader:Release(System.Object)' [ 0] 56 (0x038) ldloc.s 4 [ 1] 58 (0x03a) ldc.i4 134217728 [ 2] 63 (0x03f) and [ 1] 64 (0x040) brtrue.s STMT00021 ( 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 impImportBlockPending for BB04 impImportBlockPending for BB09 Importing BB04 (PC=066) of 'System.Threading.ObjectHeader:Release(System.Object)' [ 0] 66 (0x042) ldloc.s 4 [ 1] 68 (0x044) ldc.i4 4128768 [ 2] 73 (0x049) and [ 1] 74 (0x04a) brtrue.s STMT00022 ( 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 impImportBlockPending for BB05 impImportBlockPending for BB06 Importing BB06 (PC=086) of 'System.Threading.ObjectHeader:Release(System.Object)' [ 0] 86 (0x056) ldloc.s 4 [ 1] 88 (0x058) ldc.i4 65536 [ 2] 93 (0x05d) sub *************** In impGetSpillTmpBase(BB06) lvaGrabTemps(1) returning 9..9 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00023 ( 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 impImportBlockPending for BB07 Importing BB07 (PC=094) of 'System.Threading.ObjectHeader:Release(System.Object)' [ 1] 94 (0x05e) stloc.s 6 lvaGrabTemp returning 10 (V10 tmp9) (a long lifetime temp) called for Inline stloc first use temp. Marked V10 as a single def temp STMT00024 ( ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 [ 0] 96 (0x060) ldloc.3 [ 1] 97 (0x061) ldloc.s 6 [ 2] 99 (0x063) ldloc.s 4 [ 3] 101 (0x065) call 06003712 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Named Intrinsic System.Threading.Interlocked.CompareExchange: Recognized [ 1] 106 (0x06a) ldloc.s 4 [ 2] 108 (0x06c) bne.un.s STMT00025 ( 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000079] ----------- | +--* LCL_VAR int V10 tmp9 [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 impImportBlockPending for BB08 impImportBlockPending for BB02 Importing BB08 (PC=110) of 'System.Threading.ObjectHeader:Release(System.Object)' [ 0] 110 (0x06e) ret Importing BB05 (PC=076) of 'System.Threading.ObjectHeader:Release(System.Object)' [ 0] 76 (0x04c) ldloc.s 4 [ 1] 78 (0x04e) ldc.i4 -65536 [ 2] 83 (0x053) and [ 1] 84 (0x054) br.s Spilling stack entries into temps STMT00026 ( 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 impImportBlockPending for BB07 ** Note: inlinee IL was partially imported -- imported 146 of 147 bytes of method IL *************** Inline @[000001] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [000..029)-> BB02(1) (always) i BB02 [0002] 2 BB01,BB07 1 [029..038)-> BB09(0.5),BB03(0.5) ( cond ) i bwd bwd-target BB03 [0003] 1 BB02 1 [038..042)-> BB09(0.5),BB04(0.5) ( cond ) i bwd BB04 [0004] 1 BB03 1 [042..04C)-> BB06(0.5),BB05(0.5) ( cond ) i bwd BB05 [0005] 1 BB04 1 [04C..056)-> BB07(1) (always) i bwd BB06 [0006] 1 BB04 1 [056..05E)-> BB07(1) (always) i bwd BB07 [0007] 2 BB05,BB06 1 [05E..06E)-> BB02(0.5),BB08(0.5) ( cond ) i bwd bwd-src BB08 [0008] 1 BB07 1 [06E..06F) (return) i BB09 [0009] 2 BB02,BB03 1 [06F..07A)-> BB11(1),BB10(0) ( cond ) i BB10 [0010] 1 BB09 0 [07A..080) (throw ) i rare newobj BB11 [0011] 1 BB09 1 [080..093) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0001] [000..029) -> BB02(1) (always), preds={} succs={BB02} ***** BB01 [0001] STMT00002 ( 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-] [000004] I-C-G------ * CALL void System.ArgumentNullException:ThrowIfNull(System.Object,System.String) (exactContextHandle=0x0000000000420629) [000000] ----------- arg0 +--* LCL_VAR ref V00 arg0 [000003] ----------- arg1 \--* CNS_STR ref ***** BB01 [0001] STMT00003 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000005] I-C-G------ * CALL int System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int (exactContextHandle=0x0000000000420721) ***** BB01 [0001] STMT00004 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000006] --C-------- \--* RET_EXPR int (for [000005]) ***** BB01 [0001] STMT00005 ( 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 ***** BB01 [0001] STMT00006 ( 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000017] I-C-G------ * CALL byref System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref (exactContextHandle=0x0000000000420301) [000016] ----------- arg0 \--* LCL_VAR ref V00 arg0 ***** BB01 [0001] STMT00007 ( 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000018] --C-------- \--* RET_EXPR byref (for [000017]) ***** BB01 [0001] STMT00008 ( 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000022] I-C-G------ * CALL long System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong (exactContextHandle=0x00000000004206E1) [000021] ---------U- arg0 \--* CAST long <- ulong <- byref [000020] ----------- \--* LCL_VAR byref V03 tmp2 ***** BB01 [0001] STMT00009 ( 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000023] --C-------- \--* RET_EXPR long (for [000022]) ------------ BB02 [0002] [029..038) -> BB09(0.5),BB03(0.5) (cond), preds={BB01,BB07} succs={BB03,BB09} ***** BB02 [0002] STMT00010 ( 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 ***** BB02 [0002] STMT00011 ( 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB03 [0003] [038..042) -> BB09(0.5),BB04(0.5) (cond), preds={BB02} succs={BB04,BB09} ***** BB03 [0003] STMT00021 ( 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 ------------ BB04 [0004] [042..04C) -> BB06(0.5),BB05(0.5) (cond), preds={BB03} succs={BB05,BB06} ***** BB04 [0004] STMT00022 ( 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 ------------ BB05 [0005] [04C..056) -> BB07(1) (always), preds={BB04} succs={BB07} ***** BB05 [0005] STMT00026 ( 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 ------------ BB06 [0006] [056..05E) -> BB07(1) (always), preds={BB04} succs={BB07} ***** BB06 [0006] STMT00023 ( 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 ------------ BB07 [0007] [05E..06E) -> BB02(0.5),BB08(0.5) (cond), preds={BB05,BB06} succs={BB08,BB02} ***** BB07 [0007] STMT00024 ( ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 ***** BB07 [0007] STMT00025 ( 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000079] ----------- | +--* LCL_VAR int V10 tmp9 [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 ------------ BB08 [0008] [06E..06F) (return), preds={BB07} succs={} ------------ BB09 [0009] [06F..07A) -> BB11(1),BB10(0) (cond), preds={BB02,BB03} succs={BB10,BB11} ***** BB09 [0009] STMT00012 ( 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000037] I-C-G------ * CALL int System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte (exactContextHandle=0x00000000004206E1) [000035] ----------- arg0 +--* LCL_VAR int V05 tmp4 [000036] ----------- arg1 \--* LCL_ADDR byref V06 tmp5 [+0] ***** BB09 [0009] STMT00013 ( 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000038] --C-------- +--* RET_EXPR int (for [000037]) [000039] ----------- \--* CNS_INT int 0 ------------ BB10 [0010] [07A..080) (throw), preds={BB09} succs={} ***** BB10 [0010] STMT00018 ( 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DA--------- * STORE_LCL_VAR ref V08 tmp7 [000053] ----------- \--* ALLOCOBJ ref [000052] H---------- \--* CNS_INT(h) long 0x420818 class ***** BB10 [0010] STMT00019 ( ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 ***** BB10 [0010] STMT00020 ( 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 ------------ BB11 [0011] [080..093) (return), preds={BB09} succs={} ***** BB11 [0011] STMT00014 ( 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000043] I-C-G------ * CALL ref System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock (exactContextHandle=0x00000000004207B9) [000042] ----------- arg0 \--* LCL_VAR int V06 tmp5 ***** BB11 [0011] STMT00015 ( 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000044] --C-------- \--* RET_EXPR ref (for [000043]) ***** BB11 [0011] STMT00016 ( 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 ***** BB11 [0011] STMT00017 ( 0x08B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000051] I-C-G------ * CALL nullcheck void System.Threading.Lock:Exit(int):this (exactContextHandle=0x0000000000420709) [000049] ----------- this +--* LCL_VAR ref V07 tmp6 [000050] ----------- arg1 \--* LCL_VAR int V02 tmp1 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000001] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000001] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000001] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000001] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000001] Starting PHASE Post-import *************** Inline @[000001] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000001] ----------- Arguments setup: Inlinee method body: Inserting inlinee blocks New Basic Block BB02 [0012] created. setting likelihood of BB01 -> BB02 to 1 split BB01 after the inlinee call site; after portion is now BB02 Convert bbKind of BB10 to BBJ_ALWAYS to bottom block BB02 setting likelihood of BB10 -> BB02 to 1 Convert bbKind of BB13 to BBJ_ALWAYS to bottom block BB02 setting likelihood of BB13 -> BB02 to 1 fgInlineAppendStatements: nulling out gc ref inlinee locals. STMT00027 ( 0x000[E-] ... ??? ) [000091] DA--------- * STORE_LCL_VAR ref V07 tmp6 [000090] ----------- \--* CNS_INT ref null STMT00028 ( 0x000[E-] ... ??? ) [000093] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000092] ----------- \--* CNS_INT byref 0 --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB03 [0001] 1 BB01 1 [000..001)-> BB04(1) (always) i BB04 [0002] 2 BB03,BB09 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB10(0.5) ( cond ) i bwd bwd-src BB10 [0008] 1 BB09 1 [000..001)-> BB02(1) (always) i BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare newobj BB13 [0011] 1 BB11 1 [000..001)-> BB02(1) (always) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB03 [0001] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0001] STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-] [000004] I-C-G------ * CALL void System.ArgumentNullException:ThrowIfNull(System.Object,System.String) (exactContextHandle=0x0000000000420629) [000000] ----------- arg0 +--* LCL_VAR ref V00 arg0 [000003] ----------- arg1 \--* CNS_STR ref ***** BB03 [0001] STMT00003 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000005] I-C-G------ * CALL int System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int (exactContextHandle=0x0000000000420721) ***** BB03 [0001] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000006] --C-------- \--* RET_EXPR int (for [000005]) ***** BB03 [0001] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 ***** BB03 [0001] STMT00006 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000017] I-C-G------ * CALL byref System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref (exactContextHandle=0x0000000000420301) [000016] ----------- arg0 \--* LCL_VAR ref V00 arg0 ***** BB03 [0001] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000018] --C-------- \--* RET_EXPR byref (for [000017]) ***** BB03 [0001] STMT00008 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000022] I-C-G------ * CALL long System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong (exactContextHandle=0x00000000004206E1) [000021] ---------U- arg0 \--* CAST long <- ulong <- byref [000020] ----------- \--* LCL_VAR byref V03 tmp2 ***** BB03 [0001] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000023] --C-------- \--* RET_EXPR long (for [000022]) ------------ BB04 [0002] [000..001) -> BB11(0.5),BB05(0.5) (cond), preds={BB03,BB09} succs={BB05,BB11} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB11(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB11} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB10(0.5) (cond), preds={BB07,BB08} succs={BB10,BB04} ***** BB09 [0007] STMT00024 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000079] ----------- | +--* LCL_VAR int V10 tmp9 [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0008] [000..001) -> BB02(1) (always), preds={BB09} succs={BB02} ------------ BB11 [0009] [000..001) -> BB13(1),BB12(0) (cond), preds={BB04,BB05} succs={BB12,BB13} ***** BB11 [0009] STMT00012 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000037] I-C-G------ * CALL int System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte (exactContextHandle=0x00000000004206E1) [000035] ----------- arg0 +--* LCL_VAR int V05 tmp4 [000036] ----------- arg1 \--* LCL_ADDR byref V06 tmp5 [+0] ***** BB11 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000038] --C-------- +--* RET_EXPR int (for [000037]) [000039] ----------- \--* CNS_INT int 0 ------------ BB12 [0010] [000..001) (throw), preds={BB11} succs={} ***** BB12 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DA--------- * STORE_LCL_VAR ref V08 tmp7 [000053] ----------- \--* ALLOCOBJ ref [000052] H---------- \--* CNS_INT(h) long 0x420818 class ***** BB12 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 ***** BB12 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 ------------ BB13 [0011] [000..001) -> BB02(1) (always), preds={BB11} succs={BB02} ***** BB13 [0011] STMT00014 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000043] I-C-G------ * CALL ref System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock (exactContextHandle=0x00000000004207B9) [000042] ----------- arg0 \--* LCL_VAR int V06 tmp5 ***** BB13 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000044] --C-------- \--* RET_EXPR ref (for [000043]) ***** BB13 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 ***** BB13 [0011] STMT00017 ( INL01 @ 0x08B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000051] I-C-G------ * CALL nullcheck void System.Threading.Lock:Exit(int):this (exactContextHandle=0x0000000000420709) [000049] ----------- this +--* LCL_VAR ref V07 tmp6 [000050] ----------- arg1 \--* LCL_VAR int V02 tmp1 ------------------------------------------------------------------------------------------------------------------- INLINER: Updating optMethodFlags -- root:0 callee:2 new:2 INLINER: may-throw inlinee Successfully inlined System.Threading.ObjectHeader:Release(System.Object) (147 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- BB01 becomes empty INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.ObjectHeader:Release(System.Object)' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00002 in BB03: STMT00002 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x000[E-] [000004] I-C-G------ * CALL void System.ArgumentNullException:ThrowIfNull(System.Object,System.String) (exactContextHandle=0x0000000000420629) [000000] ----------- arg0 +--* LCL_VAR ref V00 arg0 [000003] ----------- arg1 \--* CNS_STR ref IL argument #0: is a local var [000000] ----------- * LCL_VAR ref V00 arg0 IL argument #1: is a constant or invariant [000003] ----------- * CNS_STR ref INLINER: inlineInfo.tokenLookupContextHandle for System.ArgumentNullException:ThrowIfNull(System.Object,System.String) set to 0x0000000000420629: Invoking compiler for the inlinee method System.ArgumentNullException:ThrowIfNull(System.Object,System.String) : IL to import: IL_0000 02 ldarg.0 IL_0001 2d 06 brtrue.s 6 (IL_0009) IL_0003 03 ldarg.1 IL_0004 28 2f 07 00 06 call 0x600072F IL_0009 2a ret INLINER impTokenLookupContextHandle for System.ArgumentNullException:ThrowIfNull(System.Object,System.String) is 0x0000000000420629. *************** In compInitDebuggingInfo() for System.ArgumentNullException:ThrowIfNull(System.Object,System.String) info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ArgumentNullException:ThrowIfNull(System.Object,System.String) Jump targets: IL_0009 New Basic Block BB01 [0013] created. BB01 [0013] [000..003) New Basic Block BB02 [0014] created. BB02 [0014] [003..009) New Basic Block BB03 [0015] created. BB03 [0015] [009..00A) setting likelihood of BB01 -> BB03 to 0.5 setting likelihood of BB01 -> BB02 to 0.5 setting likelihood of BB02 -> BB03 to 1 Basic block list for 'System.ArgumentNullException:ThrowIfNull(System.Object,System.String)' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0013] 1 1 [000..003)-> BB03(0.5),BB02(0.5) ( cond ) BB02 [0014] 1 BB01 1 [003..009)-> BB03(1) (always) BB03 [0015] 2 BB01,BB02 1 [009..00A) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000004] Starting PHASE Pre-import *************** Inline @[000004] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0013] 1 1 [000..003)-> BB03(0.5),BB02(0.5) ( cond ) BB02 [0014] 1 BB01 1 [003..009)-> BB03(1) (always) BB03 [0015] 2 BB01,BB02 1 [009..00A) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0013] [000..003) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ------------ BB02 [0014] [003..009) -> BB03(1) (always), preds={BB01} succs={BB03} ------------ BB03 [0015] [009..00A) (return), preds={BB01,BB02} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000004] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000004] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0013] 1 1 [000..003)-> BB03(0.5),BB02(0.5) ( cond ) BB02 [0014] 1 BB01 1 [003..009)-> BB03(1) (always) BB03 [0015] 2 BB01,BB02 1 [009..00A) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0013] [000..003) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ------------ BB02 [0014] [003..009) -> BB03(1) (always), preds={BB01} succs={BB03} ------------ BB03 [0015] [009..00A) (return), preds={BB01,BB02} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000004] Starting PHASE Canonicalize entry *************** Inline @[000004] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000004] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.ArgumentNullException:ThrowIfNull(System.Object,System.String)' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) brtrue.s STMT00029 ( 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null impImportBlockPending for BB02 impImportBlockPending for BB03 Importing BB03 (PC=009) of 'System.ArgumentNullException:ThrowIfNull(System.Object,System.String)' [ 0] 9 (0x009) ret Importing BB02 (PC=003) of 'System.ArgumentNullException:ThrowIfNull(System.Object,System.String)' [ 0] 3 (0x003) ldarg.1 [ 1] 4 (0x004) call 0600072F In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 CheckCanInline: fetching method info for inline candidate Throw -- context 0000000000420629 Class context: System.ArgumentNullException INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.ArgumentNullException:ThrowIfNull(System.Object,System.String)' calling 'System.ArgumentNullException:Throw(System.String)' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00030 ( 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] I-C-G------ * CALL void System.ArgumentNullException:Throw(System.String) (exactContextHandle=0x0000000000420629) [000098] ----------- arg0 \--* CNS_STR ref impImportBlockPending for BB03 ** Note: inlinee IL was partially imported -- imported 9 of 10 bytes of method IL *************** Inline @[000004] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0013] 1 1 [000..003)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 1 [003..009)-> BB03(1) (always) i BB03 [0015] 2 BB01,BB02 1 [009..00A) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0013] [000..003) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0013] STMT00029 ( 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null ------------ BB02 [0014] [003..009) -> BB03(1) (always), preds={BB01} succs={BB03} ***** BB02 [0014] STMT00030 ( 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] I-C-G------ * CALL void System.ArgumentNullException:Throw(System.String) (exactContextHandle=0x0000000000420629) [000098] ----------- arg0 \--* CNS_STR ref ------------ BB03 [0015] [009..00A) (return), preds={BB01,BB02} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000004] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000004] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000004] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000004] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000004] Starting PHASE Post-import *************** Inline @[000004] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000004] ----------- Arguments setup: Inlinee method body: Inserting inlinee blocks New Basic Block BB14 [0016] created. BB04 previous predecessor was BB03, now is BB14 setting likelihood of BB14 -> BB04 from 1 to 1 setting likelihood of BB03 -> BB14 to 1 split BB03 after the inlinee call site; after portion is now BB14 Convert bbKind of BB17 to BBJ_ALWAYS to bottom block BB14 setting likelihood of BB17 -> BB14 to 1 fgInlineAppendStatements: no gc ref inline locals. --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB15 [0013] 1 BB03 1 [000..001)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB15 1 [000..001)-> BB17(1) (always) i BB17 [0015] 2 BB15,BB16 1 [000..001)-> BB14(1) (always) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB15 [0013] [000..001) -> BB17(0.5),BB16(0.5) (cond), preds={BB03} succs={BB16,BB17} ***** BB15 [0013] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null ------------ BB16 [0014] [000..001) -> BB17(1) (always), preds={BB15} succs={BB17} ***** BB16 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] I-C-G------ * CALL void System.ArgumentNullException:Throw(System.String) (exactContextHandle=0x0000000000420629) [000098] ----------- arg0 \--* CNS_STR ref ------------ BB17 [0015] [000..001) -> BB14(1) (always), preds={BB15,BB16} succs={BB14} ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.ArgumentNullException:ThrowIfNull(System.Object,System.String) (10 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- BB03 becomes empty INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.ArgumentNullException:ThrowIfNull(System.Object,System.String)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00030 in BB16: STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] I-C-G------ * CALL void System.ArgumentNullException:Throw(System.String) (exactContextHandle=0x0000000000420629) [000098] ----------- arg0 \--* CNS_STR ref IL argument #0: is a constant or invariant [000098] ----------- * CNS_STR ref INLINER: inlineInfo.tokenLookupContextHandle for System.ArgumentNullException:Throw(System.String) set to 0x0000000000420629: Invoking compiler for the inlinee method System.ArgumentNullException:Throw(System.String) : IL to import: IL_0000 02 ldarg.0 IL_0001 73 27 07 00 06 newobj 0x6000727 IL_0006 7a throw INLINER impTokenLookupContextHandle for System.ArgumentNullException:Throw(System.String) is 0x0000000000420629. *************** In compInitDebuggingInfo() for System.ArgumentNullException:Throw(System.String) info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ArgumentNullException:Throw(System.String) Jump targets: none New Basic Block BB01 [0017] created. BB01 [0017] [000..007) Basic block list for 'System.ArgumentNullException:Throw(System.String)' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0017] 1 0 [000..007) (throw ) rare --------------------------------------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.ArgumentNullException:Throw(System.String)' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'does not return' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.ArgumentNullException:Throw(System.String)' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'does not return' Expanding INLINE_CANDIDATE in statement STMT00003 in BB14: STMT00003 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000005] I-C-G------ * CALL int System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int (exactContextHandle=0x0000000000420721) INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int set to 0x0000000000420721: Invoking compiler for the inlinee method System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int : IL to import: IL_0000 7e 19 0b 00 04 ldsfld 0x4000B19 IL_0005 2a ret INLINER impTokenLookupContextHandle for System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int is 0x0000000000420721. *************** In compInitDebuggingInfo() for System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int Jump targets: none New Basic Block BB01 [0017] created. BB01 [0017] [000..006) Basic block list for 'System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0017] 1 1 [000..006) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000005] Starting PHASE Pre-import *************** Inline @[000005] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0017] 1 1 [000..006) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0017] [000..006) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000005] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000005] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0017] 1 1 [000..006) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0017] [000..006) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000005] Starting PHASE Canonicalize entry *************** Inline @[000005] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000005] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int' [ 0] 0 (0x000) ldsfld 04000B19 [ 1] 5 (0x005) ret Inlinee Return expression (before normalization) => [000104] n-C-G------ * IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] Inlinee Return expression (after normalization) => [000104] n-C-G------ * IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ** Note: inlinee IL was partially imported -- imported 0 of 6 bytes of method IL *************** Inline @[000005] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0017] 1 1 [000..006) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0017] [000..006) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000005] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000005] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000005] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000005] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000005] Starting PHASE Post-import *************** Inline @[000005] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000005] ----------- Inlinee method body: inlinee was empty fgInlineAppendStatements: no gc ref inline locals. INLINER: Updating optMethodFlags -- root:2 callee:10000 new:10002 Successfully inlined System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int (6 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000006] with [000104] [000006] --C-------- * RET_EXPR int (for [000005]) -> [000104] Inserting the inline return expression [000104] n-C-G------ * IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' for 'System.Threading.Monitor:Exit(System.Object)' calling 'n/a' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' Expanding INLINE_CANDIDATE in statement STMT00006 in BB14: STMT00006 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000017] I-C-G------ * CALL byref System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref (exactContextHandle=0x0000000000420301) [000016] ----------- arg0 \--* LCL_VAR ref V00 arg0 IL argument #0: is a local var [000016] ----------- * LCL_VAR ref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref set to 0x0000000000420301: Invoking compiler for the inlinee method System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref : IL to import: IL_0000 02 ldarg.0 IL_0001 7c bd 00 00 04 ldflda 0x40000BD IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref is 0x0000000000420301. *************** In compInitDebuggingInfo() for System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref Jump targets: none New Basic Block BB01 [0018] created. BB01 [0018] [000..007) Basic block list for 'System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0018] 1 1 [000..007) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000017] Starting PHASE Pre-import *************** Inline @[000017] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0018] 1 1 [000..007) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0018] [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000017] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000017] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0018] 1 1 [000..007) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0018] [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000017] Starting PHASE Canonicalize entry *************** Inline @[000017] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000017] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldflda 040000BD [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [000106] ---X------- * FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 Inlinee Return expression (after normalization) => [000106] ---X------- * FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000017] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0018] 1 1 [000..007) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0018] [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000017] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000017] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000017] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000017] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000017] Starting PHASE Post-import *************** Inline @[000017] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000017] ----------- Arguments setup: Inlinee method body: inlinee was empty fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000018] with [000106] [000018] --C-------- * RET_EXPR byref (for [000017]) -> [000106] Inserting the inline return expression [000106] ---X------- * FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 Expanding INLINE_CANDIDATE in statement STMT00008 in BB14: STMT00008 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000022] I-C-G------ * CALL long System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong (exactContextHandle=0x00000000004206E1) [000021] ---------U- arg0 \--* CAST long <- ulong <- byref [000020] ----------- \--* LCL_VAR byref V03 tmp2 IL argument #0: [000021] ---------U- * CAST long <- ulong <- byref [000020] ----------- \--* LCL_VAR byref V03 tmp2 INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong set to 0x00000000004206E1: Invoking compiler for the inlinee method System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong : IL to import: IL_0000 02 ldarg.0 IL_0001 1a ldc.i4.4 IL_0002 59 sub IL_0003 2a ret INLINER impTokenLookupContextHandle for System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong is 0x00000000004206E1. *************** In compInitDebuggingInfo() for System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong Jump targets: none New Basic Block BB01 [0019] created. BB01 [0019] [000..004) Basic block list for 'System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0019] 1 1 [000..004) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000022] Starting PHASE Pre-import *************** Inline @[000022] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0019] 1 1 [000..004) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0019] [000..004) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000022] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000022] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0019] 1 1 [000..004) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0019] [000..004) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000022] Starting PHASE Canonicalize entry *************** Inline @[000022] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000022] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 11 (V11 tmp10) called for Inlining Arg. Marked V11 as a single def temp [ 1] 1 (0x001) ldc.i4.4 4 [ 2] 2 (0x002) sub Folding long operator with constant nodes into a constant: [000110] ----------- * CAST long <- int [000109] ----------- \--* CNS_INT int 4 Bashed to long constant: [000110] ----------- * CNS_INT long 4 [ 1] 3 (0x003) ret Inlinee Return expression (before normalization) => [000111] ----------- * SUB long [000108] ----------- +--* LCL_VAR long V11 tmp10 [000110] ----------- \--* CNS_INT long 4 Inlinee Return expression (after normalization) => [000111] ----------- * SUB long [000108] ----------- +--* LCL_VAR long V11 tmp10 [000110] ----------- \--* CNS_INT long 4 ** Note: inlinee IL was partially imported -- imported 0 of 4 bytes of method IL *************** Inline @[000022] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0019] 1 1 [000..004) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0019] [000..004) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000022] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000022] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000022] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000022] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000022] Starting PHASE Post-import *************** Inline @[000022] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000022] ----------- Arguments setup: Inlinee method body: inlinee was empty fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong (4 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Replacing the return expression placeholder [000023] with [000111] [000023] --C-------- * RET_EXPR long (for [000022]) -> [000111] Inserting the inline return expression [000111] ----------- * SUB long [000021] ---------U- +--* CAST long <- ulong <- byref [000020] ----------- | \--* LCL_VAR byref V03 tmp2 [000110] ----------- \--* CNS_INT long 4 Expanding INLINE_CANDIDATE in statement STMT00012 in BB11: STMT00012 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000037] I-C-G------ * CALL int System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte (exactContextHandle=0x00000000004206E1) [000035] ----------- arg0 +--* LCL_VAR int V05 tmp4 [000036] ----------- arg1 \--* LCL_ADDR byref V06 tmp5 [+0] IL argument #0: is a local var [000035] ----------- * LCL_VAR int V05 tmp4 IL argument #1: is a constant or invariant [000036] ----------- * LCL_ADDR byref V06 tmp5 [+0] INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte set to 0x00000000004206E1: Invoking compiler for the inlinee method System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte : IL to import: IL_0000 03 ldarg.1 IL_0001 02 ldarg.0 IL_0002 20 ff ff ff 03 ldc.i4 0x3FFFFFF IL_0007 5f and IL_0008 54 stind.i4 IL_0009 02 ldarg.0 IL_000a 28 60 37 00 06 call 0x6003760 IL_000f 2a ret INLINER impTokenLookupContextHandle for System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte is 0x00000000004206E1. *************** In compInitDebuggingInfo() for System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte Jump targets: none New Basic Block BB01 [0020] created. BB01 [0020] [000..010) Basic block list for 'System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0020] 1 1 [000..010) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000037] Starting PHASE Pre-import *************** Inline @[000037] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0020] 1 1 [000..010) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0020] [000..010) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000037] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000037] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0020] 1 1 [000..010) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0020] [000..010) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000037] Starting PHASE Canonicalize entry *************** Inline @[000037] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000037] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte' [ 0] 0 (0x000) ldarg.1 [ 1] 1 (0x001) ldarg.0 [ 2] 2 (0x002) ldc.i4 67108863 [ 3] 7 (0x007) and [ 2] 8 (0x008) stind.i4 STMT00031 ( 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] nA--G------ * STOREIND int [000113] ----------- +--* LCL_ADDR long V06 tmp5 [+0] [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF [ 0] 9 (0x009) ldarg.0 [ 1] 10 (0x00a) call 06003760 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ubyte, structSize is 0 CheckCanInline: fetching method info for inline candidate HasSyncEntryIndex -- context 00000000004206E1 Class context: System.Threading.ObjectHeader INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte' calling 'System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00032 ( 0x009[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000118] I-C-G------ * CALL int System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte (exactContextHandle=0x00000000004206E1) [000117] ----------- arg0 \--* LCL_VAR int V05 tmp4 [ 1] 15 (0x00f) ret Inlinee Return expression (before normalization) => [000119] --C-------- * RET_EXPR int (for [000118]) Inlinee Return expression (after normalization) => [000119] --C-------- * RET_EXPR int (for [000118]) *************** Inline @[000037] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0020] 1 1 [000..010) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0020] [000..010) (return), preds={} succs={} ***** BB01 [0020] STMT00031 ( 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] nA--G------ * STOREIND int [000113] ----------- +--* LCL_ADDR long V06 tmp5 [+0] [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF ***** BB01 [0020] STMT00032 ( 0x009[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000118] I-C-G------ * CALL int System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte (exactContextHandle=0x00000000004206E1) [000117] ----------- arg0 \--* LCL_VAR int V05 tmp4 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000037] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000037] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000037] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000037] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000037] Starting PHASE Post-import *************** Inline @[000037] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000037] ----------- Arguments setup: Inlinee method body: Inserting inlinee code into BB11 STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] nA--G------ * STOREIND int [000113] ----------- +--* LCL_ADDR long V06 tmp5 [+0] [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF STMT00032 ( INL06 @ 0x009[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000118] I-C-G------ * CALL int System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte (exactContextHandle=0x00000000004206E1) [000117] ----------- arg0 \--* LCL_VAR int V05 tmp4 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte (16 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00032 in BB11: STMT00032 ( INL06 @ 0x009[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000118] I-C-G------ * CALL int System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte (exactContextHandle=0x00000000004206E1) [000117] ----------- arg0 \--* LCL_VAR int V05 tmp4 IL argument #0: is a local var [000117] ----------- * LCL_VAR int V05 tmp4 INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte set to 0x00000000004206E1: Invoking compiler for the inlinee method System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte : IL to import: IL_0000 02 ldarg.0 IL_0001 20 00 00 00 0c ldc.i4 0xC000000 IL_0006 5f and IL_0007 20 00 00 00 08 ldc.i4 0x8000000 IL_000c fe 01 ceq IL_000e 2a ret INLINER impTokenLookupContextHandle for System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte is 0x00000000004206E1. *************** In compInitDebuggingInfo() for System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte Jump targets: none New Basic Block BB01 [0021] created. BB01 [0021] [000..00F) Basic block list for 'System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0021] 1 1 [000..00F) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000118] Starting PHASE Pre-import *************** Inline @[000118] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0021] 1 1 [000..00F) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0021] [000..00F) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000118] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000118] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0021] 1 1 [000..00F) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0021] [000..00F) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000118] Starting PHASE Canonicalize entry *************** Inline @[000118] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000118] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldc.i4 201326592 [ 2] 6 (0x006) and [ 1] 7 (0x007) ldc.i4 134217728 [ 2] 12 (0x00c) ceq [ 1] 14 (0x00e) ret Inlinee Return expression (before normalization) => [000124] ----------- * EQ int [000122] ----------- +--* AND int [000117] ----------- | +--* LCL_VAR int V05 tmp4 [000121] ----------- | \--* CNS_INT int 0xC000000 [000123] ----------- \--* CNS_INT int 0x8000000 Inlinee Return expression (after normalization) => [000124] ----------- * EQ int [000122] ----------- +--* AND int [000117] ----------- | +--* LCL_VAR int V05 tmp4 [000121] ----------- | \--* CNS_INT int 0xC000000 [000123] ----------- \--* CNS_INT int 0x8000000 ** Note: inlinee IL was partially imported -- imported 0 of 15 bytes of method IL *************** Inline @[000118] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0021] 1 1 [000..00F) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0021] [000..00F) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000118] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000118] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000118] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000118] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000118] Starting PHASE Post-import *************** Inline @[000118] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000118] ----------- Arguments setup: Inlinee method body: inlinee was empty fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte (15 IL bytes) (depth 3) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Replacing the return expression placeholder [000038] with [000124] [000038] --C-------- * RET_EXPR int (for [000037]) -> [000119] Inserting the inline return expression [000124] ----------- * EQ int [000122] ----------- +--* AND int [000117] ----------- | +--* LCL_VAR int V05 tmp4 [000121] ----------- | \--* CNS_INT int 0xC000000 [000123] ----------- \--* CNS_INT int 0x8000000 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.SynchronizationLockException:.ctor():this' INLINER: Marking System.Threading.SynchronizationLockException:.ctor():this as NOINLINE because of too many il bytes INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' for 'System.Threading.Monitor:Exit(System.Object)' calling 'n/a' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' Expanding INLINE_CANDIDATE in statement STMT00014 in BB13: STMT00014 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000043] I-C-G------ * CALL ref System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock (exactContextHandle=0x00000000004207B9) [000042] ----------- arg0 \--* LCL_VAR int V06 tmp5 IL argument #0: is a local var has caller local ref [000042] ----------- * LCL_VAR int V06 tmp5 INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock set to 0x00000000004207B9: Invoking compiler for the inlinee method System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock : IL to import: IL_0000 02 ldarg.0 IL_0001 28 6a 37 00 06 call 0x600376A IL_0006 7b 33 25 00 04 ldfld 0x4002533 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock is 0x00000000004207B9. *************** In compInitDebuggingInfo() for System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock Jump targets: none New Basic Block BB01 [0022] created. BB01 [0022] [000..00C) Basic block list for 'System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0022] 1 1 [000..00C) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000043] Starting PHASE Pre-import *************** Inline @[000043] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0022] 1 1 [000..00C) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0022] [000..00C) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000043] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000043] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0022] 1 1 [000..00C) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0022] [000..00C) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000043] Starting PHASE Canonicalize entry *************** Inline @[000043] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000043] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 12 (V12 tmp11) called for Inlining Arg. Marked V12 as a single def temp [ 1] 1 (0x001) call 0600376A In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 CheckCanInline: fetching method info for inline candidate UnsafeEntryRef -- context 00000000004207B9 Class context: System.Threading.SyncTable INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock' calling 'System.Threading.SyncTable:UnsafeEntryRef(int):byref' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00033 ( 0x000[E-] ... ??? ) <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000127] I-C-G------ * CALL byref System.Threading.SyncTable:UnsafeEntryRef(int):byref (exactContextHandle=0x00000000004207B9) [000126] ----------- arg0 \--* LCL_VAR int V12 tmp11 [ 1] 6 (0x006) ldfld 04002533 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000130] n-CXG------ * IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000128] --C-------- \--* RET_EXPR byref (for [000127]) Inlinee Return expression (after normalization) => [000130] n-CXG------ * IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000128] --C-------- \--* RET_EXPR byref (for [000127]) *************** Inline @[000043] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0022] 1 1 [000..00C) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0022] [000..00C) (return), preds={} succs={} ***** BB01 [0022] STMT00033 ( 0x000[E-] ... ??? ) <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000127] I-C-G------ * CALL byref System.Threading.SyncTable:UnsafeEntryRef(int):byref (exactContextHandle=0x00000000004207B9) [000126] ----------- arg0 \--* LCL_VAR int V12 tmp11 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000043] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000043] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000043] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000043] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000043] Starting PHASE Post-import *************** Inline @[000043] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000043] ----------- Arguments setup: STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA--------- * STORE_LCL_VAR int V12 tmp11 [000042] ----------- \--* LCL_VAR int V06 tmp5 Inlinee method body: Inserting inlinee code into BB13 STMT00033 ( INL08 @ 0x000[E-] ... ??? ) <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000127] I-C-G------ * CALL byref System.Threading.SyncTable:UnsafeEntryRef(int):byref (exactContextHandle=0x00000000004207B9) [000126] ----------- arg0 \--* LCL_VAR int V12 tmp11 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00033 in BB13: STMT00033 ( INL08 @ 0x000[E-] ... ??? ) <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000127] I-C-G------ * CALL byref System.Threading.SyncTable:UnsafeEntryRef(int):byref (exactContextHandle=0x00000000004207B9) [000126] ----------- arg0 \--* LCL_VAR int V12 tmp11 IL argument #0: is a local var [000126] ----------- * LCL_VAR int V12 tmp11 INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.SyncTable:UnsafeEntryRef(int):byref set to 0x00000000004207B9: Invoking compiler for the inlinee method System.Threading.SyncTable:UnsafeEntryRef(int):byref : IL to import: IL_0000 7e 3e 0b 00 04 ldsfld 0x4000B3E IL_0005 28 70 09 00 2b call 0x2B000970 IL_000a 02 ldarg.0 IL_000b 28 71 09 00 2b call 0x2B000971 IL_0010 2a ret INLINER impTokenLookupContextHandle for System.Threading.SyncTable:UnsafeEntryRef(int):byref is 0x00000000004207B9. *************** In compInitDebuggingInfo() for System.Threading.SyncTable:UnsafeEntryRef(int):byref info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.SyncTable:UnsafeEntryRef(int):byref Jump targets: none New Basic Block BB01 [0023] created. BB01 [0023] [000..011) Basic block list for 'System.Threading.SyncTable:UnsafeEntryRef(int):byref' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0023] 1 1 [000..011) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000127] Starting PHASE Pre-import *************** Inline @[000127] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0023] 1 1 [000..011) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0023] [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000127] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000127] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0023] 1 1 [000..011) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0023] [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000127] Starting PHASE Canonicalize entry *************** Inline @[000127] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000127] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.SyncTable:UnsafeEntryRef(int):byref' [ 0] 0 (0x000) ldsfld 04000B3E [ 1] 5 (0x005) call 2B000970 In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Runtime.InteropServices.MemoryMarshal.GetArrayDataReference: Recognized lvaGrabTemp returning 13 (V13 tmp12) called for MemoryMarshal.GetArrayDataReference array. STMT00035 ( 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] STMT00036 ( ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 [ 1] 10 (0x00a) ldarg.0 [ 2] 11 (0x00b) call 2B000971 In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Runtime.CompilerServices.Unsafe.Add: Recognized [ 1] 16 (0x010) ret Inlinee Return expression (before normalization) => [000147] ---XG------ * ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 [000145] ----------- \--* CNS_INT long 32 Inlinee Return expression (after normalization) => [000147] ---XG------ * ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 [000145] ----------- \--* CNS_INT long 32 *************** Inline @[000127] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0023] 1 1 [000..011) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0023] [000..011) (return), preds={} succs={} ***** BB01 [0023] STMT00035 ( 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] ***** BB01 [0023] STMT00036 ( ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000127] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000127] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000127] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000127] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000127] Starting PHASE Post-import *************** Inline @[000127] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000127] ----------- Arguments setup: Inlinee method body: Inserting inlinee code into BB13 STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 fgInlineAppendStatements: no gc ref inline locals. INLINER: Updating optMethodFlags -- root:10002 callee:8 new:1000a Successfully inlined System.Threading.SyncTable:UnsafeEntryRef(int):byref (17 IL bytes) (depth 3) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.SyncTable:UnsafeEntryRef(int):byref' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Replacing the return expression placeholder [000044] with [000130] [000044] --C-------- * RET_EXPR ref (for [000043]) -> [000130] Inserting the inline return expression [000130] n-CXG------ * IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000128] --C-------- \--* RET_EXPR byref (for [000127]) -> [000147] Replacing the return expression placeholder [000128] with [000147] [000128] --C-------- * RET_EXPR byref (for [000127]) -> [000147] Inserting the inline return expression [000147] ---XG------ * ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 [000145] ----------- \--* CNS_INT long 32 Querying runtime about current class of field System.Threading.SyncTable+Entry:Lock (declared as System.Threading.Lock) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00017 in BB13: STMT00017 ( INL01 @ 0x08B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000051] I-C-G------ * CALL nullcheck void System.Threading.Lock:Exit(int):this (exactContextHandle=0x0000000000420709) [000049] ----------- this +--* LCL_VAR ref V07 tmp6 [000050] ----------- arg1 \--* LCL_VAR int V02 tmp1 ThisPointer: is a local var [000049] ----------- * LCL_VAR ref V07 tmp6 IL argument #1: is a local var [000050] ----------- * LCL_VAR int V02 tmp1 INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.Lock:Exit(int):this set to 0x0000000000420709: Invoking compiler for the inlinee method System.Threading.Lock:Exit(int):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 26 0b 00 04 ldfld 0x4000B26 IL_0006 03 ldarg.1 IL_0007 2e 05 beq.s 5 (IL_000e) IL_0009 28 09 20 00 06 call 0x6002009 IL_000e 02 ldarg.0 IL_000f 28 f6 36 00 06 call 0x60036F6 IL_0014 2a ret INLINER impTokenLookupContextHandle for System.Threading.Lock:Exit(int):this is 0x0000000000420709. *************** In compInitDebuggingInfo() for System.Threading.Lock:Exit(int):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.Lock:Exit(int):this Jump targets: IL_000e New Basic Block BB01 [0024] created. BB01 [0024] [000..009) New Basic Block BB02 [0025] created. BB02 [0025] [009..00E) New Basic Block BB03 [0026] created. BB03 [0026] [00E..015) setting likelihood of BB01 -> BB03 to 0.5 setting likelihood of BB01 -> BB02 to 0.5 setting likelihood of BB02 -> BB03 to 1 Basic block list for 'System.Threading.Lock:Exit(int):this' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0024] 1 1 [000..009)-> BB03(0.5),BB02(0.5) ( cond ) BB02 [0025] 1 BB01 1 [009..00E)-> BB03(1) (always) BB03 [0026] 2 BB01,BB02 1 [00E..015) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000051] Starting PHASE Pre-import *************** Inline @[000051] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0024] 1 1 [000..009)-> BB03(0.5),BB02(0.5) ( cond ) BB02 [0025] 1 BB01 1 [009..00E)-> BB03(1) (always) BB03 [0026] 2 BB01,BB02 1 [00E..015) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0024] [000..009) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ------------ BB02 [0025] [009..00E) -> BB03(1) (always), preds={BB01} succs={BB03} ------------ BB03 [0026] [00E..015) (return), preds={BB01,BB02} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000051] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000051] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0024] 1 1 [000..009)-> BB03(0.5),BB02(0.5) ( cond ) BB02 [0025] 1 BB01 1 [009..00E)-> BB03(1) (always) BB03 [0026] 2 BB01,BB02 1 [00E..015) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0024] [000..009) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ------------ BB02 [0025] [009..00E) -> BB03(1) (always), preds={BB01} succs={BB03} ------------ BB03 [0026] [00E..015) (return), preds={BB01,BB02} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000051] Starting PHASE Canonicalize entry *************** Inline @[000051] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000051] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.Lock:Exit(int):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000B26 [ 1] 6 (0x006) ldarg.1 [ 2] 7 (0x007) beq.s STMT00037 ( 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 impImportBlockPending for BB02 impImportBlockPending for BB03 Importing BB03 (PC=014) of 'System.Threading.Lock:Exit(int):this' [ 0] 14 (0x00e) ldarg.0 [ 1] 15 (0x00f) call 060036F6 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 CheckCanInline: fetching method info for inline candidate ExitImpl -- context 0000000000420709 Class context: System.Threading.Lock INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.Lock:Exit(int):this' calling 'System.Threading.Lock:ExitImpl():this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00038 ( 0x00E[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000154] I-C-G------ * CALL void System.Threading.Lock:ExitImpl():this (exactContextHandle=0x0000000000420709) [000153] ----------- this \--* LCL_VAR ref V07 tmp6 [ 0] 20 (0x014) ret Importing BB02 (PC=009) of 'System.Threading.Lock:Exit(int):this' [ 0] 9 (0x009) call 06002009 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 CheckCanInline: fetching method info for inline candidate ThrowSynchronizationLockException_LockExit -- context 0000000000420951 Class context: System.ThrowHelper INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.Lock:Exit(int):this' calling 'System.ThrowHelper:ThrowSynchronizationLockException_LockExit()' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00039 ( 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] I-C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() (exactContextHandle=0x0000000000420951) impImportBlockPending for BB03 *************** Inline @[000051] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0024] 1 1 [000..009)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0025] 1 BB01 1 [009..00E)-> BB03(1) (always) i BB03 [0026] 2 BB01,BB02 1 [00E..015) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0024] [000..009) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0024] STMT00037 ( 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB02 [0025] [009..00E) -> BB03(1) (always), preds={BB01} succs={BB03} ***** BB02 [0025] STMT00039 ( 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] I-C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() (exactContextHandle=0x0000000000420951) ------------ BB03 [0026] [00E..015) (return), preds={BB01,BB02} succs={} ***** BB03 [0026] STMT00038 ( 0x00E[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000154] I-C-G------ * CALL void System.Threading.Lock:ExitImpl():this (exactContextHandle=0x0000000000420709) [000153] ----------- this \--* LCL_VAR ref V07 tmp6 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000051] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000051] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000051] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000051] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000051] Starting PHASE Post-import *************** Inline @[000051] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000051] ----------- Arguments setup: Inlinee method body: Inserting inlinee blocks New Basic Block BB18 [0027] created. BB02 previous predecessor was BB13, now is BB18 setting likelihood of BB18 -> BB02 from 1 to 1 setting likelihood of BB13 -> BB18 to 1 split BB13 after the inlinee call site; after portion is now BB18 Convert bbKind of BB21 to BBJ_ALWAYS to bottom block BB18 setting likelihood of BB21 -> BB18 to 1 fgInlineAppendStatements: no gc ref inline locals. --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB19 [0024] 1 BB13 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i BB20 [0025] 1 BB19 1 [000..001)-> BB21(1) (always) i BB21 [0026] 2 BB19,BB20 1 [000..001)-> BB18(1) (always) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB19 [0024] [000..001) -> BB21(0.5),BB20(0.5) (cond), preds={BB13} succs={BB20,BB21} ***** BB19 [0024] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB20 [0025] [000..001) -> BB21(1) (always), preds={BB19} succs={BB21} ***** BB20 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] I-C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() (exactContextHandle=0x0000000000420951) ------------ BB21 [0026] [000..001) -> BB18(1) (always), preds={BB19,BB20} succs={BB18} ***** BB21 [0026] STMT00038 ( INL10 @ 0x00E[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000154] I-C-G------ * CALL void System.Threading.Lock:ExitImpl():this (exactContextHandle=0x0000000000420709) [000153] ----------- this \--* LCL_VAR ref V07 tmp6 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Threading.Lock:Exit(int):this (21 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.Lock:Exit(int):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00039 in BB20: STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] I-C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() (exactContextHandle=0x0000000000420951) INLINER: inlineInfo.tokenLookupContextHandle for System.ThrowHelper:ThrowSynchronizationLockException_LockExit() set to 0x0000000000420951: Invoking compiler for the inlinee method System.ThrowHelper:ThrowSynchronizationLockException_LockExit() : IL to import: IL_0000 72 30 3c 02 70 ldstr 0x70023C30 IL_0005 73 af 39 00 06 newobj 0x60039AF IL_000a 7a throw INLINER impTokenLookupContextHandle for System.ThrowHelper:ThrowSynchronizationLockException_LockExit() is 0x0000000000420951. *************** In compInitDebuggingInfo() for System.ThrowHelper:ThrowSynchronizationLockException_LockExit() info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ThrowHelper:ThrowSynchronizationLockException_LockExit() Jump targets: none New Basic Block BB01 [0028] created. BB01 [0028] [000..00B) Basic block list for 'System.ThrowHelper:ThrowSynchronizationLockException_LockExit()' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0028] 1 0 [000..00B) (throw ) rare --------------------------------------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.ThrowHelper:ThrowSynchronizationLockException_LockExit()' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'does not return' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.ThrowHelper:ThrowSynchronizationLockException_LockExit()' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'does not return' Expanding INLINE_CANDIDATE in statement STMT00038 in BB21: STMT00038 ( INL10 @ 0x00E[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000154] I-C-G------ * CALL void System.Threading.Lock:ExitImpl():this (exactContextHandle=0x0000000000420709) [000153] ----------- this \--* LCL_VAR ref V07 tmp6 ThisPointer: is a local var [000153] ----------- * LCL_VAR ref V07 tmp6 INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.Lock:ExitImpl():this set to 0x0000000000420709: Invoking compiler for the inlinee method System.Threading.Lock:ExitImpl():this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 28 0b 00 04 ldfld 0x4000B28 IL_0006 2d 1f brtrue.s 31 (IL_0027) IL_0008 02 ldarg.0 IL_0009 16 ldc.i4.0 IL_000a 7d 26 0b 00 04 stfld 0x4000B26 IL_000f 02 ldarg.0 IL_0010 28 e6 95 00 06 call 0x60095E6 IL_0015 0a stloc.0 IL_0016 12 00 ldloca.s 0x0 IL_0018 28 db 95 00 06 call 0x60095DB IL_001d 2c 16 brfalse.s 22 (IL_0035) IL_001f 02 ldarg.0 IL_0020 06 ldloc.0 IL_0021 28 fd 36 00 06 call 0x60036FD IL_0026 2a ret IL_0027 02 ldarg.0 IL_0028 02 ldarg.0 IL_0029 7b 28 0b 00 04 ldfld 0x4000B28 IL_002e 17 ldc.i4.1 IL_002f 59 sub IL_0030 7d 28 0b 00 04 stfld 0x4000B28 IL_0035 2a ret INLINER impTokenLookupContextHandle for System.Threading.Lock:ExitImpl():this is 0x0000000000420709. *************** In compInitDebuggingInfo() for System.Threading.Lock:ExitImpl():this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.Lock:ExitImpl():this Jump targets: IL_0027 IL_0035 New Basic Block BB01 [0028] created. BB01 [0028] [000..008) New Basic Block BB02 [0029] created. BB02 [0029] [008..01F) New Basic Block BB03 [0030] created. BB03 [0030] [01F..027) New Basic Block BB04 [0031] created. BB04 [0031] [027..035) New Basic Block BB05 [0032] created. BB05 [0032] [035..036) setting likelihood of BB01 -> BB04 to 0.5 setting likelihood of BB01 -> BB02 to 0.5 setting likelihood of BB02 -> BB05 to 0.5 setting likelihood of BB02 -> BB03 to 0.5 setting likelihood of BB04 -> BB05 to 1 Basic block list for 'System.Threading.Lock:ExitImpl():this' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0028] 1 1 [000..008)-> BB04(0.5),BB02(0.5) ( cond ) BB02 [0029] 1 BB01 1 [008..01F)-> BB05(0.5),BB03(0.5) ( cond ) BB03 [0030] 1 BB02 1 [01F..027) (return) BB04 [0031] 1 BB01 1 [027..035)-> BB05(1) (always) BB05 [0032] 2 BB02,BB04 1 [035..036) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000154] Starting PHASE Pre-import *************** Inline @[000154] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0028] 1 1 [000..008)-> BB04(0.5),BB02(0.5) ( cond ) BB02 [0029] 1 BB01 1 [008..01F)-> BB05(0.5),BB03(0.5) ( cond ) BB03 [0030] 1 BB02 1 [01F..027) (return) BB04 [0031] 1 BB01 1 [027..035)-> BB05(1) (always) BB05 [0032] 2 BB02,BB04 1 [035..036) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0028] [000..008) -> BB04(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB04} ------------ BB02 [0029] [008..01F) -> BB05(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB05} ------------ BB03 [0030] [01F..027) (return), preds={BB02} succs={} ------------ BB04 [0031] [027..035) -> BB05(1) (always), preds={BB01} succs={BB05} ------------ BB05 [0032] [035..036) (return), preds={BB02,BB04} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000154] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000154] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0028] 1 1 [000..008)-> BB04(0.5),BB02(0.5) ( cond ) BB02 [0029] 1 BB01 1 [008..01F)-> BB05(0.5),BB03(0.5) ( cond ) BB03 [0030] 1 BB02 1 [01F..027) (return) BB04 [0031] 1 BB01 1 [027..035)-> BB05(1) (always) BB05 [0032] 2 BB02,BB04 1 [035..036) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0028] [000..008) -> BB04(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB04} ------------ BB02 [0029] [008..01F) -> BB05(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB05} ------------ BB03 [0030] [01F..027) (return), preds={BB02} succs={} ------------ BB04 [0031] [027..035) -> BB05(1) (always), preds={BB01} succs={BB05} ------------ BB05 [0032] [035..036) (return), preds={BB02,BB04} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000154] Starting PHASE Canonicalize entry *************** Inline @[000154] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000154] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.Lock:ExitImpl():this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000B28 [ 1] 6 (0x006) brtrue.s STMT00040 ( 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 impImportBlockPending for BB02 impImportBlockPending for BB04 Importing BB04 (PC=039) of 'System.Threading.Lock:ExitImpl():this' [ 0] 39 (0x027) ldarg.0 [ 1] 40 (0x028) ldarg.0 [ 2] 41 (0x029) ldfld 04000B28 [ 2] 46 (0x02e) ldc.i4.1 1 [ 3] 47 (0x02f) sub [ 2] 48 (0x030) stfld 04000B28 STMT00041 ( 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 [000166] ----------- \--* CNS_INT int 1 impImportBlockPending for BB05 Importing BB05 (PC=053) of 'System.Threading.Lock:ExitImpl():this' [ 0] 53 (0x035) ret Importing BB02 (PC=008) of 'System.Threading.Lock:ExitImpl():this' [ 0] 8 (0x008) ldarg.0 [ 1] 9 (0x009) ldc.i4.0 0 [ 2] 10 (0x00a) stfld 04000B26 STMT00042 ( 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 [ 0] 15 (0x00f) ldarg.0 [ 1] 16 (0x010) call 060095E6 In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 4 CheckCanInline: fetching method info for inline candidate Unlock -- context 0000000000420971 Class context: System.Threading.Lock+State INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.Lock:ExitImpl():this' calling 'System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00043 ( 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000175] I-C-G------ * CALL struct System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State (exactContextHandle=0x0000000000420971) [000174] ----------- arg0 \--* LCL_VAR ref V07 tmp6 [ 1] 21 (0x015) stloc.0 lvaGrabTemp returning 14 (V14 tmp13) (a long lifetime temp) called for Inline stloc first use temp. STMT00044 ( 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct V14 tmp13 [000176] --C-------- \--* RET_EXPR struct(for [000175]) [ 0] 22 (0x016) ldloca.s 0 [ 1] 24 (0x018) call 060095DB In Compiler::impImportCall: opcode is call, kind=0, callRetType is ubyte, structSize is 0 CheckCanInline: fetching method info for inline candidate get_HasAnyWaiters -- context 0000000000420971 Class context: System.Threading.Lock+State INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.Lock:ExitImpl():this' calling 'System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00045 ( 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000179] I-C-G------ * CALL int System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this (exactContextHandle=0x0000000000420971) [000178] ----------- this \--* LCL_ADDR byref V14 tmp13 [+0] [ 1] 29 (0x01d) brfalse.s STMT00046 ( 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000180] --C-------- +--* RET_EXPR int (for [000179]) [000181] ----------- \--* CNS_INT int 0 impImportBlockPending for BB03 impImportBlockPending for BB05 Importing BB03 (PC=031) of 'System.Threading.Lock:ExitImpl():this' [ 0] 31 (0x01f) ldarg.0 [ 1] 32 (0x020) ldloc.0 [ 2] 33 (0x021) call 060036FD In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 Calling impNormStructVal on: [000185] ----------- * LCL_VAR struct V14 tmp13 resulting tree: [000185] ----------- * LCL_VAR struct V14 tmp13 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Threading.Lock:ExitImpl():this' calling 'System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00047 ( 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 [000185] ----------- arg1 \--* LCL_VAR struct V14 tmp13 [ 0] 38 (0x026) ret ** Note: inlinee IL was partially imported -- imported 53 of 54 bytes of method IL *************** Inline @[000154] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0028] 1 1 [000..008)-> BB04(0.5),BB02(0.5) ( cond ) i BB02 [0029] 1 BB01 1 [008..01F)-> BB05(0.5),BB03(0.5) ( cond ) i BB03 [0030] 1 BB02 1 [01F..027) (return) i BB04 [0031] 1 BB01 1 [027..035)-> BB05(1) (always) i BB05 [0032] 2 BB02,BB04 1 [035..036) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0028] [000..008) -> BB04(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB04} ***** BB01 [0028] STMT00040 ( 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 ------------ BB02 [0029] [008..01F) -> BB05(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB05} ***** BB02 [0029] STMT00042 ( 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 ***** BB02 [0029] STMT00043 ( 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000175] I-C-G------ * CALL struct System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State (exactContextHandle=0x0000000000420971) [000174] ----------- arg0 \--* LCL_VAR ref V07 tmp6 ***** BB02 [0029] STMT00044 ( 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct V14 tmp13 [000176] --C-------- \--* RET_EXPR struct(for [000175]) ***** BB02 [0029] STMT00045 ( 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000179] I-C-G------ * CALL int System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this (exactContextHandle=0x0000000000420971) [000178] ----------- this \--* LCL_ADDR byref V14 tmp13 [+0] ***** BB02 [0029] STMT00046 ( 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000180] --C-------- +--* RET_EXPR int (for [000179]) [000181] ----------- \--* CNS_INT int 0 ------------ BB03 [0030] [01F..027) (return), preds={BB02} succs={} ***** BB03 [0030] STMT00047 ( 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 [000185] ----------- arg1 \--* LCL_VAR struct V14 tmp13 ------------ BB04 [0031] [027..035) -> BB05(1) (always), preds={BB01} succs={BB05} ***** BB04 [0031] STMT00041 ( 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 [000166] ----------- \--* CNS_INT int 1 ------------ BB05 [0032] [035..036) (return), preds={BB02,BB04} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000154] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000154] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000154] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000154] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000154] Starting PHASE Post-import *************** Inline @[000154] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000154] ----------- Arguments setup: Inlinee method body: Inserting inlinee blocks New Basic Block BB22 [0033] created. BB18 previous predecessor was BB21, now is BB22 setting likelihood of BB22 -> BB18 from 1 to 1 setting likelihood of BB21 -> BB22 to 1 split BB21 after the inlinee call site; after portion is now BB22 Convert bbKind of BB25 to BBJ_ALWAYS to bottom block BB22 setting likelihood of BB25 -> BB22 to 1 Convert bbKind of BB27 to BBJ_ALWAYS to bottom block BB22 setting likelihood of BB27 -> BB22 to 1 fgInlineAppendStatements: no gc ref inline locals. --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB23 [0028] 1 BB21 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB23 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i BB25 [0030] 1 BB24 1 [000..001)-> BB22(1) (always) i BB26 [0031] 1 BB23 1 [000..001)-> BB27(1) (always) i BB27 [0032] 2 BB24,BB26 1 [000..001)-> BB22(1) (always) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB23 [0028] [000..001) -> BB26(0.5),BB24(0.5) (cond), preds={BB21} succs={BB24,BB26} ***** BB23 [0028] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 ------------ BB24 [0029] [000..001) -> BB27(0.5),BB25(0.5) (cond), preds={BB23} succs={BB25,BB27} ***** BB24 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00043 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000175] I-C-G------ * CALL struct System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State (exactContextHandle=0x0000000000420971) [000174] ----------- arg0 \--* LCL_VAR ref V07 tmp6 ***** BB24 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct V14 tmp13 [000176] --C-------- \--* RET_EXPR struct(for [000175]) ***** BB24 [0029] STMT00045 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000179] I-C-G------ * CALL int System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this (exactContextHandle=0x0000000000420971) [000178] ----------- this \--* LCL_ADDR byref V14 tmp13 [+0] ***** BB24 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000180] --C-------- +--* RET_EXPR int (for [000179]) [000181] ----------- \--* CNS_INT int 0 ------------ BB25 [0030] [000..001) -> BB22(1) (always), preds={BB24} succs={BB22} ***** BB25 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 [000185] ----------- arg1 \--* LCL_VAR struct V14 tmp13 ------------ BB26 [0031] [000..001) -> BB27(1) (always), preds={BB23} succs={BB27} ***** BB26 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 [000166] ----------- \--* CNS_INT int 1 ------------ BB27 [0032] [000..001) -> BB22(1) (always), preds={BB24,BB26} succs={BB22} ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Threading.Lock:ExitImpl():this (54 IL bytes) (depth 3) [aggressive inline attribute] -------------------------------------------------------------------------------------------- BB21 becomes empty INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.Lock:ExitImpl():this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00043 in BB24: STMT00043 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000175] I-C-G------ * CALL struct System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State (exactContextHandle=0x0000000000420971) [000174] ----------- arg0 \--* LCL_VAR ref V07 tmp6 IL argument #0: is a local var [000174] ----------- * LCL_VAR ref V07 tmp6 INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State set to 0x0000000000420971: Invoking compiler for the inlinee method System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State : IL to import: IL_0000 02 ldarg.0 IL_0001 7c 27 0b 00 04 ldflda 0x4000B27 IL_0006 28 24 37 00 06 call 0x6003724 IL_000b 73 c8 95 00 06 newobj 0x60095C8 IL_0010 2a ret INLINER impTokenLookupContextHandle for System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State is 0x0000000000420971. *************** In compInitDebuggingInfo() for System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State Jump targets: none New Basic Block BB01 [0034] created. BB01 [0034] [000..011) Basic block list for 'System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0034] 1 1 [000..011) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000175] Starting PHASE Pre-import *************** Inline @[000175] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0034] 1 1 [000..011) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0034] [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000175] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000175] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0034] 1 1 [000..011) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0034] [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000175] Starting PHASE Canonicalize entry *************** Inline @[000175] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000175] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldflda 04000B27 [ 1] 6 (0x006) call 06003724 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 CheckCanInline: fetching method info for inline candidate Decrement -- context 0000000000420831 Class context: System.Threading.Interlocked INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State' calling 'System.Threading.Interlocked:Decrement(byref):uint' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00048 ( 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000189] I-CXG------ * CALL int System.Threading.Interlocked:Decrement(byref):uint (exactContextHandle=0x0000000000420831) [000188] ---X------- arg0 \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 [ 1] 11 (0x00b) newobj lvaGrabTemp returning 15 (V15 tmp14) called for NewObj constructor temp. STMT00049 ( 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000192] DA--------- * STORE_LCL_VAR struct V15 tmp14 [000191] ----------- \--* CNS_INT int 0 060095C8 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 CheckCanInline: fetching method info for inline candidate .ctor -- context 0000000000420971 Class context: System.Threading.Lock+State INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State' calling 'System.Threading.Lock+State:.ctor(uint):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00050 ( ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000194] I-C-G------ * CALL void System.Threading.Lock+State:.ctor(uint):this (exactContextHandle=0x0000000000420971) [000193] ----------- this +--* LCL_ADDR byref V15 tmp14 [+0] [000190] --C-------- arg1 \--* RET_EXPR int (for [000189]) [ 1] 16 (0x010) ret Inlinee Return expression (before normalization) => [000195] ----------- * LCL_VAR struct V15 tmp14 impFixupStructReturnType: retyping [000195] ----------- * LCL_VAR struct V15 tmp14 Inlinee Return expression (after normalization) => [000195] ----------- * LCL_VAR struct V15 tmp14 *************** Inline @[000175] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0034] 1 1 [000..011) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0034] [000..011) (return), preds={} succs={} ***** BB01 [0034] STMT00048 ( 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000189] I-CXG------ * CALL int System.Threading.Interlocked:Decrement(byref):uint (exactContextHandle=0x0000000000420831) [000188] ---X------- arg0 \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 ***** BB01 [0034] STMT00049 ( 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000192] DA--------- * STORE_LCL_VAR struct V15 tmp14 [000191] ----------- \--* CNS_INT int 0 ***** BB01 [0034] STMT00050 ( ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000194] I-C-G------ * CALL void System.Threading.Lock+State:.ctor(uint):this (exactContextHandle=0x0000000000420971) [000193] ----------- this +--* LCL_ADDR byref V15 tmp14 [+0] [000190] --C-------- arg1 \--* RET_EXPR int (for [000189]) ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000175] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000175] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000175] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000175] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000175] Starting PHASE Post-import *************** Inline @[000175] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000175] ----------- Arguments setup: Inlinee method body: Inserting inlinee code into BB24 STMT00048 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000189] I-CXG------ * CALL int System.Threading.Interlocked:Decrement(byref):uint (exactContextHandle=0x0000000000420831) [000188] ---X------- arg0 \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 STMT00049 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000192] DA--------- * STORE_LCL_VAR struct V15 tmp14 [000191] ----------- \--* CNS_INT int 0 STMT00050 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000194] I-C-G------ * CALL void System.Threading.Lock+State:.ctor(uint):this (exactContextHandle=0x0000000000420971) [000193] ----------- this +--* LCL_ADDR byref V15 tmp14 [+0] [000190] --C-------- arg1 \--* RET_EXPR int (for [000189]) fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State (17 IL bytes) (depth 4) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00048 in BB24: STMT00048 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000189] I-CXG------ * CALL int System.Threading.Interlocked:Decrement(byref):uint (exactContextHandle=0x0000000000420831) [000188] ---X------- arg0 \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 IL argument #0: has side effects [000188] ---X------- * FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.Interlocked:Decrement(byref):uint set to 0x0000000000420831: Invoking compiler for the inlinee method System.Threading.Interlocked:Decrement(byref):uint : IL to import: IL_0000 02 ldarg.0 IL_0001 28 64 09 00 2b call 0x2B000964 IL_0006 15 ldc.i4.m1 IL_0007 28 1c 37 00 06 call 0x600371C IL_000c 2a ret INLINER impTokenLookupContextHandle for System.Threading.Interlocked:Decrement(byref):uint is 0x0000000000420831. *************** In compInitDebuggingInfo() for System.Threading.Interlocked:Decrement(byref):uint info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.Interlocked:Decrement(byref):uint Jump targets: none New Basic Block BB01 [0035] created. BB01 [0035] [000..00D) Basic block list for 'System.Threading.Interlocked:Decrement(byref):uint' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0035] 1 1 [000..00D) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000189] Starting PHASE Pre-import *************** Inline @[000189] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0035] 1 1 [000..00D) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0035] [000..00D) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000189] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000189] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0035] 1 1 [000..00D) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0035] [000..00D) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000189] Starting PHASE Canonicalize entry *************** Inline @[000189] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000189] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.Interlocked:Decrement(byref):uint' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 16 (V16 tmp15) called for Inlining Arg. Marked V16 as a single def temp [ 1] 1 (0x001) call 2B000964 In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Runtime.CompilerServices.Unsafe.As: Recognized [ 1] 6 (0x006) ldc.i4.m1 -1 [ 2] 7 (0x007) call 0600371C In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Named Intrinsic System.Threading.Interlocked.Add: Not recognized CheckCanInline: fetching method info for inline candidate Add -- context 0000000000420831 Class context: System.Threading.Interlocked INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Threading.Interlocked:Decrement(byref):uint' calling 'System.Threading.Interlocked:Add(byref,int):int' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00051 ( 0x000[E-] ... ??? ) <- INL12 @ 0x000[E-] <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000199] I-C-G------ * CALL int System.Threading.Interlocked:Add(byref,int):int (exactContextHandle=0x0000000000420831) [000197] ----------- arg0 +--* LCL_VAR byref V16 tmp15 [000198] ----------- arg1 \--* CNS_INT int -1 [ 1] 12 (0x00c) ret Inlinee Return expression (before normalization) => [000200] --C-------- * RET_EXPR int (for [000199]) Inlinee Return expression (after normalization) => [000200] --C-------- * RET_EXPR int (for [000199]) *************** Inline @[000189] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0035] 1 1 [000..00D) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0035] [000..00D) (return), preds={} succs={} ***** BB01 [0035] STMT00051 ( 0x000[E-] ... ??? ) <- INL12 @ 0x000[E-] <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000199] I-C-G------ * CALL int System.Threading.Interlocked:Add(byref,int):int (exactContextHandle=0x0000000000420831) [000197] ----------- arg0 +--* LCL_VAR byref V16 tmp15 [000198] ----------- arg1 \--* CNS_INT int -1 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000189] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000189] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000189] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000189] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000189] Starting PHASE Post-import *************** Inline @[000189] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000189] ----------- Arguments setup: STMT00052 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000201] DA-X------- * STORE_LCL_VAR byref V16 tmp15 [000188] ---X------- \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 Inlinee method body: Inserting inlinee code into BB24 STMT00051 ( INL13 @ 0x000[E-] ... ??? ) <- INL12 @ 0x000[E-] <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000199] I-C-G------ * CALL int System.Threading.Interlocked:Add(byref,int):int (exactContextHandle=0x0000000000420831) [000197] ----------- arg0 +--* LCL_VAR byref V16 tmp15 [000198] ----------- arg1 \--* CNS_INT int -1 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Threading.Interlocked:Decrement(byref):uint (13 IL bytes) (depth 5) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.Interlocked:Decrement(byref):uint' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00051 in BB24: STMT00051 ( INL13 @ 0x000[E-] ... ??? ) <- INL12 @ 0x000[E-] <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000199] I-C-G------ * CALL int System.Threading.Interlocked:Add(byref,int):int (exactContextHandle=0x0000000000420831) [000197] ----------- arg0 +--* LCL_VAR byref V16 tmp15 [000198] ----------- arg1 \--* CNS_INT int -1 IL argument #0: is a local var [000197] ----------- * LCL_VAR byref V16 tmp15 IL argument #1: is a constant or invariant [000198] ----------- * CNS_INT int -1 INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.Interlocked:Add(byref,int):int set to 0x0000000000420831: Invoking compiler for the inlinee method System.Threading.Interlocked:Add(byref,int):int : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 28 1e 37 00 06 call 0x600371E IL_0007 03 ldarg.1 IL_0008 58 add IL_0009 2a ret INLINER impTokenLookupContextHandle for System.Threading.Interlocked:Add(byref,int):int is 0x0000000000420831. *************** In compInitDebuggingInfo() for System.Threading.Interlocked:Add(byref,int):int info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.Interlocked:Add(byref,int):int Jump targets: none New Basic Block BB01 [0036] created. BB01 [0036] [000..00A) Basic block list for 'System.Threading.Interlocked:Add(byref,int):int' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0036] 1 1 [000..00A) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000199] Starting PHASE Pre-import *************** Inline @[000199] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0036] 1 1 [000..00A) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0036] [000..00A) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000199] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000199] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0036] 1 1 [000..00A) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0036] [000..00A) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000199] Starting PHASE Canonicalize entry *************** Inline @[000199] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000199] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.Interlocked:Add(byref,int):int' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldarg.1 [ 2] 2 (0x002) call 0600371E In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Named Intrinsic System.Threading.Interlocked.ExchangeAdd: Recognized [ 1] 7 (0x007) ldarg.1 [ 2] 8 (0x008) add [ 1] 9 (0x009) ret Inlinee Return expression (before normalization) => [000206] -A-XG------ * ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 Inlinee Return expression (after normalization) => [000206] -A-XG------ * ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 ** Note: inlinee IL was partially imported -- imported 0 of 10 bytes of method IL *************** Inline @[000199] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0036] 1 1 [000..00A) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0036] [000..00A) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000199] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000199] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000199] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000199] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000199] Starting PHASE Post-import *************** Inline @[000199] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000199] ----------- Arguments setup: Inlinee method body: inlinee was empty fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Threading.Interlocked:Add(byref,int):int (10 IL bytes) (depth 6) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.Interlocked:Add(byref,int):int' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000190] with [000206] [000190] --C-------- * RET_EXPR int (for [000189]) -> [000200] Inserting the inline return expression [000206] -A-XG------ * ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 Expanding INLINE_CANDIDATE in statement STMT00050 in BB24: STMT00050 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000194] I-C-G------ * CALL void System.Threading.Lock+State:.ctor(uint):this (exactContextHandle=0x0000000000420971) [000193] ----------- this +--* LCL_ADDR byref V15 tmp14 [+0] [000206] -A-XG------ arg1 \--* ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 ThisPointer: is a constant or invariant is byref to a struct local [000193] ----------- * LCL_ADDR byref V15 tmp14 [+0] IL argument #1: has global refs has side effects [000206] -A-XG------ * ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.Lock+State:.ctor(uint):this set to 0x0000000000420971: Invoking compiler for the inlinee method System.Threading.Lock+State:.ctor(uint):this : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 7d 28 25 00 04 stfld 0x4002528 IL_0007 2a ret INLINER impTokenLookupContextHandle for System.Threading.Lock+State:.ctor(uint):this is 0x0000000000420971. *************** In compInitDebuggingInfo() for System.Threading.Lock+State:.ctor(uint):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.Lock+State:.ctor(uint):this Jump targets: none New Basic Block BB01 [0037] created. BB01 [0037] [000..008) Basic block list for 'System.Threading.Lock+State:.ctor(uint):this' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0037] 1 1 [000..008) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000194] Starting PHASE Pre-import *************** Inline @[000194] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0037] 1 1 [000..008) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0037] [000..008) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000194] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000194] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0037] 1 1 [000..008) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0037] [000..008) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000194] Starting PHASE Canonicalize entry *************** Inline @[000194] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000194] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.Lock+State:.ctor(uint):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldarg.1 lvaGrabTemp returning 17 (V17 tmp16) called for Inlining Arg. Marked V17 as a single def temp [ 2] 2 (0x002) stfld 04002528 STMT00053 ( 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] nA--------- * STOREIND int [000210] ----------- +--* FIELD_ADDR byref System.Threading.Lock+State:_state [000208] ----------- | \--* LCL_ADDR byref V15 tmp14 [+0] [000209] ----------- \--* LCL_VAR int V17 tmp16 [ 0] 7 (0x007) ret *************** Inline @[000194] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0037] 1 1 [000..008) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0037] [000..008) (return), preds={} succs={} ***** BB01 [0037] STMT00053 ( 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] nA--------- * STOREIND int [000210] ----------- +--* FIELD_ADDR byref System.Threading.Lock+State:_state [000208] ----------- | \--* LCL_ADDR byref V15 tmp14 [+0] [000209] ----------- \--* LCL_VAR int V17 tmp16 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000194] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000194] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000194] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000194] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000194] Starting PHASE Post-import *************** Inline @[000194] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000194] ----------- Arguments setup: STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 Inlinee method body: Inserting inlinee code into BB24 STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] nA--------- * STOREIND int [000210] ----------- +--* FIELD_ADDR byref System.Threading.Lock+State:_state [000208] ----------- | \--* LCL_ADDR byref V15 tmp14 [+0] [000209] ----------- \--* LCL_VAR int V17 tmp16 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Threading.Lock+State:.ctor(uint):this (8 IL bytes) (depth 5) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.Lock+State:.ctor(uint):this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000176] with [000195] [000176] --C-------- * RET_EXPR struct(for [000175]) -> [000195] Inserting the inline return expression [000195] ----------- * LCL_VAR struct V15 tmp14 Expanding INLINE_CANDIDATE in statement STMT00045 in BB24: STMT00045 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000179] I-C-G------ * CALL int System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this (exactContextHandle=0x0000000000420971) [000178] ----------- this \--* LCL_ADDR byref V14 tmp13 [+0] ThisPointer: is a constant or invariant is byref to a struct local [000178] ----------- * LCL_ADDR byref V14 tmp13 [+0] INLINER: inlineInfo.tokenLookupContextHandle for System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this set to 0x0000000000420971: Invoking compiler for the inlinee method System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 28 25 00 04 ldfld 0x4002528 IL_0006 20 80 00 00 00 ldc.i4 0x80 IL_000b fe 05 clt.un IL_000d 16 ldc.i4.0 IL_000e fe 01 ceq IL_0010 2a ret INLINER impTokenLookupContextHandle for System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this is 0x0000000000420971. *************** In compInitDebuggingInfo() for System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 38 : state 33 [ ldc.i4 ] weight= 85 : state 172 [ clt.un ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 20 : state 168 [ ceq ] weight= 19 : state 42 [ ret ] Notify VM instruction set (AdvSimd) must be supported. multiplier in methods of promotable struct increased to 3. Inline candidate has an arg that feeds a constant test. Multiplier increased to 4. Inline candidate is mostly loads and stores. Multiplier increased to 7. Inline candidate has const arg that feeds a conditional. Multiplier increased to 10. Inline candidate callsite is boring. Multiplier increased to 11.3. calleeNativeSizeEstimate=208 callsiteNativeSizeEstimate=85 benefit multiplier=11.3 threshold=960 Native estimate for function size is within threshold for inlining 20.8 <= 96 (multiplier = 11.3) Jump targets: none New Basic Block BB01 [0038] created. BB01 [0038] [000..011) Basic block list for 'System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this' --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0038] 1 1 [000..011) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000179] Starting PHASE Pre-import *************** Inline @[000179] Finishing PHASE Pre-import Trees after Pre-import --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0038] 1 1 [000..011) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0038] [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Inline @[000179] Starting PHASE Profile incorporation BBOPT not set Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000179] Finishing PHASE Profile incorporation Trees after Profile incorporation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0038] 1 1 [000..011) (return) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0038] [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000179] Starting PHASE Canonicalize entry *************** Inline @[000179] Finishing PHASE Canonicalize entry [no changes] *************** Inline @[000179] Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04002528 [ 1] 6 (0x006) ldc.i4 128 [ 2] 11 (0x00b) clt.un [ 1] 13 (0x00d) ldc.i4.0 0 [ 2] 14 (0x00e) ceq [ 1] 16 (0x010) ret Inlinee Return expression (before normalization) => [000220] ----------- * EQ int [000218] N--------U- +--* LT int [000216] n---------- | +--* IND int [000215] ----------- | | \--* FIELD_ADDR byref System.Threading.Lock+State:_state [000214] ----------- | | \--* LCL_ADDR byref V14 tmp13 [+0] [000217] ----------- | \--* CNS_INT int 128 [000219] ----------- \--* CNS_INT int 0 Inlinee Return expression (after normalization) => [000220] ----------- * EQ int [000218] N--------U- +--* LT int [000216] n---------- | +--* IND int [000215] ----------- | | \--* FIELD_ADDR byref System.Threading.Lock+State:_state [000214] ----------- | | \--* LCL_ADDR byref V14 tmp13 [+0] [000217] ----------- | \--* CNS_INT int 128 [000219] ----------- \--* CNS_INT int 0 ** Note: inlinee IL was partially imported -- imported 0 of 17 bytes of method IL *************** Inline @[000179] Finishing PHASE Importation Trees after Importation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0038] 1 1 [000..011) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0038] [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Inline @[000179] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000179] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000179] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000179] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000179] Starting PHASE Post-import *************** Inline @[000179] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000179] ----------- Arguments setup: Inlinee method body: inlinee was empty fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this (17 IL bytes) (depth 4) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Replacing the return expression placeholder [000180] with [000220] [000180] --C-------- * RET_EXPR int (for [000179]) -> [000220] Inserting the inline return expression [000220] ----------- * EQ int [000218] N--------U- +--* LT int [000216] n---------- | +--* IND int [000215] ----------- | | \--* FIELD_ADDR byref System.Threading.Lock+State:_state [000214] ----------- | | \--* LCL_ADDR byref V14 tmp13 [+0] [000217] ----------- | \--* CNS_INT int 128 [000219] ----------- \--* CNS_INT int 0 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Threading.Monitor:Exit(System.Object)' calling 'System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' **************** Inline Tree Inlines into 0600374F [via ExtendedDefaultPolicy] System.Threading.Monitor:Exit(System.Object): [INL01 IL=-572662307 TR=000001 06003768] [INLINED: callee: aggressive inline attribute] System.Threading.ObjectHeader:Release(System.Object) [INL02 IL=-572662307 TR=000004 0600072B] [INLINED: callee: below ALWAYS_INLINE size] System.ArgumentNullException:ThrowIfNull(System.Object,System.String) [INL00 IL=-572662307 TR=000099 0600072F] [FAILED: callee: does not return] System.ArgumentNullException:Throw(System.String) [INL00 IL=0004 TR=000099 0600072F] [FAILED: callee: does not return] System.ArgumentNullException:Throw(System.String) [INL03 IL=-572662307 TR=000005 060036D7] [INLINED: callee: below ALWAYS_INLINE size] System.Threading.ManagedThreadId:get_CurrentManagedThreadIdUnchecked():int [INL04 IL=-572662307 TR=000017 06006FEF] [INLINED: callee: below ALWAYS_INLINE size] System.Runtime.CompilerServices.RuntimeHelpers:GetMethodTableRef(System.Object):byref [INL05 IL=-572662307 TR=000022 0600375C] [INLINED: callee: aggressive inline attribute] System.Threading.ObjectHeader:GetHeaderPtr(ulong):ulong [INL06 IL=-572662307 TR=000037 06003761] [INLINED: callee: aggressive inline attribute] System.Threading.ObjectHeader:GetSyncEntryIndex(int,byref):ubyte [INL07 IL=-572662307 TR=000118 06003760] [INLINED: callee: aggressive inline attribute] System.Threading.ObjectHeader:HasSyncEntryIndex(int):ubyte [INL00 IL=0122 TR=000056 060039AE] [FAILED: callee: too many il bytes] System.Threading.SynchronizationLockException:.ctor():this [INL08 IL=-572662307 TR=000043 06003772] [INLINED: callee: below ALWAYS_INLINE size] System.Threading.SyncTable:GetLockObject(int):System.Threading.Lock [INL09 IL=-572662307 TR=000127 0600376A] [INLINED: callee: aggressive inline attribute] System.Threading.SyncTable:UnsafeEntryRef(int):byref [INL10 IL=-572662307 TR=000051 060036E2] [INLINED: callee: aggressive inline attribute] System.Threading.Lock:Exit(int):this [INL00 IL=-572662307 TR=000155 06002009] [FAILED: callee: does not return] System.ThrowHelper:ThrowSynchronizationLockException_LockExit() [INL00 IL=0009 TR=000155 06002009] [FAILED: callee: does not return] System.ThrowHelper:ThrowSynchronizationLockException_LockExit() [INL11 IL=-572662307 TR=000154 060036F6] [INLINED: callee: aggressive inline attribute] System.Threading.Lock:ExitImpl():this [INL12 IL=-572662307 TR=000175 060095E6] [INLINED: callee: aggressive inline attribute] System.Threading.Lock+State:Unlock(System.Threading.Lock):System.Threading.Lock+State [INL13 IL=-572662307 TR=000189 06003724] [INLINED: callee: aggressive inline attribute] System.Threading.Interlocked:Decrement(byref):uint [INL14 IL=-572662307 TR=000199 0600371C] [INLINED: callee: below ALWAYS_INLINE size] System.Threading.Interlocked:Add(byref,int):int [INL15 IL=-572662307 TR=000194 060095C8] [INLINED: callee: below ALWAYS_INLINE size] System.Threading.Lock+State:.ctor(uint):this [INL16 IL=-572662307 TR=000179 060095DB] [INLINED: call site: profitable inline] System.Threading.Lock+State:get_HasAnyWaiters():ubyte:this [INL00 IL=0033 TR=000186 060036FD] [FAILED: callee: noinline per IL/cached result] System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this Budget: initialTime=81, finalTime=481, initialBudget=810, currentBudget=1258 Budget: increased by 448 because of force inlines Budget: discretionary inline caused a force inline Budget: initialSize=290, finalSize=413 *************** Finishing PHASE Morph - Inlining Trees after Morph - Inlining --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(1) (always) i BB03 [0001] 1 BB01 1 [000..000)-> BB15(1) (always) i BB15 [0013] 1 BB03 1 [000..001)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB15 1 [000..001)-> BB17(1) (always) i BB17 [0015] 2 BB15,BB16 1 [000..001)-> BB14(1) (always) i BB14 [0016] 1 BB17 1 [000..001)-> BB04(1) (always) i BB04 [0002] 2 BB09,BB14 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB10(0.5) ( cond ) i bwd bwd-src BB10 [0008] 1 BB09 1 [000..001)-> BB02(1) (always) i BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare newobj BB13 [0011] 1 BB11 1 [000..???)-> BB19(1) (always) i nullcheck BB19 [0024] 1 BB13 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i BB20 [0025] 1 BB19 1 [000..001)-> BB21(1) (always) i BB21 [0026] 2 BB19,BB20 1 [000..???)-> BB23(1) (always) i BB23 [0028] 1 BB21 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB23 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i BB25 [0030] 1 BB24 1 [000..001)-> BB22(1) (always) i BB26 [0031] 1 BB23 1 [000..001)-> BB27(1) (always) i BB27 [0032] 2 BB24,BB26 1 [000..001)-> BB22(1) (always) i BB22 [0033] 2 BB25,BB27 1 [001..001)-> BB18(1) (always) i BB18 [0027] 1 BB22 1 [001..001)-> BB02(1) (always) i nullcheck BB02 [0012] 2 BB10,BB18 1 [006..007) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(1) (always), preds={} succs={BB03} ------------ BB03 [0001] [000..000) -> BB15(1) (always), preds={BB01} succs={BB15} ------------ BB15 [0013] [000..001) -> BB17(0.5),BB16(0.5) (cond), preds={BB03} succs={BB16,BB17} ***** BB15 [0013] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null ------------ BB16 [0014] [000..001) -> BB17(1) (always), preds={BB15} succs={BB17} ***** BB16 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --C-G------ * CALL void System.ArgumentNullException:Throw(System.String) [000098] ----------- arg0 \--* CNS_STR ref ------------ BB17 [0015] [000..001) -> BB14(1) (always), preds={BB15,BB16} succs={BB14} ------------ BB14 [0016] [000..001) -> BB04(1) (always), preds={BB17} succs={BB04} ***** BB14 [0016] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G------ \--* IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB14 [0016] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 ***** BB14 [0016] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000106] ---X------- \--* FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 ***** BB14 [0016] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000111] ----------- \--* SUB long [000021] ---------U- +--* CAST long <- ulong <- byref [000020] ----------- | \--* LCL_VAR byref V03 tmp2 [000110] ----------- \--* CNS_INT long 4 ------------ BB04 [0002] [000..001) -> BB11(0.5),BB05(0.5) (cond), preds={BB09,BB14} succs={BB05,BB11} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB11(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB11} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB10(0.5) (cond), preds={BB07,BB08} succs={BB10,BB04} ***** BB09 [0007] STMT00024 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000079] ----------- | +--* LCL_VAR int V10 tmp9 [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0008] [000..001) -> BB02(1) (always), preds={BB09} succs={BB02} ------------ BB11 [0009] [000..001) -> BB13(1),BB12(0) (cond), preds={BB04,BB05} succs={BB12,BB13} ***** BB11 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] nA--G------ * STOREIND int [000113] ----------- +--* LCL_ADDR long V06 tmp5 [+0] [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF ***** BB11 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000124] ----------- +--* EQ int [000122] ----------- | +--* AND int [000117] ----------- | | +--* LCL_VAR int V05 tmp4 [000121] ----------- | | \--* CNS_INT int 0xC000000 [000123] ----------- | \--* CNS_INT int 0x8000000 [000039] ----------- \--* CNS_INT int 0 ------------ BB12 [0010] [000..001) (throw), preds={BB11} succs={} ***** BB12 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DA--------- * STORE_LCL_VAR ref V08 tmp7 [000053] ----------- \--* ALLOCOBJ ref [000052] H---------- \--* CNS_INT(h) long 0x420818 class ***** BB12 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 ***** BB12 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 ------------ BB13 [0011] [000..???) -> BB19(1) (always), preds={BB11} succs={BB19} ***** BB13 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA--------- * STORE_LCL_VAR int V12 tmp11 [000042] ----------- \--* LCL_VAR int V06 tmp5 ***** BB13 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] ***** BB13 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 ***** BB13 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000130] n-CXG------ \--* IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000147] ---XG------ \--* ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 [000145] ----------- \--* CNS_INT long 32 ***** BB13 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 ------------ BB19 [0024] [000..001) -> BB21(0.5),BB20(0.5) (cond), preds={BB13} succs={BB20,BB21} ***** BB19 [0024] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB20 [0025] [000..001) -> BB21(1) (always), preds={BB19} succs={BB21} ***** BB20 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB21 [0026] [000..???) -> BB23(1) (always), preds={BB19,BB20} succs={BB23} ------------ BB23 [0028] [000..001) -> BB26(0.5),BB24(0.5) (cond), preds={BB21} succs={BB24,BB26} ***** BB23 [0028] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 ------------ BB24 [0029] [000..001) -> BB27(0.5),BB25(0.5) (cond), preds={BB23} succs={BB25,BB27} ***** BB24 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00052 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000201] DA-X------- * STORE_LCL_VAR byref V16 tmp15 [000188] ---X------- \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 ***** BB24 [0029] STMT00049 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000192] DA--------- * STORE_LCL_VAR struct V15 tmp14 [000191] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 ***** BB24 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] nA--------- * STOREIND int [000210] ----------- +--* FIELD_ADDR byref System.Threading.Lock+State:_state [000208] ----------- | \--* LCL_ADDR byref V15 tmp14 [+0] [000209] ----------- \--* LCL_VAR int V17 tmp16 ***** BB24 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct V14 tmp13 [000195] ----------- \--* LCL_VAR struct V15 tmp14 ***** BB24 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000220] ----------- +--* EQ int [000218] N--------U- | +--* LT int [000216] n---------- | | +--* IND int [000215] ----------- | | | \--* FIELD_ADDR byref System.Threading.Lock+State:_state [000214] ----------- | | | \--* LCL_ADDR byref V14 tmp13 [+0] [000217] ----------- | | \--* CNS_INT int 128 [000219] ----------- | \--* CNS_INT int 0 [000181] ----------- \--* CNS_INT int 0 ------------ BB25 [0030] [000..001) -> BB22(1) (always), preds={BB24} succs={BB22} ***** BB25 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 [000185] ----------- arg1 \--* LCL_VAR struct V14 tmp13 ------------ BB26 [0031] [000..001) -> BB27(1) (always), preds={BB23} succs={BB27} ***** BB26 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 [000166] ----------- \--* CNS_INT int 1 ------------ BB27 [0032] [000..001) -> BB22(1) (always), preds={BB24,BB26} succs={BB22} ------------ BB22 [0033] [001..001) -> BB18(1) (always), preds={BB25,BB27} succs={BB18} ------------ BB18 [0027] [001..001) -> BB02(1) (always), preds={BB22} succs={BB02} ------------ BB02 [0012] [006..007) (return), preds={BB10,BB18} succs={} ***** BB02 [0012] STMT00027 ( 0x000[E-] ... ??? ) [000091] DA--------- * STORE_LCL_VAR ref V07 tmp6 [000090] ----------- \--* CNS_INT ref null ***** BB02 [0012] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000092] ----------- \--* CNS_INT byref 0 ***** BB02 [0012] STMT00001 ( 0x006[E-] ... ??? ) [000002] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE DFS blocks and remove dead code 1 *************** Finishing PHASE DFS blocks and remove dead code 1 [no changes] *************** Starting PHASE Allocate Objects enabled, analyzing... ... V00 ... checking [000096] V02 first escapes via [000008] ... V00 ... checking [000106] ... V00 ... checking [000019] ... V03 ... checking [000021] V03 first escapes via [000020] ... V04 ... checking [000026] V05 first escapes via [000028] V06 first escapes via [000113] ... V13 ... checking [000141] ... V13 ... checking [000143] ... V13 ... checking [000147] ... V13 ... checking [000129] ... V13 ... checking [000130] V12 first escapes via [000126] ... V07 ... checking [000149] ... V07 ... checking [000150] ... V07 ... checking [000157] ... V07 ... checking [000158] ... V07 ... checking [000168] ... V07 ... checking [000169] ... V07 ... checking [000164] ... V07 ... checking [000165] ... V07 ... checking [000172] ... V07 ... checking [000173] ... V07 ... checking [000188] ... V07 ... checking [000201] ... V16 ... checking [000204] V16 first escapes via [000197] V15 first escapes via [000208] V17 first escapes via [000209] V14 first escapes via [000214] ... V07 ... checking [000186] V07 first escapes via [000184] ... V08 ... checking [000056] V08 first escapes via [000055] V09 first escapes via [000076] ... V04 ... checking [000081] V04 first escapes via [000078] V10 first escapes via [000079] Computing escape closure V03 causes V00 to escape Allocating V08 on the heap: [escapes] *************** Finishing PHASE Allocate Objects Trees after Allocate Objects --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(1) (always) i BB03 [0001] 1 BB01 1 [000..000)-> BB15(1) (always) i BB15 [0013] 1 BB03 1 [000..001)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB15 1 [000..001)-> BB17(1) (always) i BB17 [0015] 2 BB15,BB16 1 [000..001)-> BB14(1) (always) i BB14 [0016] 1 BB17 1 [000..001)-> BB04(1) (always) i BB04 [0002] 2 BB09,BB14 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB10(0.5) ( cond ) i bwd bwd-src BB10 [0008] 1 BB09 1 [000..001)-> BB02(1) (always) i BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare newobj BB13 [0011] 1 BB11 1 [000..???)-> BB19(1) (always) i nullcheck BB19 [0024] 1 BB13 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i BB20 [0025] 1 BB19 1 [000..001)-> BB21(1) (always) i BB21 [0026] 2 BB19,BB20 1 [000..???)-> BB23(1) (always) i BB23 [0028] 1 BB21 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB23 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i BB25 [0030] 1 BB24 1 [000..001)-> BB22(1) (always) i BB26 [0031] 1 BB23 1 [000..001)-> BB27(1) (always) i BB27 [0032] 2 BB24,BB26 1 [000..001)-> BB22(1) (always) i BB22 [0033] 2 BB25,BB27 1 [001..001)-> BB18(1) (always) i BB18 [0027] 1 BB22 1 [001..001)-> BB02(1) (always) i nullcheck BB02 [0012] 2 BB10,BB18 1 [006..007) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(1) (always), preds={} succs={BB03} ------------ BB03 [0001] [000..000) -> BB15(1) (always), preds={BB01} succs={BB15} ------------ BB15 [0013] [000..001) -> BB17(0.5),BB16(0.5) (cond), preds={BB03} succs={BB16,BB17} ***** BB15 [0013] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null ------------ BB16 [0014] [000..001) -> BB17(1) (always), preds={BB15} succs={BB17} ***** BB16 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --C-G------ * CALL void System.ArgumentNullException:Throw(System.String) [000098] ----------- arg0 \--* CNS_STR ref ------------ BB17 [0015] [000..001) -> BB14(1) (always), preds={BB15,BB16} succs={BB14} ------------ BB14 [0016] [000..001) -> BB04(1) (always), preds={BB17} succs={BB04} ***** BB14 [0016] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G------ \--* IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB14 [0016] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 ***** BB14 [0016] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000106] ---X------- \--* FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 ***** BB14 [0016] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000111] ----------- \--* SUB long [000021] ---------U- +--* CAST long <- ulong <- byref [000020] ----------- | \--* LCL_VAR byref V03 tmp2 [000110] ----------- \--* CNS_INT long 4 ------------ BB04 [0002] [000..001) -> BB11(0.5),BB05(0.5) (cond), preds={BB09,BB14} succs={BB05,BB11} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB11(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB11} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB10(0.5) (cond), preds={BB07,BB08} succs={BB10,BB04} ***** BB09 [0007] STMT00024 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000079] ----------- | +--* LCL_VAR int V10 tmp9 [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0008] [000..001) -> BB02(1) (always), preds={BB09} succs={BB02} ------------ BB11 [0009] [000..001) -> BB13(1),BB12(0) (cond), preds={BB04,BB05} succs={BB12,BB13} ***** BB11 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] nA--G------ * STOREIND int [000113] ----------- +--* LCL_ADDR long V06 tmp5 [+0] [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF ***** BB11 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000124] ----------- +--* EQ int [000122] ----------- | +--* AND int [000117] ----------- | | +--* LCL_VAR int V05 tmp4 [000121] ----------- | | \--* CNS_INT int 0xC000000 [000123] ----------- | \--* CNS_INT int 0x8000000 [000039] ----------- \--* CNS_INT int 0 ------------ BB12 [0010] [000..001) (throw), preds={BB11} succs={} ***** BB12 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC-------- * STORE_LCL_VAR ref V08 tmp7 [000053] --C-------- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H---------- arg0 \--* CNS_INT(h) long 0x420818 class ***** BB12 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 ***** BB12 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 ------------ BB13 [0011] [000..???) -> BB19(1) (always), preds={BB11} succs={BB19} ***** BB13 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA--------- * STORE_LCL_VAR int V12 tmp11 [000042] ----------- \--* LCL_VAR int V06 tmp5 ***** BB13 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] ***** BB13 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 ***** BB13 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000130] n-CXG------ \--* IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000147] ---XG------ \--* ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 [000145] ----------- \--* CNS_INT long 32 ***** BB13 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 ------------ BB19 [0024] [000..001) -> BB21(0.5),BB20(0.5) (cond), preds={BB13} succs={BB20,BB21} ***** BB19 [0024] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB20 [0025] [000..001) -> BB21(1) (always), preds={BB19} succs={BB21} ***** BB20 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB21 [0026] [000..???) -> BB23(1) (always), preds={BB19,BB20} succs={BB23} ------------ BB23 [0028] [000..001) -> BB26(0.5),BB24(0.5) (cond), preds={BB21} succs={BB24,BB26} ***** BB23 [0028] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 ------------ BB24 [0029] [000..001) -> BB27(0.5),BB25(0.5) (cond), preds={BB23} succs={BB25,BB27} ***** BB24 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00052 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000201] DA-X------- * STORE_LCL_VAR byref V16 tmp15 [000188] ---X------- \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 ***** BB24 [0029] STMT00049 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000192] DA--------- * STORE_LCL_VAR struct V15 tmp14 [000191] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 ***** BB24 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] nA--------- * STOREIND int [000210] ----------- +--* FIELD_ADDR byref System.Threading.Lock+State:_state [000208] ----------- | \--* LCL_ADDR byref V15 tmp14 [+0] [000209] ----------- \--* LCL_VAR int V17 tmp16 ***** BB24 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct V14 tmp13 [000195] ----------- \--* LCL_VAR struct V15 tmp14 ***** BB24 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000220] ----------- +--* EQ int [000218] N--------U- | +--* LT int [000216] n---------- | | +--* IND int [000215] ----------- | | | \--* FIELD_ADDR byref System.Threading.Lock+State:_state [000214] ----------- | | | \--* LCL_ADDR byref V14 tmp13 [+0] [000217] ----------- | | \--* CNS_INT int 128 [000219] ----------- | \--* CNS_INT int 0 [000181] ----------- \--* CNS_INT int 0 ------------ BB25 [0030] [000..001) -> BB22(1) (always), preds={BB24} succs={BB22} ***** BB25 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 [000185] ----------- arg1 \--* LCL_VAR struct V14 tmp13 ------------ BB26 [0031] [000..001) -> BB27(1) (always), preds={BB23} succs={BB27} ***** BB26 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 [000166] ----------- \--* CNS_INT int 1 ------------ BB27 [0032] [000..001) -> BB22(1) (always), preds={BB24,BB26} succs={BB22} ------------ BB22 [0033] [001..001) -> BB18(1) (always), preds={BB25,BB27} succs={BB18} ------------ BB18 [0027] [001..001) -> BB02(1) (always), preds={BB22} succs={BB02} ------------ BB02 [0012] [006..007) (return), preds={BB10,BB18} succs={} ***** BB02 [0012] STMT00027 ( 0x000[E-] ... ??? ) [000091] DA--------- * STORE_LCL_VAR ref V07 tmp6 [000090] ----------- \--* CNS_INT ref null ***** BB02 [0012] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000092] ----------- \--* CNS_INT byref 0 ***** BB02 [0012] STMT00001 ( 0x006[E-] ... ??? ) [000002] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Morph - Add internal blocks *************** After fgAddInternal() --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(1) (always) i BB03 [0001] 1 BB01 1 [000..000)-> BB15(1) (always) i BB15 [0013] 1 BB03 1 [000..001)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB15 1 [000..001)-> BB17(1) (always) i BB17 [0015] 2 BB15,BB16 1 [000..001)-> BB14(1) (always) i BB14 [0016] 1 BB17 1 [000..001)-> BB04(1) (always) i BB04 [0002] 2 BB09,BB14 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB10(0.5) ( cond ) i bwd bwd-src BB10 [0008] 1 BB09 1 [000..001)-> BB02(1) (always) i BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare newobj BB13 [0011] 1 BB11 1 [000..???)-> BB19(1) (always) i nullcheck BB19 [0024] 1 BB13 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i BB20 [0025] 1 BB19 1 [000..001)-> BB21(1) (always) i BB21 [0026] 2 BB19,BB20 1 [000..???)-> BB23(1) (always) i BB23 [0028] 1 BB21 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB23 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i BB25 [0030] 1 BB24 1 [000..001)-> BB22(1) (always) i BB26 [0031] 1 BB23 1 [000..001)-> BB27(1) (always) i BB27 [0032] 2 BB24,BB26 1 [000..001)-> BB22(1) (always) i BB22 [0033] 2 BB25,BB27 1 [001..001)-> BB18(1) (always) i BB18 [0027] 1 BB22 1 [001..001)-> BB02(1) (always) i nullcheck BB02 [0012] 2 BB10,BB18 1 [006..007) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks [no changes] *************** Starting PHASE Add Swift error returns *************** Finishing PHASE Add Swift error returns [no changes] *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty try/catch/fault *************** In fgRemoveEmptyTryCatchOrTryFault() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try/catch/fault [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Head and tail merge *************** Finishing PHASE Head and tail merge Trees after Head and tail merge --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(1) (always) i BB03 [0001] 1 BB01 1 [000..000)-> BB15(1) (always) i BB15 [0013] 1 BB03 1 [000..001)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB15 1 [000..001)-> BB17(1) (always) i BB17 [0015] 2 BB15,BB16 1 [000..001)-> BB14(1) (always) i BB14 [0016] 1 BB17 1 [000..001)-> BB04(1) (always) i BB04 [0002] 2 BB09,BB14 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB10(0.5) ( cond ) i bwd bwd-src BB10 [0008] 1 BB09 1 [000..001)-> BB02(1) (always) i BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare newobj BB13 [0011] 1 BB11 1 [000..???)-> BB19(1) (always) i nullcheck BB19 [0024] 1 BB13 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i BB20 [0025] 1 BB19 1 [000..001)-> BB21(1) (always) i BB21 [0026] 2 BB19,BB20 1 [000..???)-> BB23(1) (always) i BB23 [0028] 1 BB21 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB23 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i BB25 [0030] 1 BB24 1 [000..001)-> BB22(1) (always) i BB26 [0031] 1 BB23 1 [000..001)-> BB27(1) (always) i BB27 [0032] 2 BB24,BB26 1 [000..001)-> BB22(1) (always) i BB22 [0033] 2 BB25,BB27 1 [001..001)-> BB18(1) (always) i BB18 [0027] 1 BB22 1 [001..001)-> BB02(1) (always) i nullcheck BB02 [0012] 2 BB10,BB18 1 [006..007) (return) i --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(1) (always), preds={} succs={BB03} ------------ BB03 [0001] [000..000) -> BB15(1) (always), preds={BB01} succs={BB15} ------------ BB15 [0013] [000..001) -> BB17(0.5),BB16(0.5) (cond), preds={BB03} succs={BB16,BB17} ***** BB15 [0013] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null ------------ BB16 [0014] [000..001) -> BB17(1) (always), preds={BB15} succs={BB17} ***** BB16 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --C-G------ * CALL void System.ArgumentNullException:Throw(System.String) [000098] ----------- arg0 \--* CNS_STR ref ------------ BB17 [0015] [000..001) -> BB14(1) (always), preds={BB15,BB16} succs={BB14} ------------ BB14 [0016] [000..001) -> BB04(1) (always), preds={BB17} succs={BB04} ***** BB14 [0016] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G------ \--* IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB14 [0016] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 ***** BB14 [0016] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000106] ---X------- \--* FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 ***** BB14 [0016] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000111] ----------- \--* SUB long [000021] ---------U- +--* CAST long <- ulong <- byref [000020] ----------- | \--* LCL_VAR byref V03 tmp2 [000110] ----------- \--* CNS_INT long 4 ------------ BB04 [0002] [000..001) -> BB11(0.5),BB05(0.5) (cond), preds={BB09,BB14} succs={BB05,BB11} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB11(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB11} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB10(0.5) (cond), preds={BB07,BB08} succs={BB10,BB04} ***** BB09 [0007] STMT00024 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000079] ----------- | +--* LCL_VAR int V10 tmp9 [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0008] [000..001) -> BB02(1) (always), preds={BB09} succs={BB02} ------------ BB11 [0009] [000..001) -> BB13(1),BB12(0) (cond), preds={BB04,BB05} succs={BB12,BB13} ***** BB11 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] nA--G------ * STOREIND int [000113] ----------- +--* LCL_ADDR long V06 tmp5 [+0] [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF ***** BB11 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000124] ----------- +--* EQ int [000122] ----------- | +--* AND int [000117] ----------- | | +--* LCL_VAR int V05 tmp4 [000121] ----------- | | \--* CNS_INT int 0xC000000 [000123] ----------- | \--* CNS_INT int 0x8000000 [000039] ----------- \--* CNS_INT int 0 ------------ BB12 [0010] [000..001) (throw), preds={BB11} succs={} ***** BB12 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC-------- * STORE_LCL_VAR ref V08 tmp7 [000053] --C-------- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H---------- arg0 \--* CNS_INT(h) long 0x420818 class ***** BB12 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 ***** BB12 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 ------------ BB13 [0011] [000..???) -> BB19(1) (always), preds={BB11} succs={BB19} ***** BB13 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA--------- * STORE_LCL_VAR int V12 tmp11 [000042] ----------- \--* LCL_VAR int V06 tmp5 ***** BB13 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] ***** BB13 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 ***** BB13 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000130] n-CXG------ \--* IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000147] ---XG------ \--* ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 [000145] ----------- \--* CNS_INT long 32 ***** BB13 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 ------------ BB19 [0024] [000..001) -> BB21(0.5),BB20(0.5) (cond), preds={BB13} succs={BB20,BB21} ***** BB19 [0024] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB20 [0025] [000..001) -> BB21(1) (always), preds={BB19} succs={BB21} ***** BB20 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB21 [0026] [000..???) -> BB23(1) (always), preds={BB19,BB20} succs={BB23} ------------ BB23 [0028] [000..001) -> BB26(0.5),BB24(0.5) (cond), preds={BB21} succs={BB24,BB26} ***** BB23 [0028] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 ------------ BB24 [0029] [000..001) -> BB27(0.5),BB25(0.5) (cond), preds={BB23} succs={BB25,BB27} ***** BB24 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00052 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000201] DA-X------- * STORE_LCL_VAR byref V16 tmp15 [000188] ---X------- \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 ***** BB24 [0029] STMT00049 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000192] DA--------- * STORE_LCL_VAR struct V15 tmp14 [000191] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 ***** BB24 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] nA--------- * STOREIND int [000210] ----------- +--* FIELD_ADDR byref System.Threading.Lock+State:_state [000208] ----------- | \--* LCL_ADDR byref V15 tmp14 [+0] [000209] ----------- \--* LCL_VAR int V17 tmp16 ***** BB24 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct V14 tmp13 [000195] ----------- \--* LCL_VAR struct V15 tmp14 ***** BB24 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000220] ----------- +--* EQ int [000218] N--------U- | +--* LT int [000216] n---------- | | +--* IND int [000215] ----------- | | | \--* FIELD_ADDR byref System.Threading.Lock+State:_state [000214] ----------- | | | \--* LCL_ADDR byref V14 tmp13 [+0] [000217] ----------- | | \--* CNS_INT int 128 [000219] ----------- | \--* CNS_INT int 0 [000181] ----------- \--* CNS_INT int 0 ------------ BB25 [0030] [000..001) -> BB22(1) (always), preds={BB24} succs={BB22} ***** BB25 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 [000185] ----------- arg1 \--* LCL_VAR struct V14 tmp13 ------------ BB26 [0031] [000..001) -> BB27(1) (always), preds={BB23} succs={BB27} ***** BB26 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 [000166] ----------- \--* CNS_INT int 1 ------------ BB27 [0032] [000..001) -> BB22(1) (always), preds={BB24,BB26} succs={BB22} ------------ BB22 [0033] [001..001) -> BB18(1) (always), preds={BB25,BB27} succs={BB18} ------------ BB18 [0027] [001..001) -> BB02(1) (always), preds={BB22} succs={BB02} ------------ BB02 [0012] [006..007) (return), preds={BB10,BB18} succs={} ***** BB02 [0012] STMT00027 ( 0x000[E-] ... ??? ) [000091] DA--------- * STORE_LCL_VAR ref V07 tmp6 [000090] ----------- \--* CNS_INT ref null ***** BB02 [0012] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000092] ----------- \--* CNS_INT byref 0 ***** BB02 [0012] STMT00001 ( 0x006[E-] ... ??? ) [000002] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Merge throw blocks *************** In fgTailMergeThrows Scanning the 3 candidates *** Does not return call [000155] --C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() in BB20 is unique, marking it as canonical *** Does not return call [000099] --C-G------ * CALL void System.ArgumentNullException:Throw(System.String) [000098] ----------- arg0 \--* CNS_STR ref in BB16 is unique, marking it as canonical *************** no throws can be tail merged, sorry *************** Finishing PHASE Merge throw blocks [no changes] *************** Starting PHASE Update flow graph early pass Compacting BB03 into BB01: setting likelihood of BB01 -> BB15 from 1 to 1 *************** In fgDebugCheckBBlist Compacting BB15 into BB01: *************** In fgDebugCheckBBlist Compacting BB14 into BB17: setting likelihood of BB17 -> BB04 from 1 to 1 *************** In fgDebugCheckBBlist Compacting BB02 into BB10: Second block has 1 other incoming edges *************** In fgDebugCheckBBlist Compacting BB19 into BB13: *************** In fgDebugCheckBBlist Compacting BB23 into BB21: *************** In fgDebugCheckBBlist Compacting BB22 into BB27: Second block has 1 other incoming edges setting likelihood of BB27 -> BB18 from 1 to 1 *************** In fgDebugCheckBBlist Compacting BB18 into BB27: setting likelihood of BB27 -> BB10 from 1 to 1 *************** In fgDebugCheckBBlist Compacting BB10 into BB27: Second block has 1 other incoming edges *************** In fgDebugCheckBBlist *************** Finishing PHASE Update flow graph early pass Trees after Update flow graph early pass --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB01 1 [000..001)-> BB17(1) (always) i BB17 [0015] 2 BB01,BB16 1 [000..001)-> BB04(1) (always) i BB04 [0002] 2 BB09,BB17 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB27(0.5) ( cond ) i bwd bwd-src BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare newobj BB13 [0011] 1 BB11 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i nullcheck BB20 [0025] 1 BB13 1 [000..001)-> BB21(1) (always) i BB21 [0026] 2 BB13,BB20 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB21 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i BB25 [0030] 1 BB24 1 [000..001)-> BB27(1) (always) i BB26 [0031] 1 BB21 1 [000..001)-> BB27(1) (always) i BB27 [0032] 4 BB09,BB24,BB25,BB26 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB17(0.5),BB16(0.5) (cond), preds={} succs={BB16,BB17} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null ------------ BB16 [0014] [000..001) -> BB17(1) (always), preds={BB01} succs={BB17} ***** BB16 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --C-G------ * CALL void System.ArgumentNullException:Throw(System.String) [000098] ----------- arg0 \--* CNS_STR ref ------------ BB17 [0015] [000..001) -> BB04(1) (always), preds={BB01,BB16} succs={BB04} ***** BB17 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G------ \--* IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB17 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 ***** BB17 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000106] ---X------- \--* FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 ***** BB17 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000111] ----------- \--* SUB long [000021] ---------U- +--* CAST long <- ulong <- byref [000020] ----------- | \--* LCL_VAR byref V03 tmp2 [000110] ----------- \--* CNS_INT long 4 ------------ BB04 [0002] [000..001) -> BB11(0.5),BB05(0.5) (cond), preds={BB09,BB17} succs={BB05,BB11} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB11(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB11} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB27(0.5) (cond), preds={BB07,BB08} succs={BB27,BB04} ***** BB09 [0007] STMT00024 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000079] ----------- | +--* LCL_VAR int V10 tmp9 [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 ------------ BB11 [0009] [000..001) -> BB13(1),BB12(0) (cond), preds={BB04,BB05} succs={BB12,BB13} ***** BB11 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] nA--G------ * STOREIND int [000113] ----------- +--* LCL_ADDR long V06 tmp5 [+0] [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF ***** BB11 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000124] ----------- +--* EQ int [000122] ----------- | +--* AND int [000117] ----------- | | +--* LCL_VAR int V05 tmp4 [000121] ----------- | | \--* CNS_INT int 0xC000000 [000123] ----------- | \--* CNS_INT int 0x8000000 [000039] ----------- \--* CNS_INT int 0 ------------ BB12 [0010] [000..001) (throw), preds={BB11} succs={} ***** BB12 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC-------- * STORE_LCL_VAR ref V08 tmp7 [000053] --C-------- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H---------- arg0 \--* CNS_INT(h) long 0x420818 class ***** BB12 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 ***** BB12 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 ------------ BB13 [0011] [000..001) -> BB21(0.5),BB20(0.5) (cond), preds={BB11} succs={BB20,BB21} ***** BB13 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA--------- * STORE_LCL_VAR int V12 tmp11 [000042] ----------- \--* LCL_VAR int V06 tmp5 ***** BB13 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] ***** BB13 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 ***** BB13 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000130] n-CXG------ \--* IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000147] ---XG------ \--* ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 [000145] ----------- \--* CNS_INT long 32 ***** BB13 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 ***** BB13 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB20 [0025] [000..001) -> BB21(1) (always), preds={BB13} succs={BB21} ***** BB20 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB21 [0026] [000..001) -> BB26(0.5),BB24(0.5) (cond), preds={BB13,BB20} succs={BB24,BB26} ***** BB21 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 ------------ BB24 [0029] [000..001) -> BB27(0.5),BB25(0.5) (cond), preds={BB21} succs={BB25,BB27} ***** BB24 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00052 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000201] DA-X------- * STORE_LCL_VAR byref V16 tmp15 [000188] ---X------- \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 ***** BB24 [0029] STMT00049 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000192] DA--------- * STORE_LCL_VAR struct V15 tmp14 [000191] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 ***** BB24 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] nA--------- * STOREIND int [000210] ----------- +--* FIELD_ADDR byref System.Threading.Lock+State:_state [000208] ----------- | \--* LCL_ADDR byref V15 tmp14 [+0] [000209] ----------- \--* LCL_VAR int V17 tmp16 ***** BB24 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct V14 tmp13 [000195] ----------- \--* LCL_VAR struct V15 tmp14 ***** BB24 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000220] ----------- +--* EQ int [000218] N--------U- | +--* LT int [000216] n---------- | | +--* IND int [000215] ----------- | | | \--* FIELD_ADDR byref System.Threading.Lock+State:_state [000214] ----------- | | | \--* LCL_ADDR byref V14 tmp13 [+0] [000217] ----------- | | \--* CNS_INT int 128 [000219] ----------- | \--* CNS_INT int 0 [000181] ----------- \--* CNS_INT int 0 ------------ BB25 [0030] [000..001) -> BB27(1) (always), preds={BB24} succs={BB27} ***** BB25 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 [000185] ----------- arg1 \--* LCL_VAR struct V14 tmp13 ------------ BB26 [0031] [000..001) -> BB27(1) (always), preds={BB21} succs={BB27} ***** BB26 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 [000166] ----------- \--* CNS_INT int 1 ------------ BB27 [0032] [000..007) (return), preds={BB09,BB24,BB25,BB26} succs={} ***** BB27 [0032] STMT00027 ( 0x000[E-] ... ??? ) [000091] DA--------- * STORE_LCL_VAR ref V07 tmp6 [000090] ----------- \--* CNS_INT ref null ***** BB27 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000092] ----------- \--* CNS_INT byref 0 ***** BB27 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Morph - Promote Structs lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 ref class-hnd ; V01 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V02 tmp1 int "Inline stloc first use temp" ; V03 tmp2 byref pinned "Inline stloc first use temp" ; V04 tmp3 long "Inline stloc first use temp" ; V05 tmp4 int "Inline stloc first use temp" ; V06 tmp5 int ld-addr-op "Inline ldloca(s) first use temp" ; V07 tmp6 ref class-hnd exact "Inline stloc first use temp" ; V08 tmp7 ref class-hnd exact "NewObj constructor temp" ; V09 tmp8 int ; V10 tmp9 int "Inline stloc first use temp" ; V11 tmp10 long "Inlining Arg" ; V12 tmp11 int "Inlining Arg" ; V13 tmp12 ref "MemoryMarshal.GetArrayDataReference array" ; V14 tmp13 struct ld-addr-op "Inline stloc first use temp" ; V15 tmp14 struct ld-addr-op "NewObj constructor temp" ; V16 tmp15 byref "Inlining Arg" ; V17 tmp16 int "Inlining Arg" struct promotion of V01 is disabled because it has already been marked DNER Notify VM instruction set (AdvSimd) must be supported. Promoting struct local V14 (System.Threading.Lock+State): lvaGrabTemp returning 18 (V18 tmp17) (a long lifetime temp) called for field V14._state (fldOffset=0x0). Promoting struct local V15 (System.Threading.Lock+State): lvaGrabTemp returning 19 (V19 tmp18) (a long lifetime temp) called for field V15._state (fldOffset=0x0). lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 ref class-hnd ; V01 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V02 tmp1 int "Inline stloc first use temp" ; V03 tmp2 byref pinned "Inline stloc first use temp" ; V04 tmp3 long "Inline stloc first use temp" ; V05 tmp4 int "Inline stloc first use temp" ; V06 tmp5 int ld-addr-op "Inline ldloca(s) first use temp" ; V07 tmp6 ref class-hnd exact "Inline stloc first use temp" ; V08 tmp7 ref class-hnd exact "NewObj constructor temp" ; V09 tmp8 int ; V10 tmp9 int "Inline stloc first use temp" ; V11 tmp10 long "Inlining Arg" ; V12 tmp11 int "Inlining Arg" ; V13 tmp12 ref "MemoryMarshal.GetArrayDataReference array" ; V14 tmp13 struct ld-addr-op "Inline stloc first use temp" ; V15 tmp14 struct ld-addr-op "NewObj constructor temp" ; V16 tmp15 byref "Inlining Arg" ; V17 tmp16 int "Inlining Arg" ; V18 tmp17 int "field V14._state (fldOffset=0x0)" P-INDEP ; V19 tmp18 int "field V15._state (fldOffset=0x0)" P-INDEP *************** Finishing PHASE Morph - Promote Structs Trees after Morph - Promote Structs --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB01 1 [000..001)-> BB17(1) (always) i BB17 [0015] 2 BB01,BB16 1 [000..001)-> BB04(1) (always) i BB04 [0002] 2 BB09,BB17 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB27(0.5) ( cond ) i bwd bwd-src BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare newobj BB13 [0011] 1 BB11 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i nullcheck BB20 [0025] 1 BB13 1 [000..001)-> BB21(1) (always) i BB21 [0026] 2 BB13,BB20 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB21 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i BB25 [0030] 1 BB24 1 [000..001)-> BB27(1) (always) i BB26 [0031] 1 BB21 1 [000..001)-> BB27(1) (always) i BB27 [0032] 4 BB09,BB24,BB25,BB26 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB17(0.5),BB16(0.5) (cond), preds={} succs={BB16,BB17} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null ------------ BB16 [0014] [000..001) -> BB17(1) (always), preds={BB01} succs={BB17} ***** BB16 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --C-G------ * CALL void System.ArgumentNullException:Throw(System.String) [000098] ----------- arg0 \--* CNS_STR ref ------------ BB17 [0015] [000..001) -> BB04(1) (always), preds={BB01,BB16} succs={BB04} ***** BB17 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G------ \--* IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB17 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 ***** BB17 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000106] ---X------- \--* FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 ***** BB17 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000111] ----------- \--* SUB long [000021] ---------U- +--* CAST long <- ulong <- byref [000020] ----------- | \--* LCL_VAR byref V03 tmp2 [000110] ----------- \--* CNS_INT long 4 ------------ BB04 [0002] [000..001) -> BB11(0.5),BB05(0.5) (cond), preds={BB09,BB17} succs={BB05,BB11} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB11(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB11} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB27(0.5) (cond), preds={BB07,BB08} succs={BB27,BB04} ***** BB09 [0007] STMT00024 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000079] ----------- | +--* LCL_VAR int V10 tmp9 [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 ------------ BB11 [0009] [000..001) -> BB13(1),BB12(0) (cond), preds={BB04,BB05} succs={BB12,BB13} ***** BB11 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] nA--G------ * STOREIND int [000113] ----------- +--* LCL_ADDR long V06 tmp5 [+0] [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF ***** BB11 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000124] ----------- +--* EQ int [000122] ----------- | +--* AND int [000117] ----------- | | +--* LCL_VAR int V05 tmp4 [000121] ----------- | | \--* CNS_INT int 0xC000000 [000123] ----------- | \--* CNS_INT int 0x8000000 [000039] ----------- \--* CNS_INT int 0 ------------ BB12 [0010] [000..001) (throw), preds={BB11} succs={} ***** BB12 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC-------- * STORE_LCL_VAR ref V08 tmp7 [000053] --C-------- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H---------- arg0 \--* CNS_INT(h) long 0x420818 class ***** BB12 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 ***** BB12 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 ------------ BB13 [0011] [000..001) -> BB21(0.5),BB20(0.5) (cond), preds={BB11} succs={BB20,BB21} ***** BB13 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA--------- * STORE_LCL_VAR int V12 tmp11 [000042] ----------- \--* LCL_VAR int V06 tmp5 ***** BB13 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] ***** BB13 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 ***** BB13 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000130] n-CXG------ \--* IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000147] ---XG------ \--* ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 [000145] ----------- \--* CNS_INT long 32 ***** BB13 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 ***** BB13 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB20 [0025] [000..001) -> BB21(1) (always), preds={BB13} succs={BB21} ***** BB20 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB21 [0026] [000..001) -> BB26(0.5),BB24(0.5) (cond), preds={BB13,BB20} succs={BB24,BB26} ***** BB21 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 ------------ BB24 [0029] [000..001) -> BB27(0.5),BB25(0.5) (cond), preds={BB21} succs={BB25,BB27} ***** BB24 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00052 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000201] DA-X------- * STORE_LCL_VAR byref V16 tmp15 [000188] ---X------- \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 ***** BB24 [0029] STMT00049 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000192] DA--------- * STORE_LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 [000191] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 ***** BB24 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] nA--------- * STOREIND int [000210] ----------- +--* FIELD_ADDR byref System.Threading.Lock+State:_state [000208] ----------- | \--* LCL_ADDR byref V15 tmp14 [+0] | * int field V15._state (fldOffset=0x0) -> V19 tmp18 [000209] ----------- \--* LCL_VAR int V17 tmp16 ***** BB24 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 [000195] ----------- \--* LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 ***** BB24 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000220] ----------- +--* EQ int [000218] N--------U- | +--* LT int [000216] n---------- | | +--* IND int [000215] ----------- | | | \--* FIELD_ADDR byref System.Threading.Lock+State:_state [000214] ----------- | | | \--* LCL_ADDR byref V14 tmp13 [+0] | | | * int field V14._state (fldOffset=0x0) -> V18 tmp17 [000217] ----------- | | \--* CNS_INT int 128 [000219] ----------- | \--* CNS_INT int 0 [000181] ----------- \--* CNS_INT int 0 ------------ BB25 [0030] [000..001) -> BB27(1) (always), preds={BB24} succs={BB27} ***** BB25 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 [000185] ----------- arg1 \--* LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 ------------ BB26 [0031] [000..001) -> BB27(1) (always), preds={BB21} succs={BB27} ***** BB26 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 [000166] ----------- \--* CNS_INT int 1 ------------ BB27 [0032] [000..007) (return), preds={BB09,BB24,BB25,BB26} succs={} ***** BB27 [0032] STMT00027 ( 0x000[E-] ... ??? ) [000091] DA--------- * STORE_LCL_VAR ref V07 tmp6 [000090] ----------- \--* CNS_INT ref null ***** BB27 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000092] ----------- \--* CNS_INT byref 0 ***** BB27 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE DFS blocks and remove dead code 2 *************** Finishing PHASE DFS blocks and remove dead code 2 [no changes] *************** Starting PHASE Morph - Structs/AddrExp Identifying loops in DFS tree with following reverse post order: RPO -> BB [pre, post] 00 -> BB01[0, 17] 01 -> BB16[1, 16] 02 -> BB17[2, 15] 03 -> BB04[3, 14] 04 -> BB05[4, 13] 05 -> BB11[10, 12] 06 -> BB13[12, 11] 07 -> BB20[13, 10] 08 -> BB21[14, 9] 09 -> BB26[17, 8] 10 -> BB24[15, 7] 11 -> BB25[16, 6] 12 -> BB12[11, 5] 13 -> BB06[5, 4] 14 -> BB08[9, 3] 15 -> BB07[6, 2] 16 -> BB09[7, 1] 17 -> BB27[8, 0] BB09 -> BB04 is a backedge BB04 is the header of a DFS loop with 1 back edges Loop has 6 blocks BB04 -> BB11 is an exit edge BB05 -> BB11 is an exit edge BB09 -> BB27 is an exit edge BB17 -> BB04 is an entry edge Added loop L00 with header BB04 Found 1 loops *************** Natural loop graph L00 header: BB04 Members (6): [BB04..BB09] Entry: BB17 -> BB04 Exit: BB04 -> BB11; BB05 -> BB11; BB09 -> BB27 Back: BB09 -> BB04 LocalAddressVisitor visiting statement: STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --C-G------ * CALL void System.ArgumentNullException:Throw(System.String) [000098] ----------- arg0 \--* CNS_STR ref LocalAddressVisitor visiting statement: STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G------ \--* IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] LocalAddressVisitor visiting statement: STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 LocalAddressVisitor visiting statement: STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000106] ---X------- \--* FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 LocalAddressVisitor visiting statement: STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000111] ----------- \--* SUB long [000021] ---------U- +--* CAST long <- ulong <- byref [000020] ----------- | \--* LCL_VAR byref V03 tmp2 [000110] ----------- \--* CNS_INT long 4 LocalAddressVisitor visiting statement: STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 LocalAddressVisitor visiting statement: STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 LocalAddressVisitor visiting statement: STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] nA--G------ * STOREIND int [000113] ----------- +--* LCL_ADDR long V06 tmp5 [+0] [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF LocalAddressVisitor modified statement: STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA--------- * STORE_LCL_VAR int V06 tmp5 [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF LocalAddressVisitor visiting statement: STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000124] ----------- +--* EQ int [000122] ----------- | +--* AND int [000117] ----------- | | +--* LCL_VAR int V05 tmp4 [000121] ----------- | | \--* CNS_INT int 0xC000000 [000123] ----------- | \--* CNS_INT int 0x8000000 [000039] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA--------- * STORE_LCL_VAR int V12 tmp11 [000042] ----------- \--* LCL_VAR int V06 tmp5 LocalAddressVisitor visiting statement: STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] LocalAddressVisitor visiting statement: STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 LocalAddressVisitor visiting statement: STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000130] n-CXG------ \--* IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000147] ---XG------ \--* ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 [000145] ----------- \--* CNS_INT long 32 LocalAddressVisitor visiting statement: STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 LocalAddressVisitor visiting statement: STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 LocalAddressVisitor visiting statement: STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() LocalAddressVisitor visiting statement: STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 [000166] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00052 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000201] DA-X------- * STORE_LCL_VAR byref V16 tmp15 [000188] ---X------- \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 LocalAddressVisitor visiting statement: STMT00049 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000192] DA--------- * STORE_LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 [000191] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 LocalAddressVisitor visiting statement: STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] nA--------- * STOREIND int [000210] ----------- +--* FIELD_ADDR byref System.Threading.Lock+State:_state [000208] ----------- | \--* LCL_ADDR byref V15 tmp14 [+0] | * int field V15._state (fldOffset=0x0) -> V19 tmp18 [000209] ----------- \--* LCL_VAR int V17 tmp16 Replacing the field in promoted struct with local var V19 LocalAddressVisitor modified statement: STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA--------- * STORE_LCL_VAR int V19 tmp18 [000209] ----------- \--* LCL_VAR int V17 tmp16 LocalAddressVisitor visiting statement: STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 [000195] ----------- \--* LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 LocalAddressVisitor visiting statement: STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000220] ----------- +--* EQ int [000218] N--------U- | +--* LT int [000216] n---------- | | +--* IND int [000215] ----------- | | | \--* FIELD_ADDR byref System.Threading.Lock+State:_state [000214] ----------- | | | \--* LCL_ADDR byref V14 tmp13 [+0] | | | * int field V14._state (fldOffset=0x0) -> V18 tmp17 [000217] ----------- | | \--* CNS_INT int 128 [000219] ----------- | \--* CNS_INT int 0 [000181] ----------- \--* CNS_INT int 0 Replacing the field in promoted struct with local var V18 LocalAddressVisitor modified statement: STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000220] ----------- +--* EQ int [000218] N--------U- | +--* LT int [000216] ----------- | | +--* LCL_VAR int V18 tmp17 [000217] ----------- | | \--* CNS_INT int 128 [000219] ----------- | \--* CNS_INT int 0 [000181] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 [000185] ----------- arg1 \--* LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 LocalAddressVisitor visiting statement: STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC-------- * STORE_LCL_VAR ref V08 tmp7 [000053] --C-------- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H---------- arg0 \--* CNS_INT(h) long 0x420818 class LocalAddressVisitor visiting statement: STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 LocalAddressVisitor visiting statement: STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 LocalAddressVisitor visiting statement: STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 LocalAddressVisitor visiting statement: STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 LocalAddressVisitor visiting statement: STMT00024 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 LocalAddressVisitor visiting statement: STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000079] ----------- | +--* LCL_VAR int V10 tmp9 [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 LocalAddressVisitor visiting statement: STMT00027 ( 0x000[E-] ... ??? ) [000091] DA--------- * STORE_LCL_VAR ref V07 tmp6 [000090] ----------- \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00028 ( 0x000[E-] ... ??? ) [000093] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000092] ----------- \--* CNS_INT byref 0 LocalAddressVisitor visiting statement: STMT00001 ( 0x006[E-] ... ??? ) [000002] ----------- * RETURN void *************** Finishing PHASE Morph - Structs/AddrExp Trees after Morph - Structs/AddrExp --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB01 1 [000..001)-> BB17(1) (always) i BB17 [0015] 2 BB01,BB16 1 [000..001)-> BB04(1) (always) i BB04 [0002] 2 BB09,BB17 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB27(0.5) ( cond ) i bwd bwd-src BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare newobj BB13 [0011] 1 BB11 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i nullcheck BB20 [0025] 1 BB13 1 [000..001)-> BB21(1) (always) i BB21 [0026] 2 BB13,BB20 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB21 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i BB25 [0030] 1 BB24 1 [000..001)-> BB27(1) (always) i BB26 [0031] 1 BB21 1 [000..001)-> BB27(1) (always) i BB27 [0032] 4 BB09,BB24,BB25,BB26 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB17(0.5),BB16(0.5) (cond), preds={} succs={BB16,BB17} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null ------------ BB16 [0014] [000..001) -> BB17(1) (always), preds={BB01} succs={BB17} ***** BB16 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --C-G------ * CALL void System.ArgumentNullException:Throw(System.String) [000098] ----------- arg0 \--* CNS_STR ref ------------ BB17 [0015] [000..001) -> BB04(1) (always), preds={BB01,BB16} succs={BB04} ***** BB17 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G------ \--* IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB17 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 ***** BB17 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000106] ---X------- \--* FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 ***** BB17 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000111] ----------- \--* SUB long [000021] ---------U- +--* CAST long <- ulong <- byref [000020] ----------- | \--* LCL_VAR byref V03 tmp2 [000110] ----------- \--* CNS_INT long 4 ------------ BB04 [0002] [000..001) -> BB11(0.5),BB05(0.5) (cond), preds={BB09,BB17} succs={BB05,BB11} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB11(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB11} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB27(0.5) (cond), preds={BB07,BB08} succs={BB27,BB04} ***** BB09 [0007] STMT00024 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000079] ----------- | +--* LCL_VAR int V10 tmp9 [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 ------------ BB11 [0009] [000..001) -> BB13(1),BB12(0) (cond), preds={BB04,BB05} succs={BB12,BB13} ***** BB11 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA--------- * STORE_LCL_VAR int V06 tmp5 [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF ***** BB11 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000124] ----------- +--* EQ int [000122] ----------- | +--* AND int [000117] ----------- | | +--* LCL_VAR int V05 tmp4 [000121] ----------- | | \--* CNS_INT int 0xC000000 [000123] ----------- | \--* CNS_INT int 0x8000000 [000039] ----------- \--* CNS_INT int 0 ------------ BB12 [0010] [000..001) (throw), preds={BB11} succs={} ***** BB12 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC-------- * STORE_LCL_VAR ref V08 tmp7 [000053] --C-------- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H---------- arg0 \--* CNS_INT(h) long 0x420818 class ***** BB12 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 ***** BB12 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 ------------ BB13 [0011] [000..001) -> BB21(0.5),BB20(0.5) (cond), preds={BB11} succs={BB20,BB21} ***** BB13 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA--------- * STORE_LCL_VAR int V12 tmp11 [000042] ----------- \--* LCL_VAR int V06 tmp5 ***** BB13 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] ***** BB13 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 ***** BB13 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000130] n-CXG------ \--* IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000147] ---XG------ \--* ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 [000145] ----------- \--* CNS_INT long 32 ***** BB13 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 ***** BB13 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB20 [0025] [000..001) -> BB21(1) (always), preds={BB13} succs={BB21} ***** BB20 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB21 [0026] [000..001) -> BB26(0.5),BB24(0.5) (cond), preds={BB13,BB20} succs={BB24,BB26} ***** BB21 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 ------------ BB24 [0029] [000..001) -> BB27(0.5),BB25(0.5) (cond), preds={BB21} succs={BB25,BB27} ***** BB24 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00052 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000201] DA-X------- * STORE_LCL_VAR byref V16 tmp15 [000188] ---X------- \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 ***** BB24 [0029] STMT00049 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000192] DA--------- * STORE_LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 [000191] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 ***** BB24 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA--------- * STORE_LCL_VAR int V19 tmp18 [000209] ----------- \--* LCL_VAR int V17 tmp16 ***** BB24 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 [000195] ----------- \--* LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 ***** BB24 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000220] ----------- +--* EQ int [000218] N--------U- | +--* LT int [000216] ----------- | | +--* LCL_VAR int V18 tmp17 [000217] ----------- | | \--* CNS_INT int 128 [000219] ----------- | \--* CNS_INT int 0 [000181] ----------- \--* CNS_INT int 0 ------------ BB25 [0030] [000..001) -> BB27(1) (always), preds={BB24} succs={BB27} ***** BB25 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 [000185] ----------- arg1 \--* LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 ------------ BB26 [0031] [000..001) -> BB27(1) (always), preds={BB21} succs={BB27} ***** BB26 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 [000166] ----------- \--* CNS_INT int 1 ------------ BB27 [0032] [000..007) (return), preds={BB09,BB24,BB25,BB26} succs={} ***** BB27 [0032] STMT00027 ( 0x000[E-] ... ??? ) [000091] DA--------- * STORE_LCL_VAR ref V07 tmp6 [000090] ----------- \--* CNS_INT ref null ***** BB27 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000092] ----------- \--* CNS_INT byref 0 ***** BB27 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Optimize mask conversions Skipping. There are no converts of locals *************** Finishing PHASE Optimize mask conversions [no changes] *************** Starting PHASE Early liveness Local V01 should not be enregistered because: struct size does not match reg size Tracked variable (15 out of 20) table: V00 arg0 [ ref]: refCnt = 2, refCntWtd = 0 V02 tmp1 [ int]: refCnt = 6, refCntWtd = 0 V04 tmp3 [ long]: refCnt = 3, refCntWtd = 0 V05 tmp4 [ int]: refCnt = 10, refCntWtd = 0 V06 tmp5 [ int]: refCnt = 2, refCntWtd = 0 V07 tmp6 [ ref]: refCnt = 9, refCntWtd = 0 V08 tmp7 [ ref]: refCnt = 3, refCntWtd = 0 V09 tmp8 [ int]: refCnt = 3, refCntWtd = 0 V10 tmp9 [ int]: refCnt = 2, refCntWtd = 0 V12 tmp11 [ int]: refCnt = 2, refCntWtd = 0 V13 tmp12 [ ref]: refCnt = 3, refCntWtd = 0 V16 tmp15 [ byref]: refCnt = 2, refCntWtd = 0 V17 tmp16 [ int]: refCnt = 2, refCntWtd = 0 V18 tmp17 [ int]: refCnt = 3, refCntWtd = 0 V19 tmp18 [ int]: refCnt = 3, refCntWtd = 0 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V00} DEF(0)={ } BB16 USE(0)={} DEF(0)={} BB17 USE(1)={V00 } DEF(2)={ V02 V04} BB04 USE(2)={V02 V04 } DEF(1)={ V05} BB05 USE(1)={V05} DEF(0)={ } BB06 USE(1)={V05} DEF(0)={ } BB07 USE(1)={V05 } DEF(1)={ V09} BB08 USE(1)={V05 } DEF(1)={ V09} BB09 USE(3)={V04 V05 V09 } DEF(1)={ V10} BB11 USE(1)={V05 } DEF(1)={ V06} BB12 USE(0)={ } DEF(1)={V08} BB13 USE(2)={V02 V06 } DEF(3)={ V07 V12 V13} BB20 USE(0)={} DEF(0)={} BB21 USE(1)={V07} DEF(0)={ } BB24 USE(1)={V07 } DEF(4)={ V16 V17 V18 V19} BB25 USE(2)={V07 V18} DEF(0)={ } BB26 USE(1)={V07} DEF(0)={ } BB27 USE(0)={ } DEF(1)={V07} ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (1)={V00} OUT(1)={V00} BB16 IN (1)={V00} OUT(1)={V00} BB17 IN (1)={V00 } OUT(2)={ V02 V04} BB04 IN (2)={V02 V04 } OUT(3)={V02 V04 V05} BB05 IN (3)={V02 V04 V05} OUT(3)={V02 V04 V05} BB06 IN (3)={V02 V04 V05} OUT(3)={V02 V04 V05} BB07 IN (3)={V02 V04 V05 } OUT(4)={V02 V04 V05 V09} BB08 IN (3)={V02 V04 V05 } OUT(4)={V02 V04 V05 V09} BB09 IN (4)={V02 V04 V05 V09} OUT(2)={V02 V04 } BB11 IN (2)={V02 V05 } OUT(2)={V02 V06} BB12 IN (0)={} OUT(0)={} BB13 IN (2)={V02 V06 } OUT(1)={ V07} BB20 IN (1)={V07} OUT(1)={V07} BB21 IN (1)={V07} OUT(1)={V07} BB24 IN (1)={V07 } OUT(2)={V07 V18} BB25 IN (2)={V07 V18} OUT(0)={ } BB26 IN (1)={V07} OUT(0)={ } BB27 IN (0)={} OUT(0)={} Store [000192] is dead and has no side effects, removing statement removing useless STMT00049 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000192] DA--------- * STORE_LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 [000191] ----------- \--* CNS_INT int 0 from BB24 Store [000091] is dead and has no side effects, removing statement removing useless STMT00027 ( 0x000[E-] ... ??? ) [000091] DA--------- * STORE_LCL_VAR ref V07 tmp6 [000090] ----------- \--* CNS_INT ref null from BB27 *************** Finishing PHASE Early liveness Trees after Early liveness --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB01 1 [000..001)-> BB17(1) (always) i BB17 [0015] 2 BB01,BB16 1 [000..001)-> BB04(1) (always) i BB04 [0002] 2 BB09,BB17 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB27(0.5) ( cond ) i bwd bwd-src BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare newobj BB13 [0011] 1 BB11 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i nullcheck BB20 [0025] 1 BB13 1 [000..001)-> BB21(1) (always) i BB21 [0026] 2 BB13,BB20 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB21 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i BB25 [0030] 1 BB24 1 [000..001)-> BB27(1) (always) i BB26 [0031] 1 BB21 1 [000..001)-> BB27(1) (always) i BB27 [0032] 4 BB09,BB24,BB25,BB26 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB17(0.5),BB16(0.5) (cond), preds={} succs={BB16,BB17} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null ------------ BB16 [0014] [000..001) -> BB17(1) (always), preds={BB01} succs={BB17} ***** BB16 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --C-G------ * CALL void System.ArgumentNullException:Throw(System.String) [000098] ----------- arg0 \--* CNS_STR ref ------------ BB17 [0015] [000..001) -> BB04(1) (always), preds={BB01,BB16} succs={BB04} ***** BB17 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G------ \--* IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB17 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 (last use) [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 ***** BB17 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000106] ---X------- \--* FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 (last use) ***** BB17 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000111] ----------- \--* SUB long [000021] ---------U- +--* CAST long <- ulong <- byref [000020] ----------- | \--* LCL_VAR byref V03 tmp2 [000110] ----------- \--* CNS_INT long 4 ------------ BB04 [0002] [000..001) -> BB11(0.5),BB05(0.5) (cond), preds={BB09,BB17} succs={BB05,BB11} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB11(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB11} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB27(0.5) (cond), preds={BB07,BB08} succs={BB27,BB04} ***** BB09 [0007] STMT00024 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 (last use) ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000079] ----------- | +--* LCL_VAR int V10 tmp9 (last use) [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 (last use) ------------ BB11 [0009] [000..001) -> BB13(1),BB12(0) (cond), preds={BB04,BB05} succs={BB12,BB13} ***** BB11 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA--------- * STORE_LCL_VAR int V06 tmp5 [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF ***** BB11 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000124] ----------- +--* EQ int [000122] ----------- | +--* AND int [000117] ----------- | | +--* LCL_VAR int V05 tmp4 (last use) [000121] ----------- | | \--* CNS_INT int 0xC000000 [000123] ----------- | \--* CNS_INT int 0x8000000 [000039] ----------- \--* CNS_INT int 0 ------------ BB12 [0010] [000..001) (throw), preds={BB11} succs={} ***** BB12 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC-------- * STORE_LCL_VAR ref V08 tmp7 [000053] --C-------- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H---------- arg0 \--* CNS_INT(h) long 0x420818 class ***** BB12 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 ***** BB12 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 (last use) ------------ BB13 [0011] [000..001) -> BB21(0.5),BB20(0.5) (cond), preds={BB11} succs={BB20,BB21} ***** BB13 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA--------- * STORE_LCL_VAR int V12 tmp11 [000042] ----------- \--* LCL_VAR int V06 tmp5 (last use) ***** BB13 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] ***** BB13 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 ***** BB13 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000130] n-CXG------ \--* IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000147] ---XG------ \--* ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 (last use) [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 (last use) [000145] ----------- \--* CNS_INT long 32 ***** BB13 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 ***** BB13 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 (last use) ------------ BB20 [0025] [000..001) -> BB21(1) (always), preds={BB13} succs={BB21} ***** BB20 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB21 [0026] [000..001) -> BB26(0.5),BB24(0.5) (cond), preds={BB13,BB20} succs={BB24,BB26} ***** BB21 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 ------------ BB24 [0029] [000..001) -> BB27(0.5),BB25(0.5) (cond), preds={BB21} succs={BB25,BB27} ***** BB24 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00052 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000201] DA-X------- * STORE_LCL_VAR byref V16 tmp15 [000188] ---X------- \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 ***** BB24 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000197] ----------- | +--* LCL_VAR byref V16 tmp15 (last use) [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 ***** BB24 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA--------- * STORE_LCL_VAR int V19 tmp18 [000209] ----------- \--* LCL_VAR int V17 tmp16 (last use) ***** BB24 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 [000195] ----------- \--* LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 (last use) ***** BB24 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000220] ----------- +--* EQ int [000218] N--------U- | +--* LT int [000216] ----------- | | +--* LCL_VAR int V18 tmp17 [000217] ----------- | | \--* CNS_INT int 128 [000219] ----------- | \--* CNS_INT int 0 [000181] ----------- \--* CNS_INT int 0 ------------ BB25 [0030] [000..001) -> BB27(1) (always), preds={BB24} succs={BB27} ***** BB25 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 (last use) [000185] ----------- arg1 \--* LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 (last use) ------------ BB26 [0031] [000..001) -> BB27(1) (always), preds={BB21} succs={BB27} ***** BB26 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 (last use) [000166] ----------- \--* CNS_INT int 1 ------------ BB27 [0032] [000..007) (return), preds={BB09,BB24,BB25,BB26} succs={} ***** BB27 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000092] ----------- \--* CNS_INT byref 0 ***** BB27 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Forward Substitution ===> BB01 ===> BB16 ===> BB17 [000007]: next stmt has non-last use [000015]: no next stmt use [000019]: pinned local ===> BB04 [000027]: next stmt has non-last use ===> BB05 ===> BB06 ===> BB07 ===> BB08 ===> BB09 [000077]: [000079] is last use of [000077] (V10) -- fwd subbing [000076]; new next stmt is STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000076] ----------- | +--* LCL_VAR int V09 tmp8 (last use) [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 (last use) removing useless STMT00024 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000077] DA--------- * STORE_LCL_VAR int V10 tmp9 [000076] ----------- \--* LCL_VAR int V09 tmp8 (last use) from BB09 ===> BB11 [000116]: no next stmt use ===> BB12 [000054]: next stmt has non-last use ===> BB13 [000131]: no next stmt use [000138]: next stmt has non-last use [000045]: no next stmt use [000048]: pinned local ===> BB20 ===> BB21 ===> BB24 [000201]: [000197] is last use of [000201] (V16) -- fwd subbing [000188]; new next stmt is STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000188] ---X------- | +--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- | | \--* LCL_VAR ref V07 tmp6 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 removing useless STMT00052 ( INL12 @ 0x000[E-] ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000201] DA-X------- * STORE_LCL_VAR byref V16 tmp15 [000188] ---X------- \--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 from BB24 [000212]: tree to sub has effects [000211]: next stmt has non-last use [000177]: next stmt has non-last use ===> BB25 ===> BB26 ===> BB27 [000093]: pinned local *************** Finishing PHASE Forward Substitution Trees after Forward Substitution --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB01 1 [000..001)-> BB17(1) (always) i BB17 [0015] 2 BB01,BB16 1 [000..001)-> BB04(1) (always) i BB04 [0002] 2 BB09,BB17 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB27(0.5) ( cond ) i bwd bwd-src BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare newobj BB13 [0011] 1 BB11 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i nullcheck BB20 [0025] 1 BB13 1 [000..001)-> BB21(1) (always) i BB21 [0026] 2 BB13,BB20 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB21 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i BB25 [0030] 1 BB24 1 [000..001)-> BB27(1) (always) i BB26 [0031] 1 BB21 1 [000..001)-> BB27(1) (always) i BB27 [0032] 4 BB09,BB24,BB25,BB26 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB17(0.5),BB16(0.5) (cond), preds={} succs={BB16,BB17} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null ------------ BB16 [0014] [000..001) -> BB17(1) (always), preds={BB01} succs={BB17} ***** BB16 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --C-G------ * CALL void System.ArgumentNullException:Throw(System.String) [000098] ----------- arg0 \--* CNS_STR ref ------------ BB17 [0015] [000..001) -> BB04(1) (always), preds={BB01,BB16} succs={BB04} ***** BB17 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G------ \--* IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB17 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 (last use) [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 ***** BB17 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000106] ---X------- \--* FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 (last use) ***** BB17 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000111] ----------- \--* SUB long [000021] ---------U- +--* CAST long <- ulong <- byref [000020] ----------- | \--* LCL_VAR byref V03 tmp2 [000110] ----------- \--* CNS_INT long 4 ------------ BB04 [0002] [000..001) -> BB11(0.5),BB05(0.5) (cond), preds={BB09,BB17} succs={BB05,BB11} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB11(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB11} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB27(0.5) (cond), preds={BB07,BB08} succs={BB27,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000076] ----------- | +--* LCL_VAR int V09 tmp8 (last use) [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 (last use) ------------ BB11 [0009] [000..001) -> BB13(1),BB12(0) (cond), preds={BB04,BB05} succs={BB12,BB13} ***** BB11 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA--------- * STORE_LCL_VAR int V06 tmp5 [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF ***** BB11 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000124] ----------- +--* EQ int [000122] ----------- | +--* AND int [000117] ----------- | | +--* LCL_VAR int V05 tmp4 (last use) [000121] ----------- | | \--* CNS_INT int 0xC000000 [000123] ----------- | \--* CNS_INT int 0x8000000 [000039] ----------- \--* CNS_INT int 0 ------------ BB12 [0010] [000..001) (throw), preds={BB11} succs={} ***** BB12 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC-------- * STORE_LCL_VAR ref V08 tmp7 [000053] --C-------- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H---------- arg0 \--* CNS_INT(h) long 0x420818 class ***** BB12 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 ***** BB12 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 (last use) ------------ BB13 [0011] [000..001) -> BB21(0.5),BB20(0.5) (cond), preds={BB11} succs={BB20,BB21} ***** BB13 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA--------- * STORE_LCL_VAR int V12 tmp11 [000042] ----------- \--* LCL_VAR int V06 tmp5 (last use) ***** BB13 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] ***** BB13 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 ***** BB13 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000130] n-CXG------ \--* IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000147] ---XG------ \--* ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 (last use) [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 (last use) [000145] ----------- \--* CNS_INT long 32 ***** BB13 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 ***** BB13 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 (last use) ------------ BB20 [0025] [000..001) -> BB21(1) (always), preds={BB13} succs={BB21} ***** BB20 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB21 [0026] [000..001) -> BB26(0.5),BB24(0.5) (cond), preds={BB13,BB20} succs={BB24,BB26} ***** BB21 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 ------------ BB24 [0029] [000..001) -> BB27(0.5),BB25(0.5) (cond), preds={BB21} succs={BB25,BB27} ***** BB24 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 ***** BB24 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000188] ---X------- | +--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- | | \--* LCL_VAR ref V07 tmp6 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 ***** BB24 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA--------- * STORE_LCL_VAR int V19 tmp18 [000209] ----------- \--* LCL_VAR int V17 tmp16 (last use) ***** BB24 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000177] DAC-------- * STORE_LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 [000195] ----------- \--* LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 (last use) ***** BB24 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000220] ----------- +--* EQ int [000218] N--------U- | +--* LT int [000216] ----------- | | +--* LCL_VAR int V18 tmp17 [000217] ----------- | | \--* CNS_INT int 128 [000219] ----------- | \--* CNS_INT int 0 [000181] ----------- \--* CNS_INT int 0 ------------ BB25 [0030] [000..001) -> BB27(1) (always), preds={BB24} succs={BB27} ***** BB25 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 (last use) [000185] ----------- arg1 \--* LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 (last use) ------------ BB26 [0031] [000..001) -> BB27(1) (always), preds={BB21} succs={BB27} ***** BB26 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 (last use) [000166] ----------- \--* CNS_INT int 1 ------------ BB27 [0032] [000..007) (return), preds={BB09,BB24,BB25,BB26} succs={} ***** BB27 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000092] ----------- \--* CNS_INT byref 0 ***** BB27 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Physical promotion *************** Finishing PHASE Physical promotion [no changes] *************** Starting PHASE Identify candidates for implicit byref copy omission *************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes] *************** Starting PHASE Morph - ByRefs *************** Finishing PHASE Morph - ByRefs [no changes] *************** Starting PHASE Morph - Global Morphing BB01 BB01 ineligible for cross-block Assertions in: #NA fgMorphTree BB01, STMT00029 (before) [000097] ----------- * JTRUE void [000096] ----------- \--* NE int [000000] ----------- +--* LCL_VAR ref V00 arg0 [000095] ----------- \--* CNS_INT ref null GenTreeNode creates assertion: [000097] -----+----- * JTRUE void In BB01 New Local Constant Assertion: V00 != null, index = #01 GenTreeNode creates assertion: [000097] -----+----- * JTRUE void In BB01 New Local Constant Assertion: V00 == null, index = #02 Morphing BB16 Using `if false` assertions from pred BB01 Assertions in: #02 fgMorphTree BB16, STMT00030 (before) [000099] --C-G------ * CALL void System.ArgumentNullException:Throw(System.String) [000098] ----------- arg0 \--* CNS_STR ref Initializing arg info for 99.CALL: Argument 0 ABI info: [00..08) reg x0 Args for call [000099] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000098].CNS_STR ref (By value), 1 reg: x0] Morphing args for 99.CALL: Sorting the arguments: Deferred argument ('x0'): [000222] H----+----- * CNS_INT(h) ref '"obj"' Moved to late list Register placement order: x0 Args for [000099].CALL after fgMorphArgs: CallArg[[000222].CNS_INT ref (By value), 1 reg: x0, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB16, STMT00030 (after) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' Removing trees after no-return call [000099] New final statement: STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' Converting BB16 to BBJ_THROW Morphing BB17 Using `if true` assertions from pred BB01 Assertions in: #01 fgMorphTree BB17, STMT00004 (before) [000007] DAC-------- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G------ \--* IND int [000103] --C-G------ \--* ADD byref [000101] H-C-G------ +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] ----------- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] Initializing arg info for 101.CALL: Args for call [000101] CALL after AddFinalArgsAndDetermineABIInfo: Morphing args for 101.CALL: Args for [000101].CALL after fgMorphArgs: OutgoingArgsStackSize is 0 fgMorphTree BB17, STMT00005 (before) [000015] DA--------- * STORE_LCL_VAR int V02 tmp1 [000014] ----------- \--* OR int [000008] ----------- +--* LCL_VAR int V02 tmp1 [000013] ----------- \--* RSH int [000011] ----------- +--* SUB int [000009] ----------- | +--* LCL_VAR int V02 tmp1 (last use) [000010] ----------- | \--* CNS_INT int 1 [000012] ----------- \--* CNS_INT int 31 fgMorphTree BB17, STMT00005 (after) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 [000014] -----+----- \--* OR int [000008] -----+----- +--* LCL_VAR int V02 tmp1 [000013] -----+----- \--* RSH int [000011] -----+----- +--* ADD int [000009] -----+----- | +--* LCL_VAR int V02 tmp1 (last use) [000010] -----+----- | \--* CNS_INT int -1 [000012] -----+----- \--* CNS_INT int 31 fgMorphTree BB17, STMT00007 (before) [000019] DAC-------- * STORE_LCL_VAR byref V03 tmp2 [000106] ---X------- \--* FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 (last use) Before explicit null check morphing: [000106] ---X------- * FIELD_ADDR byref System.Object:m_pEEType [000016] ----------- \--* LCL_VAR ref V00 arg0 (last use) After adding explicit null check: [000226] ---X-O----- * COMMA ref [000224] ---X-O----- +--* NULLCHECK byte [000223] ----------- | \--* LCL_VAR ref V00 arg0 [000225] ----------- \--* LCL_VAR ref V00 arg0 Final value of Compiler::fgMorphFieldAddr after morphing: [000226] ---X-+-N--- * COMMA ref [000224] ---X-+----- +--* NULLCHECK byte [000223] -----+----- | \--* LCL_VAR ref V00 arg0 [000225] -----+----- \--* LCL_VAR ref V00 arg0 fgMorphTree BB17, STMT00007 (after) [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 [000226] ---X-+-N--- \--* COMMA ref [000224] ---X-+----- +--* NULLCHECK byte [000223] -----+----- | \--* LCL_VAR ref V00 arg0 [000225] -----+----- \--* LCL_VAR ref V00 arg0 fgMorphTree BB17, STMT00009 (before) [000024] DAC-------- * STORE_LCL_VAR long V04 tmp3 [000111] ----------- \--* SUB long [000021] ---------U- +--* CAST long <- ulong <- byref [000020] ----------- | \--* LCL_VAR byref V03 tmp2 [000110] ----------- \--* CNS_INT long 4 lvaGrabTemp returning 20 (V20 tmp19) called for Cast away GC. fgMorphTree BB17, STMT00009 (after) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 [000111] -A---+----- \--* ADD long [000230] -A---+----- +--* COMMA long [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 [000228] -----+----- | \--* LCL_VAR long V20 tmp19 [000110] -----+----- \--* CNS_INT long -4 Morphing BB04 BB04 pred BB09 not processed; clearing assertions in Assertions in: #NA fgMorphTree BB04, STMT00010 (before) [000027] DA-XG------ * STORE_LCL_VAR int V05 tmp4 [000026] ---XG------ \--* IND int [000025] ----------- \--* LCL_VAR long V04 tmp3 fgMorphTree BB04, STMT00011 (before) [000034] ----------- * JTRUE void [000033] N--------U- \--* NE int [000031] ----------- +--* CAST int <- ushort <- int [000028] ----------- | \--* LCL_VAR int V05 tmp4 [000032] ----------- \--* LCL_VAR int V02 tmp1 Morphing BB05 Using `if false` assertions from pred BB04 Assertions in: #NA fgMorphTree BB05, STMT00021 (before) [000064] ----------- * JTRUE void [000063] ----------- \--* NE int [000061] ----------- +--* AND int [000059] ----------- | +--* LCL_VAR int V05 tmp4 [000060] ----------- | \--* CNS_INT int 0x8000000 [000062] ----------- \--* CNS_INT int 0 Morphing BB11 Using `if true` assertions from pred BB04 Using `if true` assertions from pred BB05 Assertions in: #NA fgMorphTree BB11, STMT00031 (before) [000116] DA--------- * STORE_LCL_VAR int V06 tmp5 [000115] ----------- \--* AND int [000035] ----------- +--* LCL_VAR int V05 tmp4 [000114] ----------- \--* CNS_INT int 0x3FFFFFF fgMorphTree BB11, STMT00013 (before) [000041] --C-------- * JTRUE void [000040] --C-------- \--* NE int [000124] ----------- +--* EQ int [000122] ----------- | +--* AND int [000117] ----------- | | +--* LCL_VAR int V05 tmp4 (last use) [000121] ----------- | | \--* CNS_INT int 0xC000000 [000123] ----------- | \--* CNS_INT int 0x8000000 [000039] ----------- \--* CNS_INT int 0 fgMorphTree BB11, STMT00013 (after) [000041] -----+----- * JTRUE void [000124] J----+-N--- \--* EQ int [000122] -----+----- +--* AND int [000117] -----+----- | +--* LCL_VAR int V05 tmp4 (last use) [000121] -----+----- | \--* CNS_INT int 0xC000000 [000123] -----+----- \--* CNS_INT int 0x8000000 Morphing BB13 Using `if true` assertions from pred BB11 Assertions in: #NA fgMorphTree BB13, STMT00034 (before) [000131] DA--------- * STORE_LCL_VAR int V12 tmp11 [000042] ----------- \--* LCL_VAR int V06 tmp5 (last use) GenTreeNode creates assertion: [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 In BB13 New Local Copy Assertion: V12 == V06, index = #03 fgMorphTree BB13, STMT00035 (before) [000138] DA-XG------ * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG------ \--* IND ref [000136] ----------- \--* ADD long [000134] #---------- +--* IND long [000133] H---------- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] ----------- \--* CNS_INT long 16 Fseq[s_entries] fgMorphTree BB13, STMT00036 (before) [000141] ---X------- * NULLCHECK byte [000140] ----------- \--* LCL_VAR ref V13 tmp12 GenTreeNode creates assertion: [000141] ---X-+----- * NULLCHECK byte In BB13 New Local Constant Assertion: V13 != null, index = #04 fgMorphTree BB13, STMT00015 (before) [000045] DAC-------- * STORE_LCL_VAR ref V07 tmp6 [000130] n-CXG------ \--* IND ref [000129] --CX------- \--* FIELD_ADDR byref System.Threading.SyncTable+Entry:Lock [000147] ---XG------ \--* ADD byref [000143] ---XG------ +--* INDEX_ADDR byref System.Threading.SyncTable+Entry[] [000139] ----------- | +--* LCL_VAR ref V13 tmp12 (last use) [000142] ----------- | \--* CNS_INT long 0 [000146] ----------- \--* MUL long [000144] ----------- +--* CAST long <- int [000126] ----------- | \--* LCL_VAR int V12 tmp11 (last use) [000145] ----------- \--* CNS_INT long 32 fgMorphIndexAddr (before remorph): [000236] ----------- * ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] ----------- \--* ADD byref [000139] ----------- +--* LCL_VAR ref V13 tmp12 (last use) [000234] ----------- \--* ADD long [000232] ----------- +--* MUL long [000142] ----------- | +--* CNS_INT long 0 [000231] -------N--- | \--* CNS_INT long 32 [000233] ----------- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [000232] ----------- * MUL long [000142] -----+----- +--* CNS_INT long 0 [000231] -----+-N--- \--* CNS_INT long 32 Bashed to long constant: [000232] ----------- * CNS_INT long 0 Folding long operator with constant nodes into a constant: [000234] ----------- * ADD long [000232] -----+----- +--* CNS_INT long 0 [000233] -----+----- \--* CNS_INT long 16 Bashed to long constant: [000234] ----------- * CNS_INT long 16 fgMorphIndexAddr (after remorph): [000236] -----+----- * ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- \--* ADD byref [000139] -----+----- +--* LCL_VAR ref V13 tmp12 (last use) [000234] -----+----- \--* CNS_INT long 16 Assertion prop in BB13: Copy Assertion: V12 == V06, index = #03 [000126] ----------- * LCL_VAR int V06 tmp5 Final value of Compiler::fgMorphFieldAddr after morphing: [000147] ----G+----- * ADD byref [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- | \--* ADD byref [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 (last use) [000234] -----+----- | \--* CNS_INT long 16 [000146] -----+----- \--* LSH long [000144] -----+----- +--* CAST long <- int [000126] -----+----- | \--* LCL_VAR int V06 tmp5 [000145] -----+----- \--* CNS_INT long 5 fgMorphTree BB13, STMT00015 (after) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 [000130] ---XG+----- \--* IND ref [000147] ----G+----- \--* ADD byref [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- | \--* ADD byref [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 (last use) [000234] -----+----- | \--* CNS_INT long 16 [000146] -----+----- \--* LSH long [000144] -----+----- +--* CAST long <- int [000126] -----+----- | \--* LCL_VAR int V06 tmp5 [000145] -----+----- \--* CNS_INT long 5 fgMorphTree BB13, STMT00016 (before) [000048] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000047] ----------- \--* CNS_INT long 0 GenTreeNode creates assertion: [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 In BB13 New Local Constant Assertion: V03 == 0, index = #05 fgMorphTree BB13, STMT00037 (before) [000152] ---XG------ * JTRUE void [000151] ---XG------ \--* EQ int [000150] n--XG------ +--* IND int [000149] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000049] ----------- | \--* LCL_VAR ref V07 tmp6 [000050] ----------- \--* LCL_VAR int V02 tmp1 (last use) Final value of Compiler::fgMorphFieldAddr after morphing: [000238] -----+----- * ADD byref [000049] -----+----- +--* LCL_VAR ref V07 tmp6 [000237] -----+----- \--* CNS_INT long 16 Fseq[_owningThreadId] GenTreeNode creates assertion: [000150] ---XG+----- * IND int In BB13 New Local Constant Assertion: V07 != null, index = #06 fgMorphTree BB13, STMT00037 (after) [000152] ---XG+----- * JTRUE void [000151] J--XG+-N--- \--* EQ int [000150] ---XG+----- +--* IND int [000238] -----+----- | \--* ADD byref [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000050] -----+----- \--* LCL_VAR int V02 tmp1 (last use) Morphing BB20 Using `if false` assertions from pred BB13 Assertions in: #03 #04 #05 #06 fgMorphTree BB20, STMT00039 (before) [000155] --C-G------ * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() Initializing arg info for 155.CALL: Args for call [000155] CALL after AddFinalArgsAndDetermineABIInfo: Morphing args for 155.CALL: Args for [000155].CALL after fgMorphArgs: OutgoingArgsStackSize is 0 Removing trees after no-return call [000155] New final statement: STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() Converting BB20 to BBJ_THROW Morphing BB21 Using `if true` assertions from pred BB13 Assertions in: #03 #04 #05 #06 fgMorphTree BB21, STMT00040 (before) [000161] ---XG------ * JTRUE void [000160] ---XG------ \--* NE int [000158] n--XG------ +--* IND int [000157] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000153] ----------- | \--* LCL_VAR ref V07 tmp6 [000159] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphFieldAddr after morphing: [000240] -----+----- * ADD byref [000153] -----+----- +--* LCL_VAR ref V07 tmp6 [000239] -----+----- \--* CNS_INT long 24 Fseq[_recursionCount] fgMorphTree BB21, STMT00040 (after) [000161] ---XG+----- * JTRUE void [000160] J--XG+-N--- \--* NE int [000158] ---XG+----- +--* IND int [000240] -----+----- | \--* ADD byref [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000159] -----+----- \--* CNS_INT int 0 Morphing BB26 Using `if true` assertions from pred BB21 Assertions in: #03 #04 #05 #06 fgMorphTree BB26, STMT00041 (before) [000169] nA-XG------ * STOREIND int [000168] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000162] ----------- | \--* LCL_VAR ref V07 tmp6 [000167] ---XG------ \--* SUB int [000165] n--XG------ +--* IND int [000164] ---X------- | \--* FIELD_ADDR byref System.Threading.Lock:_recursionCount [000163] ----------- | \--* LCL_VAR ref V07 tmp6 (last use) [000166] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphFieldAddr after morphing: [000242] -----+----- * ADD byref [000162] -----+----- +--* LCL_VAR ref V07 tmp6 [000241] -----+----- \--* CNS_INT long 24 Fseq[_recursionCount] Final value of Compiler::fgMorphFieldAddr after morphing: [000244] -----+----- * ADD byref [000163] -----+----- +--* LCL_VAR ref V07 tmp6 (last use) [000243] -----+----- \--* CNS_INT long 24 Fseq[_recursionCount] fgMorphTree BB26, STMT00041 (after) [000169] -A-XG+----- * STOREIND int [000242] -----+----- +--* ADD byref [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000167] ---XG+----- \--* ADD int [000165] ---XG+----- +--* IND int [000244] -----+----- | \--* ADD byref [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 (last use) [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000166] -----+----- \--* CNS_INT int -1 Morphing BB24 Using `if false` assertions from pred BB21 Assertions in: #03 #04 #05 #06 fgMorphTree BB24, STMT00042 (before) [000173] nA-XG------ * STOREIND int [000172] ---X------- +--* FIELD_ADDR byref System.Threading.Lock:_owningThreadId [000170] ----------- | \--* LCL_VAR ref V07 tmp6 [000171] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphFieldAddr after morphing: [000246] -----+----- * ADD byref [000170] -----+----- +--* LCL_VAR ref V07 tmp6 [000245] -----+----- \--* CNS_INT long 16 Fseq[_owningThreadId] fgMorphTree BB24, STMT00042 (after) [000173] -A-XG+----- * STOREIND int [000246] -----+----- +--* ADD byref [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000171] -----+----- \--* CNS_INT int 0 fgMorphTree BB24, STMT00054 (before) [000212] DA-XG------ * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG------ \--* ADD int [000204] -A-XG------ +--* XADD int [000188] ---X------- | +--* FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- | | \--* LCL_VAR ref V07 tmp6 [000203] ----------- | \--* CNS_INT int -1 [000205] ----------- \--* CNS_INT int -1 Before explicit null check morphing: [000188] ---X------- * FIELD_ADDR byref System.Threading.Lock:_state [000174] ----------- \--* LCL_VAR ref V07 tmp6 After adding explicit null check: [000252] ---X-O----- * COMMA byref [000248] ---X-O----- +--* NULLCHECK byte [000247] ----------- | \--* LCL_VAR ref V07 tmp6 [000251] -----O----- \--* ADD byref [000249] ----------- +--* LCL_VAR ref V07 tmp6 [000250] ----------- \--* CNS_INT long 20 Fseq[_state] Non-null prop for index #06 in BB24: [000248] ---X-O----- * NULLCHECK byte NULLCHECK on [000247] will always succeed Final value of Compiler::fgMorphFieldAddr after morphing: [000251] -----+----- * ADD byref [000249] -----+----- +--* LCL_VAR ref V07 tmp6 [000250] -----+----- \--* CNS_INT long 20 Fseq[_state] fgMorphTree BB24, STMT00054 (after) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG+----- \--* ADD int [000204] -A-XG+----- +--* XADD int [000251] -----+----- | +--* ADD byref [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] [000203] -----+----- | \--* CNS_INT int -1 [000205] -----+----- \--* CNS_INT int -1 fgMorphTree BB24, STMT00053 (before) [000211] DA--------- * STORE_LCL_VAR int V19 tmp18 [000209] ----------- \--* LCL_VAR int V17 tmp16 (last use) GenTreeNode creates assertion: [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 In BB24 New Local Copy Assertion: V19 == V17, index = #07 fgMorphTree BB24, STMT00044 (before) [000177] DAC-------- * STORE_LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 [000195] ----------- \--* LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 (last use) MorphCopyBlock: PrepareDst for [000177] have found a local var V14. GenTreeNode creates assertion: [000177] DA--------- * STORE_LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 In BB24 New Local Copy Assertion: V14 == V15, index = #08 block store to morph: [000177] DA--------- * STORE_LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 [000195] -----+----- \--* LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 (last use) (m_dstDoFldStore=true) (m_srcDoFldStore=true) using field by field stores. GenTreeNode creates assertion: [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 In BB24 New Local Copy Assertion: V18 == V19, index = #09 MorphCopyBlock (after): [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 [000253] -----+----- \--* LCL_VAR int V19 tmp18 fgMorphTree BB24, STMT00044 (after) [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 [000253] -----+----- \--* LCL_VAR int V19 tmp18 fgMorphTree BB24, STMT00046 (before) [000183] --C-------- * JTRUE void [000182] --C-------- \--* EQ int [000220] ----------- +--* EQ int [000218] N--------U- | +--* LT int [000216] ----------- | | +--* LCL_VAR int V18 tmp17 [000217] ----------- | | \--* CNS_INT int 128 [000219] ----------- | \--* CNS_INT int 0 [000181] ----------- \--* CNS_INT int 0 Assertion prop in BB24: Copy Assertion: V18 == V19, index = #09 [000216] ----------- * LCL_VAR int V19 tmp18 Assertion prop in BB24: Copy Assertion: V19 == V17, index = #07 [000216] ----------- * LCL_VAR int V17 tmp16 fgMorphTree BB24, STMT00046 (after) [000183] -----+----- * JTRUE void [000218] N----+-N-U- \--* LT int [000216] -----+----- +--* LCL_VAR int V17 tmp16 [000217] -----+----- \--* CNS_INT int 128 Morphing BB25 Using `if false` assertions from pred BB24 Assertions in: #03 #04 #05 #06 #07 #08 #09 fgMorphTree BB25, STMT00047 (before) [000186] --C-G------ * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] ----------- this +--* LCL_VAR ref V07 tmp6 (last use) [000185] ----------- arg1 \--* LCL_VAR struct(P) V14 tmp13 * int field V14._state (fldOffset=0x0) -> V18 tmp17 (last use) Initializing arg info for 186.CALL: Argument 0 ABI info: [00..08) reg x0 Argument 1 ABI info: [00..04) reg x1 Args for call [000186] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000184].LCL_VAR ref (By value), 1 reg: x0, wellKnown[ThisPointer]] CallArg[[000185].LCL_VAR struct (By value), 1 reg: x1] Morphing args for 186.CALL: Assertion prop in BB25: Copy Assertion: V14 == V15, index = #08 [000185] ----------- * LCL_VAR struct(P) V15 tmp14 * int field V15._state (fldOffset=0x0) -> V19 tmp18 Sorting the arguments: Deferred argument ('x0'): [000184] -----+----- * LCL_VAR ref V07 tmp6 (last use) Moved to late list Deferred argument ('x1'): [000185] -----+----- * LCL_VAR int V19 tmp18 Moved to late list Register placement order: x0 x1 Args for [000186].CALL after fgMorphArgs: CallArg[[000184].LCL_VAR ref (By value), 1 reg: x0, isLate, processed, wellKnown[ThisPointer]] CallArg[[000185].LCL_VAR struct (By value), 1 reg: x1, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB25, STMT00047 (after) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 (last use) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 Morphing BB12 Using `if false` assertions from pred BB11 Assertions in: #NA fgMorphTree BB12, STMT00018 (before) [000054] DAC-------- * STORE_LCL_VAR ref V08 tmp7 [000053] --C-------- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H---------- arg0 \--* CNS_INT(h) long 0x420818 class Initializing arg info for 53.CALL: Argument 0 ABI info: [00..08) reg x0 Args for call [000053] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000052].CNS_INT long (By value), 1 reg: x0] Morphing args for 53.CALL: Sorting the arguments: Deferred argument ('x0'): [000052] H----+----- * CNS_INT(h) long 0x420818 class Moved to late list Register placement order: x0 Args for [000053].CALL after fgMorphArgs: CallArg[[000052].CNS_INT long (By value), 1 reg: x0, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB12, STMT00019 (before) [000056] --C-G------ * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] ----------- this \--* LCL_VAR ref V08 tmp7 Initializing arg info for 56.CALL: Argument 0 ABI info: [00..08) reg x0 Args for call [000056] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000055].LCL_VAR ref (By value), 1 reg: x0, wellKnown[ThisPointer]] Morphing args for 56.CALL: Sorting the arguments: Deferred argument ('x0'): [000055] -----+----- * LCL_VAR ref V08 tmp7 Moved to late list Register placement order: x0 Args for [000056].CALL after fgMorphArgs: CallArg[[000055].LCL_VAR ref (By value), 1 reg: x0, isLate, processed, wellKnown[ThisPointer]] OutgoingArgsStackSize is 0 fgMorphTree BB12, STMT00020 (before) [000058] --CXG------ * CALL help void CORINFO_HELP_THROW [000057] ----------- arg0 \--* LCL_VAR ref V08 tmp7 (last use) Initializing arg info for 58.CALL: Argument 0 ABI info: [00..08) reg x0 Args for call [000058] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000057].LCL_VAR ref (By value), 1 reg: x0] Morphing args for 58.CALL: Sorting the arguments: Deferred argument ('x0'): [000057] -----+----- * LCL_VAR ref V08 tmp7 (last use) Moved to late list Register placement order: x0 Args for [000058].CALL after fgMorphArgs: CallArg[[000057].LCL_VAR ref (By value), 1 reg: x0, isLate, processed] OutgoingArgsStackSize is 0 Removing trees after no-return call [000058] New final statement: STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 (last use) Converting BB12 to BBJ_THROW Morphing BB06 Using `if false` assertions from pred BB05 Assertions in: #NA fgMorphTree BB06, STMT00022 (before) [000070] ----------- * JTRUE void [000069] ----------- \--* NE int [000067] ----------- +--* AND int [000065] ----------- | +--* LCL_VAR int V05 tmp4 [000066] ----------- | \--* CNS_INT int 0x3F0000 [000068] ----------- \--* CNS_INT int 0 Morphing BB08 Using `if true` assertions from pred BB06 Assertions in: #NA fgMorphTree BB08, STMT00023 (before) [000074] DA--------- * STORE_LCL_VAR int V09 tmp8 [000073] ----------- \--* SUB int [000071] ----------- +--* LCL_VAR int V05 tmp4 [000072] ----------- \--* CNS_INT int 0x10000 fgMorphTree BB08, STMT00023 (after) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000073] -----+----- \--* ADD int [000071] -----+----- +--* LCL_VAR int V05 tmp4 [000072] -----+----- \--* CNS_INT int -0x10000 Morphing BB07 Using `if false` assertions from pred BB06 Assertions in: #NA fgMorphTree BB07, STMT00026 (before) [000088] DA--------- * STORE_LCL_VAR int V09 tmp8 [000087] ----------- \--* AND int [000085] ----------- +--* LCL_VAR int V05 tmp4 [000086] ----------- \--* CNS_INT int -0x10000 Morphing BB09 Assertions in: #NA fgMorphTree BB09, STMT00025 (before) [000084] -A-XG------ * JTRUE void [000083] NA-XG----U- \--* NE int [000081] -A-XG------ +--* CMPXCHG int [000078] -------N--- | +--* LCL_VAR long V04 tmp3 [000076] ----------- | +--* LCL_VAR int V09 tmp8 (last use) [000080] ----------- | \--* LCL_VAR int V05 tmp4 [000082] ----------- \--* LCL_VAR int V05 tmp4 (last use) Morphing BB27 Using `if false` assertions from pred BB09 Using `if true` assertions from pred BB24 Assertions in: #NA fgMorphTree BB27, STMT00028 (before) [000093] DA--------- * STORE_LCL_VAR byref V03 tmp2 [000092] ----------- \--* CNS_INT byref 0 GenTreeNode creates assertion: [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 In BB27 New Local Constant Assertion: V03 == 0, index = #05 fgMorphTree BB27, STMT00001 (before) [000002] ----------- * RETURN void morph assertion stats: 64 table size, 9 assertions, 0 dropped *************** Finishing PHASE Morph - Global Trees after Morph - Global --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB17 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB17 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB27(0.5) ( cond ) i bwd bwd-src BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare hascall gcsafe newobj BB13 [0011] 1 BB11 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i nullcheck BB20 [0025] 1 BB13 1 [000..001) (throw ) i hascall gcsafe BB21 [0026] 1 BB13 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB21 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i nullcheck BB25 [0030] 1 BB24 1 [000..001)-> BB27(1) (always) i hascall gcsafe BB26 [0031] 1 BB21 1 [000..001)-> BB27(1) (always) i BB27 [0032] 4 BB09,BB24,BB25,BB26 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB17(0.5),BB16(0.5) (cond), preds={} succs={BB16,BB17} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] -----+----- * JTRUE void [000096] J----+-N--- \--* NE int [000000] -----+----- +--* LCL_VAR ref V00 arg0 [000095] -----+----- \--* CNS_INT ref null ------------ BB16 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB16 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' ------------ BB17 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB17 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G+----- \--* IND int [000103] --C-G+----- \--* ADD byref [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB17 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 [000014] -----+----- \--* OR int [000008] -----+----- +--* LCL_VAR int V02 tmp1 [000013] -----+----- \--* RSH int [000011] -----+----- +--* ADD int [000009] -----+----- | +--* LCL_VAR int V02 tmp1 (last use) [000010] -----+----- | \--* CNS_INT int -1 [000012] -----+----- \--* CNS_INT int 31 ***** BB17 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 [000226] ---X-+-N--- \--* COMMA ref [000224] ---X-+----- +--* NULLCHECK byte [000223] -----+----- | \--* LCL_VAR ref V00 arg0 [000225] -----+----- \--* LCL_VAR ref V00 arg0 ***** BB17 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 [000111] -A---+----- \--* ADD long [000230] -A---+----- +--* COMMA long [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 [000228] -----+----- | \--* LCL_VAR long V20 tmp19 [000110] -----+----- \--* CNS_INT long -4 ------------ BB04 [0002] [000..001) -> BB11(0.5),BB05(0.5) (cond), preds={BB09,BB17} succs={BB05,BB11} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 [000026] ---XG+----- \--* IND int [000025] -----+----- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] -----+----- * JTRUE void [000033] N----+-N-U- \--* NE int [000031] -----+----- +--* CAST int <- ushort <- int [000028] -----+----- | \--* LCL_VAR int V05 tmp4 [000032] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB11(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB11} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] -----+----- * JTRUE void [000063] J----+-N--- \--* NE int [000061] -----+----- +--* AND int [000059] -----+----- | +--* LCL_VAR int V05 tmp4 [000060] -----+----- | \--* CNS_INT int 0x8000000 [000062] -----+----- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] -----+----- * JTRUE void [000069] J----+-N--- \--* NE int [000067] -----+----- +--* AND int [000065] -----+----- | +--* LCL_VAR int V05 tmp4 [000066] -----+----- | \--* CNS_INT int 0x3F0000 [000068] -----+----- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000087] -----+----- \--* AND int [000085] -----+----- +--* LCL_VAR int V05 tmp4 [000086] -----+----- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000073] -----+----- \--* ADD int [000071] -----+----- +--* LCL_VAR int V05 tmp4 [000072] -----+----- \--* CNS_INT int -0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB27(0.5) (cond), preds={BB07,BB08} succs={BB27,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG+----- * JTRUE void [000083] NA-XG+-N-U- \--* NE int [000081] -A-XG+----- +--* CMPXCHG int [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 [000076] -----+----- | +--* LCL_VAR int V09 tmp8 (last use) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 [000082] -----+----- \--* LCL_VAR int V05 tmp4 (last use) ------------ BB11 [0009] [000..001) -> BB13(1),BB12(0) (cond), preds={BB04,BB05} succs={BB12,BB13} ***** BB11 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 [000115] -----+----- \--* AND int [000035] -----+----- +--* LCL_VAR int V05 tmp4 [000114] -----+----- \--* CNS_INT int 0x3FFFFFF ***** BB11 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] -----+----- * JTRUE void [000124] J----+-N--- \--* EQ int [000122] -----+----- +--* AND int [000117] -----+----- | +--* LCL_VAR int V05 tmp4 (last use) [000121] -----+----- | \--* CNS_INT int 0xC000000 [000123] -----+----- \--* CNS_INT int 0x8000000 ------------ BB12 [0010] [000..001) (throw), preds={BB11} succs={} ***** BB12 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class ***** BB12 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 ***** BB12 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 (last use) ------------ BB13 [0011] [000..001) -> BB21(0.5),BB20(0.5) (cond), preds={BB11} succs={BB20,BB21} ***** BB13 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 [000042] -----+----- \--* LCL_VAR int V06 tmp5 (last use) ***** BB13 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG+----- \--* IND ref [000136] -----+----- \--* ADD long [000134] #----+----- +--* IND long [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] ***** BB13 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X-+----- * NULLCHECK byte [000140] -----+----- \--* LCL_VAR ref V13 tmp12 ***** BB13 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 [000130] ---XG+----- \--* IND ref [000147] ----G+----- \--* ADD byref [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- | \--* ADD byref [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 (last use) [000234] -----+----- | \--* CNS_INT long 16 [000146] -----+----- \--* LSH long [000144] -----+----- +--* CAST long <- int [000126] -----+----- | \--* LCL_VAR int V06 tmp5 [000145] -----+----- \--* CNS_INT long 5 ***** BB13 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000047] -----+----- \--* CNS_INT long 0 ***** BB13 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG+----- * JTRUE void [000151] J--XG+-N--- \--* EQ int [000150] ---XG+----- +--* IND int [000238] -----+----- | \--* ADD byref [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000050] -----+----- \--* LCL_VAR int V02 tmp1 (last use) ------------ BB20 [0025] [000..001) (throw), preds={BB13} succs={} ***** BB20 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB21 [0026] [000..001) -> BB26(0.5),BB24(0.5) (cond), preds={BB13} succs={BB24,BB26} ***** BB21 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG+----- * JTRUE void [000160] J--XG+-N--- \--* NE int [000158] ---XG+----- +--* IND int [000240] -----+----- | \--* ADD byref [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000159] -----+----- \--* CNS_INT int 0 ------------ BB24 [0029] [000..001) -> BB27(0.5),BB25(0.5) (cond), preds={BB21} succs={BB25,BB27} ***** BB24 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] -A-XG+----- * STOREIND int [000246] -----+----- +--* ADD byref [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000171] -----+----- \--* CNS_INT int 0 ***** BB24 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG+----- \--* ADD int [000204] -A-XG+----- +--* XADD int [000251] -----+----- | +--* ADD byref [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] [000203] -----+----- | \--* CNS_INT int -1 [000205] -----+----- \--* CNS_INT int -1 ***** BB24 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 [000209] -----+----- \--* LCL_VAR int V17 tmp16 (last use) ***** BB24 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 [000253] -----+----- \--* LCL_VAR int V19 tmp18 ***** BB24 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] -----+----- * JTRUE void [000218] N----+-N-U- \--* LT int [000216] -----+----- +--* LCL_VAR int V17 tmp16 [000217] -----+----- \--* CNS_INT int 128 ------------ BB25 [0030] [000..001) -> BB27(1) (always), preds={BB24} succs={BB27} ***** BB25 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 (last use) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 ------------ BB26 [0031] [000..001) -> BB27(1) (always), preds={BB21} succs={BB27} ***** BB26 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] -A-XG+----- * STOREIND int [000242] -----+----- +--* ADD byref [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000167] ---XG+----- \--* ADD int [000165] ---XG+----- +--* IND int [000244] -----+----- | \--* ADD byref [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 (last use) [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000166] -----+----- \--* CNS_INT int -1 ------------ BB27 [0032] [000..007) (return), preds={BB09,BB24,BB25,BB26} succs={} ***** BB27 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000092] -----+----- \--* CNS_INT byref 0 ***** BB27 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Post-Morph *************** In fgMarkDemotedImplicitByRefArgs() *************** Finishing PHASE Post-Morph Trees after Post-Morph --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB17 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB17 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB27(0.5) ( cond ) i bwd bwd-src BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare hascall gcsafe newobj BB13 [0011] 1 BB11 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i nullcheck BB20 [0025] 1 BB13 1 [000..001) (throw ) i hascall gcsafe BB21 [0026] 1 BB13 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB21 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i nullcheck BB25 [0030] 1 BB24 1 [000..001)-> BB27(1) (always) i hascall gcsafe BB26 [0031] 1 BB21 1 [000..001)-> BB27(1) (always) i BB27 [0032] 4 BB09,BB24,BB25,BB26 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB17(0.5),BB16(0.5) (cond), preds={} succs={BB16,BB17} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] -----+----- * JTRUE void [000096] J----+-N--- \--* NE int [000000] -----+----- +--* LCL_VAR ref V00 arg0 [000095] -----+----- \--* CNS_INT ref null ------------ BB16 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB16 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' ------------ BB17 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB17 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G+----- \--* IND int [000103] --C-G+----- \--* ADD byref [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB17 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 [000014] -----+----- \--* OR int [000008] -----+----- +--* LCL_VAR int V02 tmp1 [000013] -----+----- \--* RSH int [000011] -----+----- +--* ADD int [000009] -----+----- | +--* LCL_VAR int V02 tmp1 [000010] -----+----- | \--* CNS_INT int -1 [000012] -----+----- \--* CNS_INT int 31 ***** BB17 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 [000226] ---X-+-N--- \--* COMMA ref [000224] ---X-+----- +--* NULLCHECK byte [000223] -----+----- | \--* LCL_VAR ref V00 arg0 [000225] -----+----- \--* LCL_VAR ref V00 arg0 ***** BB17 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 [000111] -A---+----- \--* ADD long [000230] -A---+----- +--* COMMA long [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 [000228] -----+----- | \--* LCL_VAR long V20 tmp19 [000110] -----+----- \--* CNS_INT long -4 ------------ BB04 [0002] [000..001) -> BB11(0.5),BB05(0.5) (cond), preds={BB09,BB17} succs={BB05,BB11} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 [000026] ---XG+----- \--* IND int [000025] -----+----- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] -----+----- * JTRUE void [000033] N----+-N-U- \--* NE int [000031] -----+----- +--* CAST int <- ushort <- int [000028] -----+----- | \--* LCL_VAR int V05 tmp4 [000032] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB11(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB11} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] -----+----- * JTRUE void [000063] J----+-N--- \--* NE int [000061] -----+----- +--* AND int [000059] -----+----- | +--* LCL_VAR int V05 tmp4 [000060] -----+----- | \--* CNS_INT int 0x8000000 [000062] -----+----- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] -----+----- * JTRUE void [000069] J----+-N--- \--* NE int [000067] -----+----- +--* AND int [000065] -----+----- | +--* LCL_VAR int V05 tmp4 [000066] -----+----- | \--* CNS_INT int 0x3F0000 [000068] -----+----- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000087] -----+----- \--* AND int [000085] -----+----- +--* LCL_VAR int V05 tmp4 [000086] -----+----- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000073] -----+----- \--* ADD int [000071] -----+----- +--* LCL_VAR int V05 tmp4 [000072] -----+----- \--* CNS_INT int -0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB27(0.5) (cond), preds={BB07,BB08} succs={BB27,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG+----- * JTRUE void [000083] NA-XG+-N-U- \--* NE int [000081] -A-XG+----- +--* CMPXCHG int [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 [000076] -----+----- | +--* LCL_VAR int V09 tmp8 [000080] -----+----- | \--* LCL_VAR int V05 tmp4 [000082] -----+----- \--* LCL_VAR int V05 tmp4 ------------ BB11 [0009] [000..001) -> BB13(1),BB12(0) (cond), preds={BB04,BB05} succs={BB12,BB13} ***** BB11 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 [000115] -----+----- \--* AND int [000035] -----+----- +--* LCL_VAR int V05 tmp4 [000114] -----+----- \--* CNS_INT int 0x3FFFFFF ***** BB11 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] -----+----- * JTRUE void [000124] J----+-N--- \--* EQ int [000122] -----+----- +--* AND int [000117] -----+----- | +--* LCL_VAR int V05 tmp4 [000121] -----+----- | \--* CNS_INT int 0xC000000 [000123] -----+----- \--* CNS_INT int 0x8000000 ------------ BB12 [0010] [000..001) (throw), preds={BB11} succs={} ***** BB12 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class ***** BB12 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 ***** BB12 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 ------------ BB13 [0011] [000..001) -> BB21(0.5),BB20(0.5) (cond), preds={BB11} succs={BB20,BB21} ***** BB13 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 [000042] -----+----- \--* LCL_VAR int V06 tmp5 ***** BB13 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG+----- \--* IND ref [000136] -----+----- \--* ADD long [000134] #----+----- +--* IND long [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] ***** BB13 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X-+----- * NULLCHECK byte [000140] -----+----- \--* LCL_VAR ref V13 tmp12 ***** BB13 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 [000130] ---XG+----- \--* IND ref [000147] ----G+----- \--* ADD byref [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- | \--* ADD byref [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 [000234] -----+----- | \--* CNS_INT long 16 [000146] -----+----- \--* LSH long [000144] -----+----- +--* CAST long <- int [000126] -----+----- | \--* LCL_VAR int V06 tmp5 [000145] -----+----- \--* CNS_INT long 5 ***** BB13 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000047] -----+----- \--* CNS_INT long 0 ***** BB13 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG+----- * JTRUE void [000151] J--XG+-N--- \--* EQ int [000150] ---XG+----- +--* IND int [000238] -----+----- | \--* ADD byref [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000050] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB20 [0025] [000..001) (throw), preds={BB13} succs={} ***** BB20 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB21 [0026] [000..001) -> BB26(0.5),BB24(0.5) (cond), preds={BB13} succs={BB24,BB26} ***** BB21 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG+----- * JTRUE void [000160] J--XG+-N--- \--* NE int [000158] ---XG+----- +--* IND int [000240] -----+----- | \--* ADD byref [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000159] -----+----- \--* CNS_INT int 0 ------------ BB24 [0029] [000..001) -> BB27(0.5),BB25(0.5) (cond), preds={BB21} succs={BB25,BB27} ***** BB24 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] -A-XG+----- * STOREIND int [000246] -----+----- +--* ADD byref [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000171] -----+----- \--* CNS_INT int 0 ***** BB24 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG+----- \--* ADD int [000204] -A-XG+----- +--* XADD int [000251] -----+----- | +--* ADD byref [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] [000203] -----+----- | \--* CNS_INT int -1 [000205] -----+----- \--* CNS_INT int -1 ***** BB24 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 [000209] -----+----- \--* LCL_VAR int V17 tmp16 ***** BB24 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 [000253] -----+----- \--* LCL_VAR int V19 tmp18 ***** BB24 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] -----+----- * JTRUE void [000218] N----+-N-U- \--* LT int [000216] -----+----- +--* LCL_VAR int V17 tmp16 [000217] -----+----- \--* CNS_INT int 128 ------------ BB25 [0030] [000..001) -> BB27(1) (always), preds={BB24} succs={BB27} ***** BB25 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 ------------ BB26 [0031] [000..001) -> BB27(1) (always), preds={BB21} succs={BB27} ***** BB26 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] -A-XG+----- * STOREIND int [000242] -----+----- +--* ADD byref [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000167] ---XG+----- \--* ADD int [000165] ---XG+----- +--* IND int [000244] -----+----- | \--* ADD byref [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000166] -----+----- \--* CNS_INT int -1 ------------ BB27 [0032] [000..007) (return), preds={BB09,BB24,BB25,BB26} succs={} ***** BB27 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000092] -----+----- \--* CNS_INT byref 0 ***** BB27 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie [no changes] *************** Starting PHASE Compute block weights --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB17 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB17 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB27(0.5) ( cond ) i bwd bwd-src BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare hascall gcsafe newobj BB13 [0011] 1 BB11 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i nullcheck BB20 [0025] 1 BB13 1 [000..001) (throw ) i hascall gcsafe BB21 [0026] 1 BB13 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB21 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i nullcheck BB25 [0030] 1 BB24 1 [000..001)-> BB27(1) (always) i hascall gcsafe BB26 [0031] 1 BB21 1 [000..001)-> BB27(1) (always) i BB27 [0032] 4 BB09,BB24,BB25,BB26 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Compute block weights [no changes] *************** Starting PHASE Remove empty finally 2 No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally 2 [no changes] *************** Starting PHASE Remove empty try 2 *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try 2 [no changes] *************** Starting PHASE Remove empty try-catch-fault 2 *************** In fgRemoveEmptyTryCatchOrTryFault() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try-catch-fault 2 [no changes] *************** Starting PHASE Invert loops *************** Before renumbering the basic blocks --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB17(0.5),BB16(0.5) ( cond ) i BB16 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB17 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB17 1 [000..001)-> BB11(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB11(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB27(0.5) ( cond ) i bwd bwd-src BB11 [0009] 2 BB04,BB05 1 [000..001)-> BB13(1),BB12(0) ( cond ) i BB12 [0010] 1 BB11 0 [000..001) (throw ) i rare hascall gcsafe newobj BB13 [0011] 1 BB11 1 [000..001)-> BB21(0.5),BB20(0.5) ( cond ) i nullcheck BB20 [0025] 1 BB13 1 [000..001) (throw ) i hascall gcsafe BB21 [0026] 1 BB13 1 [000..001)-> BB26(0.5),BB24(0.5) ( cond ) i BB24 [0029] 1 BB21 1 [000..001)-> BB27(0.5),BB25(0.5) ( cond ) i nullcheck BB25 [0030] 1 BB24 1 [000..001)-> BB27(1) (always) i hascall gcsafe BB26 [0031] 1 BB21 1 [000..001)-> BB27(1) (always) i BB27 [0032] 4 BB09,BB24,BB25,BB26 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB16 to BB02 Renumber BB17 to BB03 Renumber BB11 to BB10 Renumber BB12 to BB11 Renumber BB13 to BB12 Renumber BB20 to BB13 Renumber BB21 to BB14 Renumber BB24 to BB15 Renumber BB25 to BB16 Renumber BB26 to BB17 Renumber BB27 to BB18 *************** After renumbering the basic blocks --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 1 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 1 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 1 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 1 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 1 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 1 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 1 [000..001)-> BB18(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 1 [000..001)-> BB18(1) (always) i BB18 [0032] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Invert loops Trees after Invert loops --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 1 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 1 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 1 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 1 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 1 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 1 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 1 [000..001)-> BB18(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 1 [000..001)-> BB18(1) (always) i BB18 [0032] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] -----+----- * JTRUE void [000096] J----+-N--- \--* NE int [000000] -----+----- +--* LCL_VAR ref V00 arg0 [000095] -----+----- \--* CNS_INT ref null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G+----- \--* IND int [000103] --C-G+----- \--* ADD byref [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 [000014] -----+----- \--* OR int [000008] -----+----- +--* LCL_VAR int V02 tmp1 [000013] -----+----- \--* RSH int [000011] -----+----- +--* ADD int [000009] -----+----- | +--* LCL_VAR int V02 tmp1 [000010] -----+----- | \--* CNS_INT int -1 [000012] -----+----- \--* CNS_INT int 31 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 [000226] ---X-+-N--- \--* COMMA ref [000224] ---X-+----- +--* NULLCHECK byte [000223] -----+----- | \--* LCL_VAR ref V00 arg0 [000225] -----+----- \--* LCL_VAR ref V00 arg0 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 [000111] -A---+----- \--* ADD long [000230] -A---+----- +--* COMMA long [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 [000228] -----+----- | \--* LCL_VAR long V20 tmp19 [000110] -----+----- \--* CNS_INT long -4 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 [000026] ---XG+----- \--* IND int [000025] -----+----- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] -----+----- * JTRUE void [000033] N----+-N-U- \--* NE int [000031] -----+----- +--* CAST int <- ushort <- int [000028] -----+----- | \--* LCL_VAR int V05 tmp4 [000032] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] -----+----- * JTRUE void [000063] J----+-N--- \--* NE int [000061] -----+----- +--* AND int [000059] -----+----- | +--* LCL_VAR int V05 tmp4 [000060] -----+----- | \--* CNS_INT int 0x8000000 [000062] -----+----- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] -----+----- * JTRUE void [000069] J----+-N--- \--* NE int [000067] -----+----- +--* AND int [000065] -----+----- | +--* LCL_VAR int V05 tmp4 [000066] -----+----- | \--* CNS_INT int 0x3F0000 [000068] -----+----- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000087] -----+----- \--* AND int [000085] -----+----- +--* LCL_VAR int V05 tmp4 [000086] -----+----- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000073] -----+----- \--* ADD int [000071] -----+----- +--* LCL_VAR int V05 tmp4 [000072] -----+----- \--* CNS_INT int -0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG+----- * JTRUE void [000083] NA-XG+-N-U- \--* NE int [000081] -A-XG+----- +--* CMPXCHG int [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 [000076] -----+----- | +--* LCL_VAR int V09 tmp8 [000080] -----+----- | \--* LCL_VAR int V05 tmp4 [000082] -----+----- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 [000115] -----+----- \--* AND int [000035] -----+----- +--* LCL_VAR int V05 tmp4 [000114] -----+----- \--* CNS_INT int 0x3FFFFFF ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] -----+----- * JTRUE void [000124] J----+-N--- \--* EQ int [000122] -----+----- +--* AND int [000117] -----+----- | +--* LCL_VAR int V05 tmp4 [000121] -----+----- | \--* CNS_INT int 0xC000000 [000123] -----+----- \--* CNS_INT int 0x8000000 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 [000042] -----+----- \--* LCL_VAR int V06 tmp5 ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG+----- \--* IND ref [000136] -----+----- \--* ADD long [000134] #----+----- +--* IND long [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X-+----- * NULLCHECK byte [000140] -----+----- \--* LCL_VAR ref V13 tmp12 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 [000130] ---XG+----- \--* IND ref [000147] ----G+----- \--* ADD byref [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- | \--* ADD byref [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 [000234] -----+----- | \--* CNS_INT long 16 [000146] -----+----- \--* LSH long [000144] -----+----- +--* CAST long <- int [000126] -----+----- | \--* LCL_VAR int V06 tmp5 [000145] -----+----- \--* CNS_INT long 5 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000047] -----+----- \--* CNS_INT long 0 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG+----- * JTRUE void [000151] J--XG+-N--- \--* EQ int [000150] ---XG+----- +--* IND int [000238] -----+----- | \--* ADD byref [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000050] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG+----- * JTRUE void [000160] J--XG+-N--- \--* NE int [000158] ---XG+----- +--* IND int [000240] -----+----- | \--* ADD byref [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000159] -----+----- \--* CNS_INT int 0 ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] -A-XG+----- * STOREIND int [000246] -----+----- +--* ADD byref [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000171] -----+----- \--* CNS_INT int 0 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG+----- \--* ADD int [000204] -A-XG+----- +--* XADD int [000251] -----+----- | +--* ADD byref [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] [000203] -----+----- | \--* CNS_INT int -1 [000205] -----+----- \--* CNS_INT int -1 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 [000209] -----+----- \--* LCL_VAR int V17 tmp16 ***** BB15 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 [000253] -----+----- \--* LCL_VAR int V19 tmp18 ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] -----+----- * JTRUE void [000218] N----+-N-U- \--* LT int [000216] -----+----- +--* LCL_VAR int V17 tmp16 [000217] -----+----- \--* CNS_INT int 128 ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] -A-XG+----- * STOREIND int [000242] -----+----- +--* ADD byref [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000167] ---XG+----- \--* ADD int [000165] ---XG+----- +--* IND int [000244] -----+----- | \--* ADD byref [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000166] -----+----- \--* CNS_INT int -1 ------------ BB18 [0032] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} ***** BB18 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000092] -----+----- \--* CNS_INT byref 0 ***** BB18 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Optimize control flow *************** In fgUpdateFlowGraph() Before updating the flow graph: --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 1 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 1 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 1 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 1 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 1 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 1 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 1 [000..001)-> BB18(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 1 [000..001)-> BB18(1) (always) i BB18 [0032] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- Considering uncond to cond BB03 -> BB04 Considering uncond to cond BB07 -> BB09 Considering uncond to cond BB08 -> BB09 Considering uncond to cond BB16 -> BB18 Considering uncond to cond BB17 -> BB18 *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 1 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 1 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 1 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 1 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 1 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 1 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 1 [000..001)-> BB18(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 1 [000..001)-> BB18(1) (always) i BB18 [0032] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Optimize control flow Trees after Optimize control flow --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 1 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 1 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 1 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 1 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 1 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 1 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 1 [000..001)-> BB18(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 1 [000..001)-> BB18(1) (always) i BB18 [0032] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] -----+----- * JTRUE void [000096] J----+-N--- \--* NE int [000000] -----+----- +--* LCL_VAR ref V00 arg0 [000095] -----+----- \--* CNS_INT ref null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G+----- \--* IND int [000103] --C-G+----- \--* ADD byref [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 [000014] -----+----- \--* OR int [000008] -----+----- +--* LCL_VAR int V02 tmp1 [000013] -----+----- \--* RSH int [000011] -----+----- +--* ADD int [000009] -----+----- | +--* LCL_VAR int V02 tmp1 [000010] -----+----- | \--* CNS_INT int -1 [000012] -----+----- \--* CNS_INT int 31 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 [000226] ---X-+-N--- \--* COMMA ref [000224] ---X-+----- +--* NULLCHECK byte [000223] -----+----- | \--* LCL_VAR ref V00 arg0 [000225] -----+----- \--* LCL_VAR ref V00 arg0 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 [000111] -A---+----- \--* ADD long [000230] -A---+----- +--* COMMA long [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 [000228] -----+----- | \--* LCL_VAR long V20 tmp19 [000110] -----+----- \--* CNS_INT long -4 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 [000026] ---XG+----- \--* IND int [000025] -----+----- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] -----+----- * JTRUE void [000033] N----+-N-U- \--* NE int [000031] -----+----- +--* CAST int <- ushort <- int [000028] -----+----- | \--* LCL_VAR int V05 tmp4 [000032] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] -----+----- * JTRUE void [000063] J----+-N--- \--* NE int [000061] -----+----- +--* AND int [000059] -----+----- | +--* LCL_VAR int V05 tmp4 [000060] -----+----- | \--* CNS_INT int 0x8000000 [000062] -----+----- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] -----+----- * JTRUE void [000069] J----+-N--- \--* NE int [000067] -----+----- +--* AND int [000065] -----+----- | +--* LCL_VAR int V05 tmp4 [000066] -----+----- | \--* CNS_INT int 0x3F0000 [000068] -----+----- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000087] -----+----- \--* AND int [000085] -----+----- +--* LCL_VAR int V05 tmp4 [000086] -----+----- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000073] -----+----- \--* ADD int [000071] -----+----- +--* LCL_VAR int V05 tmp4 [000072] -----+----- \--* CNS_INT int -0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG+----- * JTRUE void [000083] NA-XG+-N-U- \--* NE int [000081] -A-XG+----- +--* CMPXCHG int [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 [000076] -----+----- | +--* LCL_VAR int V09 tmp8 [000080] -----+----- | \--* LCL_VAR int V05 tmp4 [000082] -----+----- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 [000115] -----+----- \--* AND int [000035] -----+----- +--* LCL_VAR int V05 tmp4 [000114] -----+----- \--* CNS_INT int 0x3FFFFFF ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] -----+----- * JTRUE void [000124] J----+-N--- \--* EQ int [000122] -----+----- +--* AND int [000117] -----+----- | +--* LCL_VAR int V05 tmp4 [000121] -----+----- | \--* CNS_INT int 0xC000000 [000123] -----+----- \--* CNS_INT int 0x8000000 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 [000042] -----+----- \--* LCL_VAR int V06 tmp5 ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG+----- \--* IND ref [000136] -----+----- \--* ADD long [000134] #----+----- +--* IND long [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X-+----- * NULLCHECK byte [000140] -----+----- \--* LCL_VAR ref V13 tmp12 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 [000130] ---XG+----- \--* IND ref [000147] ----G+----- \--* ADD byref [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- | \--* ADD byref [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 [000234] -----+----- | \--* CNS_INT long 16 [000146] -----+----- \--* LSH long [000144] -----+----- +--* CAST long <- int [000126] -----+----- | \--* LCL_VAR int V06 tmp5 [000145] -----+----- \--* CNS_INT long 5 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000047] -----+----- \--* CNS_INT long 0 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG+----- * JTRUE void [000151] J--XG+-N--- \--* EQ int [000150] ---XG+----- +--* IND int [000238] -----+----- | \--* ADD byref [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000050] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG+----- * JTRUE void [000160] J--XG+-N--- \--* NE int [000158] ---XG+----- +--* IND int [000240] -----+----- | \--* ADD byref [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000159] -----+----- \--* CNS_INT int 0 ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] -A-XG+----- * STOREIND int [000246] -----+----- +--* ADD byref [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000171] -----+----- \--* CNS_INT int 0 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG+----- \--* ADD int [000204] -A-XG+----- +--* XADD int [000251] -----+----- | +--* ADD byref [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] [000203] -----+----- | \--* CNS_INT int -1 [000205] -----+----- \--* CNS_INT int -1 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 [000209] -----+----- \--* LCL_VAR int V17 tmp16 ***** BB15 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 [000253] -----+----- \--* LCL_VAR int V19 tmp18 ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] -----+----- * JTRUE void [000218] N----+-N-U- \--* LT int [000216] -----+----- +--* LCL_VAR int V17 tmp16 [000217] -----+----- \--* CNS_INT int 128 ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] -A-XG+----- * STOREIND int [000242] -----+----- +--* ADD byref [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000167] ---XG+----- \--* ADD int [000165] ---XG+----- +--* IND int [000244] -----+----- | \--* ADD byref [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000166] -----+----- \--* CNS_INT int -1 ------------ BB18 [0032] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} ***** BB18 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000092] -----+----- \--* CNS_INT byref 0 ***** BB18 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Post-morph head and tail merge *************** Finishing PHASE Post-morph head and tail merge Trees after Post-morph head and tail merge --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 1 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 1 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 1 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 1 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 1 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 1 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 1 [000..001)-> BB18(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 1 [000..001)-> BB18(1) (always) i BB18 [0032] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] -----+----- * JTRUE void [000096] J----+-N--- \--* NE int [000000] -----+----- +--* LCL_VAR ref V00 arg0 [000095] -----+----- \--* CNS_INT ref null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G+----- \--* IND int [000103] --C-G+----- \--* ADD byref [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 [000014] -----+----- \--* OR int [000008] -----+----- +--* LCL_VAR int V02 tmp1 [000013] -----+----- \--* RSH int [000011] -----+----- +--* ADD int [000009] -----+----- | +--* LCL_VAR int V02 tmp1 [000010] -----+----- | \--* CNS_INT int -1 [000012] -----+----- \--* CNS_INT int 31 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 [000226] ---X-+-N--- \--* COMMA ref [000224] ---X-+----- +--* NULLCHECK byte [000223] -----+----- | \--* LCL_VAR ref V00 arg0 [000225] -----+----- \--* LCL_VAR ref V00 arg0 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 [000111] -A---+----- \--* ADD long [000230] -A---+----- +--* COMMA long [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 [000228] -----+----- | \--* LCL_VAR long V20 tmp19 [000110] -----+----- \--* CNS_INT long -4 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 [000026] ---XG+----- \--* IND int [000025] -----+----- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] -----+----- * JTRUE void [000033] N----+-N-U- \--* NE int [000031] -----+----- +--* CAST int <- ushort <- int [000028] -----+----- | \--* LCL_VAR int V05 tmp4 [000032] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] -----+----- * JTRUE void [000063] J----+-N--- \--* NE int [000061] -----+----- +--* AND int [000059] -----+----- | +--* LCL_VAR int V05 tmp4 [000060] -----+----- | \--* CNS_INT int 0x8000000 [000062] -----+----- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] -----+----- * JTRUE void [000069] J----+-N--- \--* NE int [000067] -----+----- +--* AND int [000065] -----+----- | +--* LCL_VAR int V05 tmp4 [000066] -----+----- | \--* CNS_INT int 0x3F0000 [000068] -----+----- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000087] -----+----- \--* AND int [000085] -----+----- +--* LCL_VAR int V05 tmp4 [000086] -----+----- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000073] -----+----- \--* ADD int [000071] -----+----- +--* LCL_VAR int V05 tmp4 [000072] -----+----- \--* CNS_INT int -0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG+----- * JTRUE void [000083] NA-XG+-N-U- \--* NE int [000081] -A-XG+----- +--* CMPXCHG int [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 [000076] -----+----- | +--* LCL_VAR int V09 tmp8 [000080] -----+----- | \--* LCL_VAR int V05 tmp4 [000082] -----+----- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 [000115] -----+----- \--* AND int [000035] -----+----- +--* LCL_VAR int V05 tmp4 [000114] -----+----- \--* CNS_INT int 0x3FFFFFF ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] -----+----- * JTRUE void [000124] J----+-N--- \--* EQ int [000122] -----+----- +--* AND int [000117] -----+----- | +--* LCL_VAR int V05 tmp4 [000121] -----+----- | \--* CNS_INT int 0xC000000 [000123] -----+----- \--* CNS_INT int 0x8000000 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 [000042] -----+----- \--* LCL_VAR int V06 tmp5 ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG+----- \--* IND ref [000136] -----+----- \--* ADD long [000134] #----+----- +--* IND long [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X-+----- * NULLCHECK byte [000140] -----+----- \--* LCL_VAR ref V13 tmp12 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 [000130] ---XG+----- \--* IND ref [000147] ----G+----- \--* ADD byref [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- | \--* ADD byref [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 [000234] -----+----- | \--* CNS_INT long 16 [000146] -----+----- \--* LSH long [000144] -----+----- +--* CAST long <- int [000126] -----+----- | \--* LCL_VAR int V06 tmp5 [000145] -----+----- \--* CNS_INT long 5 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000047] -----+----- \--* CNS_INT long 0 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG+----- * JTRUE void [000151] J--XG+-N--- \--* EQ int [000150] ---XG+----- +--* IND int [000238] -----+----- | \--* ADD byref [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000050] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG+----- * JTRUE void [000160] J--XG+-N--- \--* NE int [000158] ---XG+----- +--* IND int [000240] -----+----- | \--* ADD byref [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000159] -----+----- \--* CNS_INT int 0 ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] -A-XG+----- * STOREIND int [000246] -----+----- +--* ADD byref [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000171] -----+----- \--* CNS_INT int 0 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG+----- \--* ADD int [000204] -A-XG+----- +--* XADD int [000251] -----+----- | +--* ADD byref [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] [000203] -----+----- | \--* CNS_INT int -1 [000205] -----+----- \--* CNS_INT int -1 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 [000209] -----+----- \--* LCL_VAR int V17 tmp16 ***** BB15 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 [000253] -----+----- \--* LCL_VAR int V19 tmp18 ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] -----+----- * JTRUE void [000218] N----+-N-U- \--* LT int [000216] -----+----- +--* LCL_VAR int V17 tmp16 [000217] -----+----- \--* CNS_INT int 128 ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] -A-XG+----- * STOREIND int [000242] -----+----- +--* ADD byref [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000167] ---XG+----- \--* ADD int [000165] ---XG+----- +--* IND int [000244] -----+----- | \--* ADD byref [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000166] -----+----- \--* CNS_INT int -1 ------------ BB18 [0032] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} ***** BB18 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000092] -----+----- \--* CNS_INT byref 0 ***** BB18 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE DFS blocks and remove dead code 3 *************** Finishing PHASE DFS blocks and remove dead code 3 [no changes] *************** Starting PHASE Find loops *************** In optFindLoopsPhase() Identifying loops in DFS tree with following reverse post order: RPO -> BB [pre, post] 00 -> BB01[0, 17] 01 -> BB03[2, 16] 02 -> BB04[3, 15] 03 -> BB05[4, 14] 04 -> BB10[10, 13] 05 -> BB12[12, 12] 06 -> BB14[14, 11] 07 -> BB17[17, 10] 08 -> BB15[15, 9] 09 -> BB16[16, 8] 10 -> BB13[13, 7] 11 -> BB11[11, 6] 12 -> BB06[5, 5] 13 -> BB08[9, 4] 14 -> BB07[6, 3] 15 -> BB09[7, 2] 16 -> BB18[8, 1] 17 -> BB02[1, 0] BB09 -> BB04 is a backedge BB04 is the header of a DFS loop with 1 back edges Loop has 6 blocks BB04 -> BB10 is an exit edge BB05 -> BB10 is an exit edge BB09 -> BB18 is an exit edge BB03 -> BB04 is an entry edge Added loop L00 with header BB04 Found 1 loops *************** Natural loop graph L00 header: BB04 Members (6): [BB04..BB09] Entry: BB03 -> BB04 Exit: BB04 -> BB10; BB05 -> BB10; BB09 -> BB18 Back: BB09 -> BB04 Natural loop L00 already has preheader BB03 All preds of exit BB10 of L00 are already in the loop, no exit canonicalization needed All preds of exit BB10 of L00 are already in the loop, no exit canonicalization needed Canonicalize exit BB18 for L00 to have only loop predecessors New Basic Block BB19 [0039] created. setting likelihood of BB19 -> BB18 to 1 Created new exit BB19 to replace BB18 exit for L00 Identifying loops in DFS tree with following reverse post order: RPO -> BB [pre, post] 00 -> BB01[0, 18] 01 -> BB03[2, 17] 02 -> BB04[3, 16] 03 -> BB05[4, 15] 04 -> BB10[11, 14] 05 -> BB12[13, 13] 06 -> BB14[15, 12] 07 -> BB17[18, 11] 08 -> BB15[16, 10] 09 -> BB16[17, 9] 10 -> BB13[14, 8] 11 -> BB11[12, 7] 12 -> BB06[5, 6] 13 -> BB08[10, 5] 14 -> BB07[6, 4] 15 -> BB09[7, 3] 16 -> BB19[8, 2] 17 -> BB18[9, 1] 18 -> BB02[1, 0] BB09 -> BB04 is a backedge BB04 is the header of a DFS loop with 1 back edges Loop has 6 blocks BB04 -> BB10 is an exit edge BB05 -> BB10 is an exit edge BB09 -> BB19 is an exit edge BB03 -> BB04 is an entry edge Added loop L00 with header BB04 Found 1 loops *************** Natural loop graph L00 header: BB04 Members (6): [BB04..BB09] Entry: BB03 -> BB04 Exit: BB04 -> BB10; BB05 -> BB10; BB09 -> BB19 Back: BB09 -> BB04 *************** Finishing PHASE Find loops Trees after Find loops --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 1 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB19(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 1 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 1 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 1 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 1 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 1 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 1 [000..001)-> BB18(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 1 [000..001)-> BB18(1) (always) i BB19 [0039] 1 BB09 0.50 [000..???)-> BB18(1) (always) internal BB18 [0032] 4 BB15,BB16,BB17,BB19 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] -----+----- * JTRUE void [000096] J----+-N--- \--* NE int [000000] -----+----- +--* LCL_VAR ref V00 arg0 [000095] -----+----- \--* CNS_INT ref null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G+----- \--* IND int [000103] --C-G+----- \--* ADD byref [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 [000014] -----+----- \--* OR int [000008] -----+----- +--* LCL_VAR int V02 tmp1 [000013] -----+----- \--* RSH int [000011] -----+----- +--* ADD int [000009] -----+----- | +--* LCL_VAR int V02 tmp1 [000010] -----+----- | \--* CNS_INT int -1 [000012] -----+----- \--* CNS_INT int 31 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 [000226] ---X-+-N--- \--* COMMA ref [000224] ---X-+----- +--* NULLCHECK byte [000223] -----+----- | \--* LCL_VAR ref V00 arg0 [000225] -----+----- \--* LCL_VAR ref V00 arg0 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 [000111] -A---+----- \--* ADD long [000230] -A---+----- +--* COMMA long [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 [000228] -----+----- | \--* LCL_VAR long V20 tmp19 [000110] -----+----- \--* CNS_INT long -4 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 [000026] ---XG+----- \--* IND int [000025] -----+----- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] -----+----- * JTRUE void [000033] N----+-N-U- \--* NE int [000031] -----+----- +--* CAST int <- ushort <- int [000028] -----+----- | \--* LCL_VAR int V05 tmp4 [000032] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] -----+----- * JTRUE void [000063] J----+-N--- \--* NE int [000061] -----+----- +--* AND int [000059] -----+----- | +--* LCL_VAR int V05 tmp4 [000060] -----+----- | \--* CNS_INT int 0x8000000 [000062] -----+----- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] -----+----- * JTRUE void [000069] J----+-N--- \--* NE int [000067] -----+----- +--* AND int [000065] -----+----- | +--* LCL_VAR int V05 tmp4 [000066] -----+----- | \--* CNS_INT int 0x3F0000 [000068] -----+----- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000087] -----+----- \--* AND int [000085] -----+----- +--* LCL_VAR int V05 tmp4 [000086] -----+----- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000073] -----+----- \--* ADD int [000071] -----+----- +--* LCL_VAR int V05 tmp4 [000072] -----+----- \--* CNS_INT int -0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB19(0.5) (cond), preds={BB07,BB08} succs={BB19,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG+----- * JTRUE void [000083] NA-XG+-N-U- \--* NE int [000081] -A-XG+----- +--* CMPXCHG int [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 [000076] -----+----- | +--* LCL_VAR int V09 tmp8 [000080] -----+----- | \--* LCL_VAR int V05 tmp4 [000082] -----+----- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 [000115] -----+----- \--* AND int [000035] -----+----- +--* LCL_VAR int V05 tmp4 [000114] -----+----- \--* CNS_INT int 0x3FFFFFF ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] -----+----- * JTRUE void [000124] J----+-N--- \--* EQ int [000122] -----+----- +--* AND int [000117] -----+----- | +--* LCL_VAR int V05 tmp4 [000121] -----+----- | \--* CNS_INT int 0xC000000 [000123] -----+----- \--* CNS_INT int 0x8000000 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 [000042] -----+----- \--* LCL_VAR int V06 tmp5 ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG+----- \--* IND ref [000136] -----+----- \--* ADD long [000134] #----+----- +--* IND long [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X-+----- * NULLCHECK byte [000140] -----+----- \--* LCL_VAR ref V13 tmp12 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 [000130] ---XG+----- \--* IND ref [000147] ----G+----- \--* ADD byref [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- | \--* ADD byref [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 [000234] -----+----- | \--* CNS_INT long 16 [000146] -----+----- \--* LSH long [000144] -----+----- +--* CAST long <- int [000126] -----+----- | \--* LCL_VAR int V06 tmp5 [000145] -----+----- \--* CNS_INT long 5 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000047] -----+----- \--* CNS_INT long 0 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG+----- * JTRUE void [000151] J--XG+-N--- \--* EQ int [000150] ---XG+----- +--* IND int [000238] -----+----- | \--* ADD byref [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000050] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG+----- * JTRUE void [000160] J--XG+-N--- \--* NE int [000158] ---XG+----- +--* IND int [000240] -----+----- | \--* ADD byref [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000159] -----+----- \--* CNS_INT int 0 ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] -A-XG+----- * STOREIND int [000246] -----+----- +--* ADD byref [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000171] -----+----- \--* CNS_INT int 0 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG+----- \--* ADD int [000204] -A-XG+----- +--* XADD int [000251] -----+----- | +--* ADD byref [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] [000203] -----+----- | \--* CNS_INT int -1 [000205] -----+----- \--* CNS_INT int -1 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 [000209] -----+----- \--* LCL_VAR int V17 tmp16 ***** BB15 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 [000253] -----+----- \--* LCL_VAR int V19 tmp18 ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] -----+----- * JTRUE void [000218] N----+-N-U- \--* LT int [000216] -----+----- +--* LCL_VAR int V17 tmp16 [000217] -----+----- \--* CNS_INT int 128 ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] -A-XG+----- * STOREIND int [000242] -----+----- +--* ADD byref [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000167] ---XG+----- \--* ADD int [000165] ---XG+----- +--* IND int [000244] -----+----- | \--* ADD byref [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000166] -----+----- \--* CNS_INT int -1 ------------ BB19 [0039] [000..???) -> BB18(1) (always), preds={BB09} succs={BB18} ------------ BB18 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB19} succs={} ***** BB18 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000092] -----+----- \--* CNS_INT byref 0 ***** BB18 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Set block weights After computing the dominance tree: BB01 : BB03 BB02 BB03 : BB04 BB04 : BB05 BB10 BB18 BB05 : BB06 BB10 : BB12 BB11 BB12 : BB14 BB13 BB14 : BB17 BB15 BB15 : BB16 BB06 : BB08 BB07 BB09 BB09 : BB19 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB02 BB01 BB03 : BB03 BB01 BB04 : BB09 BB07 BB08 BB06 BB05 BB04 BB03 BB01 BB05 : BB09 BB07 BB08 BB06 BB05 BB04 BB03 BB01 BB06 : BB09 BB07 BB08 BB06 BB05 BB04 BB03 BB01 BB07 : BB09 BB07 BB08 BB06 BB05 BB04 BB03 BB01 BB08 : BB09 BB07 BB08 BB06 BB05 BB04 BB03 BB01 BB09 : BB09 BB07 BB08 BB06 BB05 BB04 BB03 BB01 BB10 : BB09 BB07 BB08 BB06 BB10 BB05 BB04 BB03 BB01 BB11 : BB09 BB07 BB08 BB06 BB11 BB10 BB05 BB04 BB03 BB01 BB12 : BB09 BB07 BB08 BB06 BB12 BB10 BB05 BB04 BB03 BB01 BB13 : BB09 BB07 BB08 BB06 BB13 BB12 BB10 BB05 BB04 BB03 BB01 BB14 : BB09 BB07 BB08 BB06 BB14 BB12 BB10 BB05 BB04 BB03 BB01 BB15 : BB09 BB07 BB08 BB06 BB15 BB14 BB12 BB10 BB05 BB04 BB03 BB01 BB16 : BB09 BB07 BB08 BB06 BB16 BB15 BB14 BB12 BB10 BB05 BB04 BB03 BB01 BB17 : BB09 BB07 BB08 BB06 BB17 BB14 BB12 BB10 BB05 BB04 BB03 BB01 BB19 : BB19 BB09 BB07 BB08 BB06 BB05 BB04 BB03 BB01 BB18 : BB18 BB19 BB09 BB07 BB08 BB06 BB16 BB15 BB17 BB14 BB12 BB10 BB05 BB04 BB03 BB01 *************** Before renumbering the basic blocks --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 1 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB19(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 1 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 1 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 1 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 1 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 1 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 1 [000..001)-> BB18(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 1 [000..001)-> BB18(1) (always) i BB19 [0039] 1 BB09 0.50 [000..???)-> BB18(1) (always) internal BB18 [0032] 4 BB15,BB16,BB17,BB19 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB19 to BB18 Renumber BB18 to BB19 *************** After renumbering the basic blocks --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 1 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 1 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i bwd bwd-target BB05 [0003] 1 BB04 1 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 1 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 1 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 1 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 1 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 1 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 1 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 1 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 1 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 1 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 1 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.50 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In optMarkLoopHeads() 1 loop heads marked *************** In optFindAndScaleGeneralLoopBlocks() Marking a loop from BB04 to BB09 BB04(wt=800) BB05(wt=800) BB06(wt=800) BB07(wt=400) BB08(wt=400) BB09(wt=800) Found a total of 1 general loops. Return blocks: BB19 *************** Finishing PHASE Set block weights Trees after Set block weights --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] -----+----- * JTRUE void [000096] J----+-N--- \--* NE int [000000] -----+----- +--* LCL_VAR ref V00 arg0 [000095] -----+----- \--* CNS_INT ref null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G+----- \--* IND int [000103] --C-G+----- \--* ADD byref [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 [000014] -----+----- \--* OR int [000008] -----+----- +--* LCL_VAR int V02 tmp1 [000013] -----+----- \--* RSH int [000011] -----+----- +--* ADD int [000009] -----+----- | +--* LCL_VAR int V02 tmp1 [000010] -----+----- | \--* CNS_INT int -1 [000012] -----+----- \--* CNS_INT int 31 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 [000226] ---X-+-N--- \--* COMMA ref [000224] ---X-+----- +--* NULLCHECK byte [000223] -----+----- | \--* LCL_VAR ref V00 arg0 [000225] -----+----- \--* LCL_VAR ref V00 arg0 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 [000111] -A---+----- \--* ADD long [000230] -A---+----- +--* COMMA long [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 [000228] -----+----- | \--* LCL_VAR long V20 tmp19 [000110] -----+----- \--* CNS_INT long -4 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 [000026] ---XG+----- \--* IND int [000025] -----+----- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] -----+----- * JTRUE void [000033] N----+-N-U- \--* NE int [000031] -----+----- +--* CAST int <- ushort <- int [000028] -----+----- | \--* LCL_VAR int V05 tmp4 [000032] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] -----+----- * JTRUE void [000063] J----+-N--- \--* NE int [000061] -----+----- +--* AND int [000059] -----+----- | +--* LCL_VAR int V05 tmp4 [000060] -----+----- | \--* CNS_INT int 0x8000000 [000062] -----+----- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] -----+----- * JTRUE void [000069] J----+-N--- \--* NE int [000067] -----+----- +--* AND int [000065] -----+----- | +--* LCL_VAR int V05 tmp4 [000066] -----+----- | \--* CNS_INT int 0x3F0000 [000068] -----+----- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000087] -----+----- \--* AND int [000085] -----+----- +--* LCL_VAR int V05 tmp4 [000086] -----+----- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000073] -----+----- \--* ADD int [000071] -----+----- +--* LCL_VAR int V05 tmp4 [000072] -----+----- \--* CNS_INT int -0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG+----- * JTRUE void [000083] NA-XG+-N-U- \--* NE int [000081] -A-XG+----- +--* CMPXCHG int [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 [000076] -----+----- | +--* LCL_VAR int V09 tmp8 [000080] -----+----- | \--* LCL_VAR int V05 tmp4 [000082] -----+----- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 [000115] -----+----- \--* AND int [000035] -----+----- +--* LCL_VAR int V05 tmp4 [000114] -----+----- \--* CNS_INT int 0x3FFFFFF ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] -----+----- * JTRUE void [000124] J----+-N--- \--* EQ int [000122] -----+----- +--* AND int [000117] -----+----- | +--* LCL_VAR int V05 tmp4 [000121] -----+----- | \--* CNS_INT int 0xC000000 [000123] -----+----- \--* CNS_INT int 0x8000000 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 [000042] -----+----- \--* LCL_VAR int V06 tmp5 ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG+----- \--* IND ref [000136] -----+----- \--* ADD long [000134] #----+----- +--* IND long [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X-+----- * NULLCHECK byte [000140] -----+----- \--* LCL_VAR ref V13 tmp12 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 [000130] ---XG+----- \--* IND ref [000147] ----G+----- \--* ADD byref [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- | \--* ADD byref [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 [000234] -----+----- | \--* CNS_INT long 16 [000146] -----+----- \--* LSH long [000144] -----+----- +--* CAST long <- int [000126] -----+----- | \--* LCL_VAR int V06 tmp5 [000145] -----+----- \--* CNS_INT long 5 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000047] -----+----- \--* CNS_INT long 0 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG+----- * JTRUE void [000151] J--XG+-N--- \--* EQ int [000150] ---XG+----- +--* IND int [000238] -----+----- | \--* ADD byref [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000050] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG+----- * JTRUE void [000160] J--XG+-N--- \--* NE int [000158] ---XG+----- +--* IND int [000240] -----+----- | \--* ADD byref [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000159] -----+----- \--* CNS_INT int 0 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] -A-XG+----- * STOREIND int [000246] -----+----- +--* ADD byref [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000171] -----+----- \--* CNS_INT int 0 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG+----- \--* ADD int [000204] -A-XG+----- +--* XADD int [000251] -----+----- | +--* ADD byref [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] [000203] -----+----- | \--* CNS_INT int -1 [000205] -----+----- \--* CNS_INT int -1 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 [000209] -----+----- \--* LCL_VAR int V17 tmp16 ***** BB15 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 [000253] -----+----- \--* LCL_VAR int V19 tmp18 ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] -----+----- * JTRUE void [000218] N----+-N-U- \--* LT int [000216] -----+----- +--* LCL_VAR int V17 tmp16 [000217] -----+----- \--* CNS_INT int 128 ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] -A-XG+----- * STOREIND int [000242] -----+----- +--* ADD byref [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000167] ---XG+----- \--* ADD int [000165] ---XG+----- +--* IND int [000244] -----+----- | \--* ADD byref [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000166] -----+----- \--* CNS_INT int -1 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000092] -----+----- \--* CNS_INT byref 0 ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Clone loops *************** In optCloneLoops() Considering loop L00 to clone for optimizations. Analyzing iteration for L00 with header BB04 Preheader = BB03 Checking exiting block BB04 Could not extract an IV Checking exiting block BB05 Could not extract an IV Checking exiting block BB09 Could not extract an IV Could not find any IV Loop cloning: rejecting loop L00. Could not analyze iteration. ------------------------------------------------------------ No clonable loops *************** Finishing PHASE Clone loops Trees after Clone loops --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] -----+----- * JTRUE void [000096] J----+-N--- \--* NE int [000000] -----+----- +--* LCL_VAR ref V00 arg0 [000095] -----+----- \--* CNS_INT ref null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G+----- \--* IND int [000103] --C-G+----- \--* ADD byref [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 [000014] -----+----- \--* OR int [000008] -----+----- +--* LCL_VAR int V02 tmp1 [000013] -----+----- \--* RSH int [000011] -----+----- +--* ADD int [000009] -----+----- | +--* LCL_VAR int V02 tmp1 [000010] -----+----- | \--* CNS_INT int -1 [000012] -----+----- \--* CNS_INT int 31 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 [000226] ---X-+-N--- \--* COMMA ref [000224] ---X-+----- +--* NULLCHECK byte [000223] -----+----- | \--* LCL_VAR ref V00 arg0 [000225] -----+----- \--* LCL_VAR ref V00 arg0 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 [000111] -A---+----- \--* ADD long [000230] -A---+----- +--* COMMA long [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 [000228] -----+----- | \--* LCL_VAR long V20 tmp19 [000110] -----+----- \--* CNS_INT long -4 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 [000026] ---XG+----- \--* IND int [000025] -----+----- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] -----+----- * JTRUE void [000033] N----+-N-U- \--* NE int [000031] -----+----- +--* CAST int <- ushort <- int [000028] -----+----- | \--* LCL_VAR int V05 tmp4 [000032] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] -----+----- * JTRUE void [000063] J----+-N--- \--* NE int [000061] -----+----- +--* AND int [000059] -----+----- | +--* LCL_VAR int V05 tmp4 [000060] -----+----- | \--* CNS_INT int 0x8000000 [000062] -----+----- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] -----+----- * JTRUE void [000069] J----+-N--- \--* NE int [000067] -----+----- +--* AND int [000065] -----+----- | +--* LCL_VAR int V05 tmp4 [000066] -----+----- | \--* CNS_INT int 0x3F0000 [000068] -----+----- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000087] -----+----- \--* AND int [000085] -----+----- +--* LCL_VAR int V05 tmp4 [000086] -----+----- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000073] -----+----- \--* ADD int [000071] -----+----- +--* LCL_VAR int V05 tmp4 [000072] -----+----- \--* CNS_INT int -0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG+----- * JTRUE void [000083] NA-XG+-N-U- \--* NE int [000081] -A-XG+----- +--* CMPXCHG int [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 [000076] -----+----- | +--* LCL_VAR int V09 tmp8 [000080] -----+----- | \--* LCL_VAR int V05 tmp4 [000082] -----+----- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 [000115] -----+----- \--* AND int [000035] -----+----- +--* LCL_VAR int V05 tmp4 [000114] -----+----- \--* CNS_INT int 0x3FFFFFF ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] -----+----- * JTRUE void [000124] J----+-N--- \--* EQ int [000122] -----+----- +--* AND int [000117] -----+----- | +--* LCL_VAR int V05 tmp4 [000121] -----+----- | \--* CNS_INT int 0xC000000 [000123] -----+----- \--* CNS_INT int 0x8000000 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 [000042] -----+----- \--* LCL_VAR int V06 tmp5 ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG+----- \--* IND ref [000136] -----+----- \--* ADD long [000134] #----+----- +--* IND long [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X-+----- * NULLCHECK byte [000140] -----+----- \--* LCL_VAR ref V13 tmp12 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 [000130] ---XG+----- \--* IND ref [000147] ----G+----- \--* ADD byref [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- | \--* ADD byref [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 [000234] -----+----- | \--* CNS_INT long 16 [000146] -----+----- \--* LSH long [000144] -----+----- +--* CAST long <- int [000126] -----+----- | \--* LCL_VAR int V06 tmp5 [000145] -----+----- \--* CNS_INT long 5 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000047] -----+----- \--* CNS_INT long 0 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG+----- * JTRUE void [000151] J--XG+-N--- \--* EQ int [000150] ---XG+----- +--* IND int [000238] -----+----- | \--* ADD byref [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000050] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG+----- * JTRUE void [000160] J--XG+-N--- \--* NE int [000158] ---XG+----- +--* IND int [000240] -----+----- | \--* ADD byref [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000159] -----+----- \--* CNS_INT int 0 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] -A-XG+----- * STOREIND int [000246] -----+----- +--* ADD byref [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000171] -----+----- \--* CNS_INT int 0 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG+----- \--* ADD int [000204] -A-XG+----- +--* XADD int [000251] -----+----- | +--* ADD byref [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] [000203] -----+----- | \--* CNS_INT int -1 [000205] -----+----- \--* CNS_INT int -1 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 [000209] -----+----- \--* LCL_VAR int V17 tmp16 ***** BB15 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 [000253] -----+----- \--* LCL_VAR int V19 tmp18 ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] -----+----- * JTRUE void [000218] N----+-N-U- \--* LT int [000216] -----+----- +--* LCL_VAR int V17 tmp16 [000217] -----+----- \--* CNS_INT int 128 ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] -A-XG+----- * STOREIND int [000242] -----+----- +--* ADD byref [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000167] ---XG+----- \--* ADD int [000165] ---XG+----- +--* IND int [000244] -----+----- | \--* ADD byref [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000166] -----+----- \--* CNS_INT int -1 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000092] -----+----- \--* CNS_INT byref 0 ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) [000002] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Unroll loops Analyzing iteration for L00 with header BB04 Preheader = BB03 Checking exiting block BB04 Could not extract an IV Checking exiting block BB05 Could not extract an IV Checking exiting block BB09 Could not extract an IV Could not find any IV *************** In fgDebugCheckBBlist *************** Finishing PHASE Unroll loops [no changes] *************** Starting PHASE Compute dominators *************** Finishing PHASE Compute dominators [no changes] *************** Starting PHASE Morph array ops No multi-dimensional array references in the function *************** Finishing PHASE Morph array ops [no changes] *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** *** marking local variables in block BB01 (weight=1) STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000097] -----+----- * JTRUE void [000096] J----+-N--- \--* NE int [000000] -----+----- +--* LCL_VAR ref V00 arg0 [000095] -----+----- \--* CNS_INT ref null New refCnts for V00: refCnt = 1, refCntWtd = 1 *** marking local variables in block BB02 (weight=0.50) STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' *** marking local variables in block BB03 (weight=1) STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 [000104] n-C-G+----- \--* IND int [000103] --C-G+----- \--* ADD byref [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] New refCnts for V02: refCnt = 1, refCntWtd = 1 V02 needs explicit zero init. Disqualified as a single-def register candidate. STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 [000014] -----+----- \--* OR int [000008] -----+----- +--* LCL_VAR int V02 tmp1 [000013] -----+----- \--* RSH int [000011] -----+----- +--* ADD int [000009] -----+----- | +--* LCL_VAR int V02 tmp1 [000010] -----+----- | \--* CNS_INT int -1 [000012] -----+----- \--* CNS_INT int 31 New refCnts for V02: refCnt = 2, refCntWtd = 2 New refCnts for V02: refCnt = 3, refCntWtd = 3 New refCnts for V02: refCnt = 4, refCntWtd = 4 STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 [000226] ---X-+-N--- \--* COMMA ref [000224] ---X-+----- +--* NULLCHECK byte [000223] -----+----- | \--* LCL_VAR ref V00 arg0 [000225] -----+----- \--* LCL_VAR ref V00 arg0 New refCnts for V03: refCnt = 1, refCntWtd = 1 Marking EH Var V03 as a register candidate. New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 3, refCntWtd = 3 STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 [000111] -A---+----- \--* ADD long [000230] -A---+----- +--* COMMA long [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 [000228] -----+----- | \--* LCL_VAR long V20 tmp19 [000110] -----+----- \--* CNS_INT long -4 New refCnts for V04: refCnt = 1, refCntWtd = 1 V04 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V20: refCnt = 1, refCntWtd = 2 V20 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V20: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB04 (weight=8) STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 [000026] ---XG+----- \--* IND int [000025] -----+----- \--* LCL_VAR long V04 tmp3 New refCnts for V05: refCnt = 1, refCntWtd = 8 V05 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V04: refCnt = 2, refCntWtd = 9 STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] [000034] -----+----- * JTRUE void [000033] N----+-N-U- \--* NE int [000031] -----+----- +--* CAST int <- ushort <- int [000028] -----+----- | \--* LCL_VAR int V05 tmp4 [000032] -----+----- \--* LCL_VAR int V02 tmp1 New refCnts for V05: refCnt = 2, refCntWtd = 16 New refCnts for V02: refCnt = 5, refCntWtd = 12 *** marking local variables in block BB05 (weight=4) STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] [000064] -----+----- * JTRUE void [000063] J----+-N--- \--* NE int [000061] -----+----- +--* AND int [000059] -----+----- | +--* LCL_VAR int V05 tmp4 [000060] -----+----- | \--* CNS_INT int 0x8000000 [000062] -----+----- \--* CNS_INT int 0 New refCnts for V05: refCnt = 3, refCntWtd = 20 *** marking local variables in block BB06 (weight=4) STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] [000070] -----+----- * JTRUE void [000069] J----+-N--- \--* NE int [000067] -----+----- +--* AND int [000065] -----+----- | +--* LCL_VAR int V05 tmp4 [000066] -----+----- | \--* CNS_INT int 0x3F0000 [000068] -----+----- \--* CNS_INT int 0 New refCnts for V05: refCnt = 4, refCntWtd = 24 *** marking local variables in block BB07 (weight=2) STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000087] -----+----- \--* AND int [000085] -----+----- +--* LCL_VAR int V05 tmp4 [000086] -----+----- \--* CNS_INT int -0x10000 New refCnts for V09: refCnt = 1, refCntWtd = 2 V09 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V05: refCnt = 5, refCntWtd = 26 *** marking local variables in block BB08 (weight=2) STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 [000073] -----+----- \--* ADD int [000071] -----+----- +--* LCL_VAR int V05 tmp4 [000072] -----+----- \--* CNS_INT int -0x10000 New refCnts for V09: refCnt = 2, refCntWtd = 4 New refCnts for V05: refCnt = 6, refCntWtd = 28 *** marking local variables in block BB09 (weight=4) STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] [000084] -A-XG+----- * JTRUE void [000083] NA-XG+-N-U- \--* NE int [000081] -A-XG+----- +--* CMPXCHG int [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 [000076] -----+----- | +--* LCL_VAR int V09 tmp8 [000080] -----+----- | \--* LCL_VAR int V05 tmp4 [000082] -----+----- \--* LCL_VAR int V05 tmp4 New refCnts for V04: refCnt = 3, refCntWtd = 13 New refCnts for V09: refCnt = 3, refCntWtd = 8 New refCnts for V05: refCnt = 7, refCntWtd = 32 New refCnts for V05: refCnt = 8, refCntWtd = 36 *** marking local variables in block BB10 (weight=0.50) STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 [000115] -----+----- \--* AND int [000035] -----+----- +--* LCL_VAR int V05 tmp4 [000114] -----+----- \--* CNS_INT int 0x3FFFFFF New refCnts for V06: refCnt = 1, refCntWtd = 0.50 V06 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V05: refCnt = 9, refCntWtd = 36.50 STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] [000041] -----+----- * JTRUE void [000124] J----+-N--- \--* EQ int [000122] -----+----- +--* AND int [000117] -----+----- | +--* LCL_VAR int V05 tmp4 [000121] -----+----- | \--* CNS_INT int 0xC000000 [000123] -----+----- \--* CNS_INT int 0x8000000 New refCnts for V05: refCnt = 10, refCntWtd = 37 *** marking local variables in block BB11 (weight=0) STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class New refCnts for V08: refCnt = 1, refCntWtd = 0 Marking EH Var V08 as a register candidate. STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 New refCnts for V08: refCnt = 2, refCntWtd = 0 STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 New refCnts for V08: refCnt = 3, refCntWtd = 0 *** marking local variables in block BB12 (weight=0.50) STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 [000042] -----+----- \--* LCL_VAR int V06 tmp5 New refCnts for V12: refCnt = 1, refCntWtd = 1 V12 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V06: refCnt = 2, refCntWtd = 1 STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 [000137] ---XG+----- \--* IND ref [000136] -----+----- \--* ADD long [000134] #----+----- +--* IND long [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] New refCnts for V13: refCnt = 1, refCntWtd = 1 Marking EH Var V13 as a register candidate. STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] [000141] ---X-+----- * NULLCHECK byte [000140] -----+----- \--* LCL_VAR ref V13 tmp12 New refCnts for V13: refCnt = 2, refCntWtd = 2 STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 [000130] ---XG+----- \--* IND ref [000147] ----G+----- \--* ADD byref [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] [000235] -----+----- | \--* ADD byref [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 [000234] -----+----- | \--* CNS_INT long 16 [000146] -----+----- \--* LSH long [000144] -----+----- +--* CAST long <- int [000126] -----+----- | \--* LCL_VAR int V06 tmp5 [000145] -----+----- \--* CNS_INT long 5 New refCnts for V07: refCnt = 1, refCntWtd = 0.50 Marking EH Var V07 as a register candidate. New refCnts for V13: refCnt = 3, refCntWtd = 3 New refCnts for V06: refCnt = 3, refCntWtd = 1.50 STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000047] -----+----- \--* CNS_INT long 0 New refCnts for V03: refCnt = 3, refCntWtd = 2.50 V03 has multiple definitions. Disqualified as a single-def register candidate. STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000152] ---XG+----- * JTRUE void [000151] J--XG+-N--- \--* EQ int [000150] ---XG+----- +--* IND int [000238] -----+----- | \--* ADD byref [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000050] -----+----- \--* LCL_VAR int V02 tmp1 New refCnts for V07: refCnt = 2, refCntWtd = 1 New refCnts for V02: refCnt = 6, refCntWtd = 12.50 *** marking local variables in block BB13 (weight=0.50) STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() *** marking local variables in block BB14 (weight=0.50) STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000161] ---XG+----- * JTRUE void [000160] J--XG+-N--- \--* NE int [000158] ---XG+----- +--* IND int [000240] -----+----- | \--* ADD byref [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000159] -----+----- \--* CNS_INT int 0 New refCnts for V07: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB15 (weight=0.50) STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000173] -A-XG+----- * STOREIND int [000246] -----+----- +--* ADD byref [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] [000171] -----+----- \--* CNS_INT int 0 New refCnts for V07: refCnt = 4, refCntWtd = 2 STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 [000206] -A-XG+----- \--* ADD int [000204] -A-XG+----- +--* XADD int [000251] -----+----- | +--* ADD byref [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] [000203] -----+----- | \--* CNS_INT int -1 [000205] -----+----- \--* CNS_INT int -1 New refCnts for V17: refCnt = 1, refCntWtd = 1 V17 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V07: refCnt = 5, refCntWtd = 2.50 STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 [000209] -----+----- \--* LCL_VAR int V17 tmp16 New refCnts for V19: refCnt = 1, refCntWtd = 0.50 V19 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V17: refCnt = 2, refCntWtd = 2 STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 [000253] -----+----- \--* LCL_VAR int V19 tmp18 New refCnts for V18: refCnt = 1, refCntWtd = 0.50 V18 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V19: refCnt = 2, refCntWtd = 1 STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000183] -----+----- * JTRUE void [000218] N----+-N-U- \--* LT int [000216] -----+----- +--* LCL_VAR int V17 tmp16 [000217] -----+----- \--* CNS_INT int 128 New refCnts for V17: refCnt = 3, refCntWtd = 3 *** marking local variables in block BB16 (weight=0.50) STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 New refCnts for V07: refCnt = 6, refCntWtd = 3 New refCnts for V19: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB17 (weight=0.50) STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] [000169] -A-XG+----- * STOREIND int [000242] -----+----- +--* ADD byref [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000167] ---XG+----- \--* ADD int [000165] ---XG+----- +--* IND int [000244] -----+----- | \--* ADD byref [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] [000166] -----+----- \--* CNS_INT int -1 New refCnts for V07: refCnt = 7, refCntWtd = 3.50 New refCnts for V07: refCnt = 8, refCntWtd = 4 *** marking local variables in block BB18 (weight=0.25) *** marking local variables in block BB19 (weight=1) STMT00028 ( 0x000[E-] ... ??? ) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 [000092] -----+----- \--* CNS_INT byref 0 New refCnts for V03: refCnt = 4, refCntWtd = 3.50 STMT00001 ( 0x006[E-] ... ??? ) [000002] -----+----- * RETURN void *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 4, refCntWtd = 4 New refCnts for V00: refCnt = 5, refCntWtd = 5 *************** Finishing PHASE Mark local vars [no changes] *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order Trees after Find oper order --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] ( 5, 6) [000097] -----+----- * JTRUE void ( 3, 4) [000096] J----+-N--- \--* NE int ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 17, 4) [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 ( 17, 4) [000104] n-C-G+----- \--* IND int ( 16, 5) [000103] --C-G+-N--- \--* ADD byref ( 14, 2) [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 ( 7, 9) [000014] -----+----- \--* OR int ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 ( 5, 7) [000013] -----+----- \--* RSH int ( 3, 4) [000011] -----+----- +--* ADD int ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 3, 3) [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 ( 3, 3) [000226] ---X-+-N--- \--* COMMA ref ( 2, 2) [000224] ---X-+----- +--* NULLCHECK byte ( 1, 1) [000223] -----+----- | \--* LCL_VAR ref V00 arg0 ( 1, 1) [000225] -----+----- \--* LCL_VAR ref V00 arg0 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 ( 4, 7) [000111] -A---+----- \--* ADD long ( 2, 4) [000230] -A---+----- +--* COMMA long ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 ( 3, 2) [000026] ---XG+----- \--* IND int ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 6, 7) [000034] -----+----- * JTRUE void ( 4, 5) [000033] N----+-N-U- \--* NE int ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 7, 11) [000064] -----+----- * JTRUE void ( 5, 9) [000063] J----+-N--- \--* NE int ( 3, 6) [000061] -----+----- +--* AND int ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 7, 9) [000070] -----+----- * JTRUE void ( 5, 7) [000069] J----+-N--- \--* NE int ( 3, 4) [000067] -----+----- +--* AND int ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 ( 3, 4) [000087] -----+----- \--* AND int ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 ( 3, 4) [000073] -----+----- \--* ADD int ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] (255, 12) [000084] -A-XG+----- * JTRUE void (255, 10) [000083] NA-XG+-N-U- \--* NE int (255, 8) [000081] -A-XG+----- +--* CMPXCHG int ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 ( 3, 6) [000115] -----+----- \--* AND int ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 7, 13) [000041] -----+----- * JTRUE void ( 5, 11) [000124] J----+-N--- \--* EQ int ( 3, 6) [000122] -----+----- +--* AND int ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 7, 5) [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 ( 3, 2) [000042] -----+----- \--* LCL_VAR int V06 tmp5 ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 ( 8, 12) [000137] ---XG+----- \--* IND ref ( 7, 13) [000136] -----+-N--- \--* ADD long ( 5, 10) [000134] #----+----- +--* IND long ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] ( 2, 2) [000141] ---X-+----- * NULLCHECK byte ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 ( 11, 14) [000130] ---XG+----- \--* IND ref ( 9, 13) [000147] ----G+-N--- \--* ADD byref ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] ( 2, 5) [000235] -----+-N--- | \--* ADD byref ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 ( 6, 7) [000146] -----+----- \--* LSH long ( 4, 4) [000144] -----+----- +--* CAST long <- int ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] ( 8, 7) [000152] ---XG+----- * JTRUE void ( 6, 5) [000151] J--XG+-N--- \--* EQ int ( 4, 3) [000150] ---XG+----- +--* IND int ( 3, 4) [000238] -----+-N--- | \--* ADD byref ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] ( 8, 8) [000161] ---XG+----- * JTRUE void ( 6, 6) [000160] J--XG+-N--- \--* NE int ( 4, 3) [000158] ---XG+----- +--* IND int ( 3, 4) [000240] -----+-N--- | \--* ADD byref ( 1, 1) [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 ( 1, 2) [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] ( 1, 2) [000159] -----+----- \--* CNS_INT int 0 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] ( 6, 6) [000173] -A-XG+----- * STOREIND int ( 3, 4) [000246] -----+-N--- +--* ADD byref ( 1, 1) [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 ( 1, 2) [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] ( 1, 2) [000171] -----+----- \--* CNS_INT int 0 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 ( 7, 10) [000206] -A-XG+----- \--* ADD int ( 5, 7) [000204] -A-XG+----- +--* XADD int ( 3, 4) [000251] -----+----- | +--* ADD byref ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 ***** BB15 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] ( 7, 5) [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 ( 3, 2) [000253] -----+----- \--* LCL_VAR int V19 tmp18 ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] ( 5, 6) [000183] -----+----- * JTRUE void ( 3, 4) [000218] N----+-N-U- \--* LT int ( 1, 1) [000216] -----+----- +--* LCL_VAR int V17 tmp16 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] ( 11, 10) [000169] -A-XG+--R-- * STOREIND int ( 3, 4) [000242] -----+-N--- +--* ADD byref ( 1, 1) [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 ( 1, 2) [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] ( 6, 6) [000167] ---XG+----- \--* ADD int ( 4, 3) [000165] ---XG+----- +--* IND int ( 3, 4) [000244] -----+-N--- | \--* ADD byref ( 1, 1) [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 ( 1, 2) [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] ( 1, 2) [000166] -----+----- \--* CNS_INT int -1 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) ( 0, 0) [000002] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Set block order *************** In fgSetBlockOrder() Found a cycle that does not go through a GC safe point: BB04 <- BB09 <- BB07 <- BB06 <- BB05 <- BB04 Marking method as fully interruptible The biggest BB has 11 tree nodes *************** Finishing PHASE Set block order Trees after Set block order --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000097] -----+----- * JTRUE void N003 ( 3, 4) [000096] J----+-N--- \--* NE int N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 17, 4) [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 N004 ( 17, 4) [000104] n-C-G+----- \--* IND int N003 ( 16, 5) [000103] --C-G+-N--- \--* ADD byref N001 ( 14, 2) [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 3, 3) [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 N004 ( 3, 3) [000226] ---X-+-N--- \--* COMMA ref N002 ( 2, 2) [000224] ---X-+----- +--* NULLCHECK byte N001 ( 1, 1) [000223] -----+----- | \--* LCL_VAR ref V00 arg0 N003 ( 1, 1) [000225] -----+----- \--* LCL_VAR ref V00 arg0 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 N006 ( 4, 7) [000111] -A---+----- \--* ADD long N004 ( 2, 4) [000230] -A---+----- +--* COMMA long N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 7) [000034] -----+----- * JTRUE void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 11) [000064] -----+----- * JTRUE void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 9) [000070] -----+----- * JTRUE void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 (255, 12) [000084] -A-XG+----- * JTRUE void N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 13) [000041] -----+----- * JTRUE void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 7, 5) [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 N001 ( 3, 2) [000042] -----+----- \--* LCL_VAR int V06 tmp5 ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long N002 ( 5, 10) [000134] #----+----- +--* IND long N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 8) [000161] ---XG+----- * JTRUE void N006 ( 6, 6) [000160] J--XG+-N--- \--* NE int N004 ( 4, 3) [000158] ---XG+----- +--* IND int N003 ( 3, 4) [000240] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 N002 ( 1, 2) [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] N005 ( 1, 2) [000159] -----+----- \--* CNS_INT int 0 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N005 ( 6, 6) [000173] -A-XG+----- * STOREIND int N003 ( 3, 4) [000246] -----+-N--- +--* ADD byref N001 ( 1, 1) [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 N002 ( 1, 2) [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] N004 ( 1, 2) [000171] -----+----- \--* CNS_INT int 0 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 ***** BB15 [0029] STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 7, 5) [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 N001 ( 3, 2) [000253] -----+----- \--* LCL_VAR int V19 tmp18 ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000183] -----+----- * JTRUE void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V17 tmp16 N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N010 ( 11, 10) [000169] -A-XG+--R-- * STOREIND int N009 ( 3, 4) [000242] -----+-N--- +--* ADD byref N007 ( 1, 1) [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 N008 ( 1, 2) [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] N006 ( 6, 6) [000167] ---XG+----- \--* ADD int N004 ( 4, 3) [000165] ---XG+----- +--* IND int N003 ( 3, 4) [000244] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 N002 ( 1, 2) [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] N005 ( 1, 2) [000166] -----+----- \--* CNS_INT int -1 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) N001 ( 0, 0) [000002] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Build SSA representation *************** In SsaBuilder::Build() *************** In fgLocalVarLiveness() In fgLocalVarLivenessInit Local V01 should not be enregistered because: struct size does not match reg size Tracked variable (14 out of 21) table: V05 tmp4 [ int]: refCnt = 10, refCntWtd = 37 V04 tmp3 [ long]: refCnt = 3, refCntWtd = 13 V02 tmp1 [ int]: refCnt = 6, refCntWtd = 12.50 V09 tmp8 [ int]: refCnt = 3, refCntWtd = 8 V00 arg0 [ ref]: refCnt = 5, refCntWtd = 5 V07 tmp6 [ ref]: refCnt = 8, refCntWtd = 4 V20 tmp19 [ long]: refCnt = 2, refCntWtd = 4 V13 tmp12 [ ref]: refCnt = 3, refCntWtd = 3 V17 tmp16 [ int]: refCnt = 3, refCntWtd = 3 V06 tmp5 [ int]: refCnt = 3, refCntWtd = 1.50 V19 tmp18 [ int]: refCnt = 3, refCntWtd = 1.50 V12 tmp11 [ int]: refCnt = 1, refCntWtd = 1 V18 tmp17 [ int]: refCnt = 1, refCntWtd = 0.50 V08 tmp7 [ ref]: refCnt = 3, refCntWtd = 0 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V00} DEF(0)={ } BB02 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB03 USE(1)={ V00 } + ByrefExposed + GcHeap DEF(3)={V04 V02 V20} BB04 USE(2)={ V04 V02} + ByrefExposed + GcHeap DEF(1)={V05 } BB05 USE(1)={V05} DEF(0)={ } BB06 USE(1)={V05} DEF(0)={ } BB07 USE(1)={V05 } DEF(1)={ V09} BB08 USE(1)={V05 } DEF(1)={ V09} BB09 USE(3)={V05 V04 V09} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB10 USE(1)={V05 } DEF(1)={ V06} BB11 USE(0)={ } + ByrefExposed + GcHeap DEF(1)={V08} + ByrefExposed* + GcHeap* BB12 USE(2)={V02 V06 } + ByrefExposed + GcHeap DEF(3)={ V07 V13 V12} BB13 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB14 USE(1)={V07} + ByrefExposed + GcHeap DEF(0)={ } BB15 USE(1)={V07 } + ByrefExposed + GcHeap DEF(3)={ V17 V19 V18} + ByrefExposed* + GcHeap* BB16 USE(2)={V07 V19} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB17 USE(1)={V07} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed + GcHeap BB18 USE(0)={} DEF(0)={} BB19 USE(0)={} DEF(0)={} ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (1)={V00} + ByrefExposed + GcHeap OUT(1)={V00} + ByrefExposed + GcHeap BB02 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} BB03 IN (1)={ V00} + ByrefExposed + GcHeap OUT(2)={V04 V02 } + ByrefExposed + GcHeap BB04 IN (2)={ V04 V02} + ByrefExposed + GcHeap OUT(3)={V05 V04 V02} + ByrefExposed + GcHeap BB05 IN (3)={V05 V04 V02} + ByrefExposed + GcHeap OUT(3)={V05 V04 V02} + ByrefExposed + GcHeap BB06 IN (3)={V05 V04 V02} + ByrefExposed + GcHeap OUT(3)={V05 V04 V02} + ByrefExposed + GcHeap BB07 IN (3)={V05 V04 V02 } + ByrefExposed + GcHeap OUT(4)={V05 V04 V02 V09} + ByrefExposed + GcHeap BB08 IN (3)={V05 V04 V02 } + ByrefExposed + GcHeap OUT(4)={V05 V04 V02 V09} + ByrefExposed + GcHeap BB09 IN (4)={V05 V04 V02 V09} + ByrefExposed + GcHeap OUT(2)={ V04 V02 } + ByrefExposed + GcHeap BB10 IN (2)={V05 V02 } + ByrefExposed + GcHeap OUT(2)={ V02 V06} + ByrefExposed + GcHeap BB11 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} BB12 IN (2)={V02 V06} + ByrefExposed + GcHeap OUT(1)={ V07 } + ByrefExposed + GcHeap BB13 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} BB14 IN (1)={V07} + ByrefExposed + GcHeap OUT(1)={V07} + ByrefExposed + GcHeap BB15 IN (1)={V07 } + ByrefExposed + GcHeap OUT(2)={V07 V19} + ByrefExposed + GcHeap BB16 IN (2)={V07 V19} + ByrefExposed + GcHeap OUT(0)={ } BB17 IN (1)={V07} + ByrefExposed + GcHeap OUT(0)={ } BB18 IN (0)={} OUT(0)={} BB19 IN (0)={} OUT(0)={} top level store removing stmt with no side effects removing useless STMT00034 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 7, 5) [000131] DA---+----- * STORE_LCL_VAR int V12 tmp11 N001 ( 3, 2) [000042] -----+----- \--* LCL_VAR int V06 tmp5 from BB12 top level store removing stmt with no side effects removing useless STMT00044 ( INL11 @ 0x00F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 7, 5) [000254] DA---+----- * STORE_LCL_VAR int V18 tmp17 N001 ( 3, 2) [000253] -----+----- \--* LCL_VAR int V19 tmp18 from BB15 *************** In optRemoveRedundantZeroInits() Analyzing BB01 *************** In SsaBuilder::InsertPhiFunctions() Inserting phi functions: Inserting phi definition for ByrefExposed at start of BB04. Added PHI definition for V09 at start of BB09. *************** In SsaBuilder::RenameVariables() V00.1: defined in BB00 3 uses (global) V02.1: defined in BB03 2 uses (local) V02.2: defined in BB03 2 uses (global) V04.1: defined in BB03 2 uses (global) V05.1: defined in BB04 9 uses (global) V06.1: defined in BB10 1 uses (global) V07.1: defined in BB00 0 uses (local) V07.2: defined in BB12 7 uses (global) V08.1: defined in BB00 0 uses (local) V08.2: defined in BB11 2 uses (local) V09.1: defined in BB08 1 uses (global), has phi uses V09.2: defined in BB07 1 uses (global), has phi uses V09.3: defined in BB09 1 uses (local) V12: in SSA but no defs V13.1: defined in BB00 0 uses (local) V13.2: defined in BB12 2 uses (local) V17.1: defined in BB15 2 uses (local) V18: in SSA but no defs V19.1: defined in BB15 1 uses (global) V20.1: defined in BB03 1 uses (local) *************** Finishing PHASE Build SSA representation Trees after Build SSA representation --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} SSA MEM: ByrefExposed, GcHeap = m:1 ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000097] -----+----- * JTRUE void N003 ( 3, 4) [000096] J----+-N--- \--* NE int N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 u:1 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null SSA MEM: ByrefExposed, GcHeap = m:1 ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} SSA MEM: ByrefExposed, GcHeap = m:1 ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' SSA MEM: ByrefExposed, GcHeap = m:9 ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} SSA MEM: ByrefExposed, GcHeap = m:1 ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 17, 4) [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 d:1 N004 ( 17, 4) [000104] n-C-G+----- \--* IND int N003 ( 16, 5) [000103] --C-G+-N--- \--* ADD byref N001 ( 14, 2) [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 u:1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 3, 3) [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 N004 ( 3, 3) [000226] ---X-+-N--- \--* COMMA ref N002 ( 2, 2) [000224] ---X-+----- +--* NULLCHECK byte N001 ( 1, 1) [000223] -----+----- | \--* LCL_VAR ref V00 arg0 u:1 N003 ( 1, 1) [000225] -----+----- \--* LCL_VAR ref V00 arg0 u:1 (last use) ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 N006 ( 4, 7) [000111] -A---+----- \--* ADD long N004 ( 2, 4) [000230] -A---+----- +--* COMMA long N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 d:1 N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 u:1 (last use) N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 SSA MEM: ByrefExposed, GcHeap = m:1 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} SSA MEM: ByrefExposed, GcHeap = phi(m:3, m:1) ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 7) [000034] -----+----- * JTRUE void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 11) [000064] -----+----- * JTRUE void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 9) [000070] -----+----- * JTRUE void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB09 [0007] STMT00055 ( ??? ... ??? ) N004 ( 0, 0) [000256] DA--------- * STORE_LCL_VAR int V09 tmp8 d:3 N003 ( 0, 0) [000255] ----------- \--* PHI int N001 ( 0, 0) [000258] ----------- pred BB07 +--* PHI_ARG int V09 tmp8 u:2 N002 ( 0, 0) [000257] ----------- pred BB08 \--* PHI_ARG int V09 tmp8 u:1 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 (255, 12) [000084] -A-XG+----- * JTRUE void N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 u:1 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 u:3 (last use) N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 u:1 (last use) SSA MEM: ByrefExposed, GcHeap = m:3 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 13) [000041] -----+----- * JTRUE void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 u:2 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 u:2 (last use) SSA MEM: ByrefExposed, GcHeap = m:8 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long N002 ( 5, 10) [000134] #----+----- +--* IND long N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 u:2 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 u:1 (last use) N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() SSA MEM: ByrefExposed, GcHeap = m:7 ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 8) [000161] ---XG+----- * JTRUE void N006 ( 6, 6) [000160] J--XG+-N--- \--* NE int N004 ( 4, 3) [000158] ---XG+----- +--* IND int N003 ( 3, 4) [000240] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] N005 ( 1, 2) [000159] -----+----- \--* CNS_INT int 0 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N005 ( 6, 6) [000173] -A-XG+----- * STOREIND int N003 ( 3, 4) [000246] -----+-N--- +--* ADD byref N001 ( 1, 1) [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] N004 ( 1, 2) [000171] -----+----- \--* CNS_INT int 0 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000183] -----+----- * JTRUE void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V17 tmp16 u:1 (last use) N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 SSA MEM: ByrefExposed, GcHeap = m:5 ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} SSA MEM: ByrefExposed, GcHeap = m:5 ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 u:1 (last use) SSA MEM: ByrefExposed, GcHeap = m:6 ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N010 ( 11, 10) [000169] -A-XG+--R-- * STOREIND int N009 ( 3, 4) [000242] -----+-N--- +--* ADD byref N007 ( 1, 1) [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N008 ( 1, 2) [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] N006 ( 6, 6) [000167] ---XG+----- \--* ADD int N004 ( 4, 3) [000165] ---XG+----- +--* IND int N003 ( 3, 4) [000244] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] N005 ( 1, 2) [000166] -----+----- \--* CNS_INT int -1 SSA MEM: ByrefExposed, GcHeap = m:4 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} SSA MEM: ByrefExposed, GcHeap = m:3 SSA MEM: ByrefExposed, GcHeap = m:3 ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) N001 ( 0, 0) [000002] -----+----- * RETURN void SSA MEM: ByrefExposed, GcHeap = m:2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist SSA checks completed successfully [deferred prior check failed -- skipping this check] *************** Starting PHASE Early Value Propagation Optimized 0 trees *************** Finishing PHASE Early Value Propagation [no changes] *************** Starting PHASE Do value numbering *************** In fgValueNumber() optComputeLoopSideEffectsOfBlock BB04, mostNestedLoop L00 optComputeLoopSideEffectsOfBlock BB05, mostNestedLoop L00 optComputeLoopSideEffectsOfBlock BB06, mostNestedLoop L00 optComputeLoopSideEffectsOfBlock BB08, mostNestedLoop L00 optComputeLoopSideEffectsOfBlock BB07, mostNestedLoop L00 optComputeLoopSideEffectsOfBlock BB09, mostNestedLoop L00 Memory Initial Value in BB01 is: $c0 Visiting BB01 The SSA definition for ByrefExposed (#1) at start of BB01 is $c0 {InitVal($41)} The SSA definition for GcHeap (#1) at start of BB01 is $c0 {InitVal($41)} ***** BB01, STMT00029(before) N004 ( 5, 6) [000097] -----+----- * JTRUE void N003 ( 3, 4) [000096] J----+-N--- \--* NE int N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 u:1 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null N001 [000000] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)} N002 [000095] CNS_INT null => $VN.Null N003 [000096] NE => $100 {NE($80, $0)} N004 [000097] JTRUE => $VN.Void ***** BB01, STMT00029(after) N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000096] J----+-N--- \--* NE int $100 N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null $VN.Null Visiting BB03 Reachable through pred BB01 The SSA definition for ByrefExposed (#1) at start of BB03 is $c0 {InitVal($41)} The SSA definition for GcHeap (#1) at start of BB03 is $c0 {InitVal($41)} ***** BB03, STMT00004(before) N005 ( 17, 4) [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 d:1 N004 ( 17, 4) [000104] n-C-G+----- \--* IND int N003 ( 16, 5) [000103] --C-G+-N--- \--* ADD byref N001 ( 14, 2) [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] N001 [000101] CALL help => $180 {ReadyToRunStaticBaseThreadNoctor($140)} N002 [000102] CNS_INT 40 Fseq[t_currentManagedThreadId] => $1c0 {LngCns 40} N003 [000103] ADD => $200 {ADD($180, $1c0)} VNForHandle(t_currentManagedThreadId) is $141, fieldType is int, size = 4 VNForMapSelect($c0, $141):int returns $101 {$c0[$141]} N004 [000104] IND => Tree [000007] assigned VN to local var V02/1: N005 [000007] STORE_LCL_VAR V02 tmp1 d:1 => $VN.Void ***** BB03, STMT00004(after) N005 ( 17, 4) [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void N004 ( 17, 4) [000104] n-C-G+----- \--* IND int N003 ( 16, 5) [000103] --C-G+-N--- \--* ADD byref $200 N001 ( 14, 2) [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR $180 N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] $1c0 --------- ***** BB03, STMT00005(before) N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 u:1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 N001 [000008] LCL_VAR V02 tmp1 u:1 => N002 [000009] LCL_VAR V02 tmp1 u:1 (last use) => N003 [000010] CNS_INT -1 => $41 {IntCns -1} N004 [000011] ADD => N005 [000012] CNS_INT 31 => $42 {IntCns 31} N006 [000013] RSH => N007 [000014] OR => Tree [000015] assigned VN to local var V02/2: N008 [000015] STORE_LCL_VAR V02 tmp1 d:2 => $VN.Void ***** BB03, STMT00005(after) N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 u:1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 $41 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 $42 --------- ***** BB03, STMT00007(before) N005 ( 3, 3) [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 N004 ( 3, 3) [000226] ---X-+-N--- \--* COMMA ref N002 ( 2, 2) [000224] ---X-+----- +--* NULLCHECK byte N001 ( 1, 1) [000223] -----+----- | \--* LCL_VAR ref V00 arg0 u:1 N003 ( 1, 1) [000225] -----+----- \--* LCL_VAR ref V00 arg0 u:1 (last use) N001 [000223] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)} N002 [000224] NULLCHECK => $281 {norm=$VN.Void, exc=$280 {NullPtrExc($80)}} N003 [000225] LCL_VAR V00 arg0 u:1 (last use) => $80 {InitVal($40)} N004 [000226] COMMA => $282 {norm=$80 {InitVal($40)}, exc=$280 {NullPtrExc($80)}} Tree [000019] assigns to non-address-taken local V03; excluded from SSA, so value not tracked N005 [000019] STORE_LCL_VAR V03 tmp2 => $281 {norm=$VN.Void, exc=$280 {NullPtrExc($80)}} ***** BB03, STMT00007(after) N005 ( 3, 3) [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 $281 N004 ( 3, 3) [000226] ---X-+-N--- \--* COMMA ref $282 N002 ( 2, 2) [000224] ---X-+----- +--* NULLCHECK byte $281 N001 ( 1, 1) [000223] -----+----- | \--* LCL_VAR ref V00 arg0 u:1 $80 N003 ( 1, 1) [000225] -----+----- \--* LCL_VAR ref V00 arg0 u:1 (last use) $80 --------- ***** BB03, STMT00009(before) N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 N006 ( 4, 7) [000111] -A---+----- \--* ADD long N004 ( 2, 4) [000230] -A---+----- +--* COMMA long N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 d:1 N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 u:1 (last use) N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 N001 [000020] LCL_VAR V03 tmp2 => $182 {MemOpaque:NotInLoop} Tree [000227] assigned VN to local var V20/1: $2c0 {$182, long <- byref} N002 [000227] STORE_LCL_VAR V20 tmp19 d:1 => $VN.Void N003 [000228] LCL_VAR V20 tmp19 u:1 (last use) => $2c0 {$182, long <- byref} N004 [000230] COMMA => $2c0 {$182, long <- byref} N005 [000110] CNS_INT -4 => $1c1 {LngCns -4} N006 [000111] ADD => $2c1 {ADD($1c1, $2c0)} Tree [000024] assigned VN to local var V04/1: $2c1 {ADD($1c1, $2c0)} N007 [000024] STORE_LCL_VAR V04 tmp3 d:1 => $VN.Void ***** BB03, STMT00009(after) N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void N006 ( 4, 7) [000111] -A---+----- \--* ADD long $2c1 N004 ( 2, 4) [000230] -A---+----- +--* COMMA long $2c0 N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 $182 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 $1c1 Visiting BB04 Reachable through pred BB09 Computing GcHeap state for block BB04, entry block for loop L00: Loop L00 has memory havoc effect; heap state is new unique $c1. The SSA definition for GcHeap (#2) at start of BB04 is $c1 {MemOpaque:L00} ***** BB04, STMT00010(before) N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 N001 [000025] LCL_VAR V04 tmp3 u:1 => $2c1 {ADD($1c1, $2c0)} N002 [000026] IND => Tree [000027] assigned VN to local var V05/1: N003 [000027] STORE_LCL_VAR V05 tmp4 d:1 => $284 {norm=$VN.Void, exc=$283 {NullPtrExc($2c1)}} ***** BB04, STMT00010(after) N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 $2c1 --------- ***** BB04, STMT00011(before) N005 ( 6, 7) [000034] -----+----- * JTRUE void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 N001 [000028] LCL_VAR V05 tmp4 u:1 => N002 [000031] CAST => N003 [000032] LCL_VAR V02 tmp1 u:2 => N004 [000033] NE => N005 [000034] JTRUE => $VN.Void ***** BB04, STMT00011(after) N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 Visiting BB05 Reachable through pred BB04 The SSA definition for ByrefExposed (#2) at start of BB05 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB05 is $c1 {MemOpaque:L00} ***** BB05, STMT00021(before) N006 ( 7, 11) [000064] -----+----- * JTRUE void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 N001 [000059] LCL_VAR V05 tmp4 u:1 => N002 [000060] CNS_INT 0x8000000 => $46 {IntCns 0x8000000} N003 [000061] AND => N004 [000062] CNS_INT 0 => $40 {IntCns 0} N005 [000063] NE => N006 [000064] JTRUE => $VN.Void ***** BB05, STMT00021(after) N006 ( 7, 11) [000064] -----+----- * JTRUE void $VN.Void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 $46 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 $40 Visiting BB06 Reachable through pred BB05 The SSA definition for ByrefExposed (#2) at start of BB06 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB06 is $c1 {MemOpaque:L00} ***** BB06, STMT00022(before) N006 ( 7, 9) [000070] -----+----- * JTRUE void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 N001 [000065] LCL_VAR V05 tmp4 u:1 => N002 [000066] CNS_INT 0x3F0000 => $47 {IntCns 0x3F0000} N003 [000067] AND => N004 [000068] CNS_INT 0 => $40 {IntCns 0} N005 [000069] NE => N006 [000070] JTRUE => $VN.Void ***** BB06, STMT00022(after) N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 $47 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 $40 Visiting BB08 Reachable through pred BB06 The SSA definition for ByrefExposed (#2) at start of BB08 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB08 is $c1 {MemOpaque:L00} ***** BB08, STMT00023(before) N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 N001 [000071] LCL_VAR V05 tmp4 u:1 => N002 [000072] CNS_INT -0x10000 => $48 {IntCns 0xFFFF0000} N003 [000073] ADD => Tree [000074] assigned VN to local var V09/1: N004 [000074] STORE_LCL_VAR V09 tmp8 d:1 => $VN.Void ***** BB08, STMT00023(after) N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 $48 Visiting BB07 Reachable through pred BB06 The SSA definition for ByrefExposed (#2) at start of BB07 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB07 is $c1 {MemOpaque:L00} ***** BB07, STMT00026(before) N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 N001 [000085] LCL_VAR V05 tmp4 u:1 => N002 [000086] CNS_INT -0x10000 => $48 {IntCns 0xFFFF0000} N003 [000087] AND => Tree [000088] assigned VN to local var V09/2: N004 [000088] STORE_LCL_VAR V09 tmp8 d:2 => $VN.Void ***** BB07, STMT00026(after) N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 $48 Visiting BB09 Reachable through pred BB07 ***** BB09, STMT00055(before) N004 ( 0, 0) [000256] DA--------- * STORE_LCL_VAR int V09 tmp8 d:3 N003 ( 0, 0) [000255] ----------- \--* PHI int N001 ( 0, 0) [000258] ----------- pred BB07 +--* PHI_ARG int V09 tmp8 u:2 N002 ( 0, 0) [000257] ----------- pred BB08 \--* PHI_ARG int V09 tmp8 u:1 SSA PHI definition: set VN of local 9/3 to $340 {PhiDef(V09 d:3, u:2, u:1)} . ***** BB09, STMT00055(after) N004 ( 0, 0) [000256] DA--------- * STORE_LCL_VAR int V09 tmp8 d:3 $VN.Void N003 ( 0, 0) [000255] ----------- \--* PHI int $340 N001 ( 0, 0) [000258] ----------- pred BB07 +--* PHI_ARG int V09 tmp8 u:2 N002 ( 0, 0) [000257] ----------- pred BB08 \--* PHI_ARG int V09 tmp8 u:1 --------- The SSA definition for ByrefExposed (#2) at start of BB09 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB09 is $c1 {MemOpaque:L00} ***** BB09, STMT00025(before) N007 (255, 12) [000084] -A-XG+----- * JTRUE void N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 u:1 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 u:3 (last use) N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 u:1 (last use) N001 [000078] LCL_VAR V04 tmp3 u:1 => $2c1 {ADD($1c1, $2c0)} N002 [000076] LCL_VAR V09 tmp8 u:3 (last use) => $340 {PhiDef(V09 d:3, u:2, u:1)} N003 [000080] LCL_VAR V05 tmp4 u:1 => fgCurMemoryVN[GcHeap] assigned for Interlocked intrinsic at [000081] to VN: $c2. N004 [000081] CMPXCHG => $11a {norm=$242 {MemOpaque:L00}, exc=$283 {NullPtrExc($2c1)}} N005 [000082] LCL_VAR V05 tmp4 u:1 (last use) => N006 [000083] NE => N007 [000084] JTRUE => $284 {norm=$VN.Void, exc=$283 {NullPtrExc($2c1)}} ***** BB09, STMT00025(after) N007 (255, 12) [000084] -A-XG+----- * JTRUE void $284 N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int $11a N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 u:1 (last use) Visiting BB10 Reachable through pred BB04 The SSA definition for ByrefExposed (#2) at start of BB10 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB10 is $c1 {MemOpaque:L00} ***** BB10, STMT00031(before) N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF N001 [000035] LCL_VAR V05 tmp4 u:1 => N002 [000114] CNS_INT 0x3FFFFFF => $49 {IntCns 0x3FFFFFF} N003 [000115] AND => Tree [000116] assigned VN to local var V06/1: N004 [000116] STORE_LCL_VAR V06 tmp5 d:1 => $VN.Void ***** BB10, STMT00031(after) N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF $49 --------- ***** BB10, STMT00013(before) N006 ( 7, 13) [000041] -----+----- * JTRUE void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 N001 [000117] LCL_VAR V05 tmp4 u:1 (last use) => N002 [000121] CNS_INT 0xC000000 => $4a {IntCns 0xC000000} N003 [000122] AND => N004 [000123] CNS_INT 0x8000000 => $46 {IntCns 0x8000000} N005 [000124] EQ => N006 [000041] JTRUE => $VN.Void ***** BB10, STMT00013(after) N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 $4a N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 $46 Visiting BB12 Reachable through pred BB10 The SSA definition for ByrefExposed (#2) at start of BB12 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB12 is $c1 {MemOpaque:L00} ***** BB12, STMT00035(before) N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long N002 ( 5, 10) [000134] #----+----- +--* IND long N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] N001 [000133] CNS_INT(h) 0x4208C8 static base addr cell => $142 {Hnd const: 0x00000000004208C8 GTF_ICON_STATIC_ADDR_PTR} N002 [000134] IND => $380 {InvariantLoad($142)} N003 [000135] CNS_INT 16 Fseq[s_entries] => $1c3 {LngCns 16} N004 [000136] ADD => $2c2 {ADD($1c3, $380)} VNForHandle(s_entries) is $143, fieldType is ref, size = 8 VNForMapSelect($c1, $143):ref returns $285 {$c1[$143]} N005 [000137] IND => Tree [000138] assigned VN to local var V13/2: N006 [000138] STORE_LCL_VAR V13 tmp12 d:2 => $289 {norm=$VN.Void, exc=$286 {NullPtrExc($2c2)}} ***** BB12, STMT00035(after) N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long $2c2 N002 ( 5, 10) [000134] #----+----- +--* IND long $380 N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell $142 N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] $1c3 --------- ***** BB12, STMT00036(before) N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 u:2 N001 [000140] LCL_VAR V13 tmp12 u:2 => N002 [000141] NULLCHECK => ***** BB12, STMT00036(after) N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 u:2 --------- ***** BB12, STMT00015(before) N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 u:1 (last use) N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 N001 [000139] LCL_VAR V13 tmp12 u:2 (last use) => N002 [000234] CNS_INT 16 => $1c3 {LngCns 16} N003 [000235] ADD => VNForHandle(arrElemType: System.Threading.SyncTable+Entry) is $144 N004 [000236] ARR_ADDR => $3c0 {PtrToArrElem($144, $285, $1c2, $1c2)} N005 [000126] LCL_VAR V06 tmp5 u:1 (last use) => N006 [000144] CAST => N007 [000145] CNS_INT 5 => $1c4 {LngCns 5} N008 [000146] LSH => N009 [000147] ADD => N010 [000130] IND => Tree [000045] assigned VN to local var V07/2: N011 [000045] STORE_LCL_VAR V07 tmp6 d:2 => ***** BB12, STMT00015(after) N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] $3c0 N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 $1c3 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 u:1 (last use) N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 $1c4 --------- ***** BB12, STMT00016(before) N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 N001 [000047] CNS_INT 0 => $1c2 {LngCns 0} Tree [000048] assigns to non-address-taken local V03; excluded from SSA, so value not tracked N002 [000048] STORE_LCL_VAR V03 tmp2 => $VN.Void ***** BB12, STMT00016(after) N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 $1c2 --------- ***** BB12, STMT00037(before) N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) N001 [000049] LCL_VAR V07 tmp6 u:2 => N002 [000237] CNS_INT 16 Fseq[_owningThreadId] => $1c3 {LngCns 16} N003 [000238] ADD => VNForHandle(_owningThreadId) is $145, fieldType is int, size = 4 VNForMapSelect($c1, $145):mem returns $440 {$c1[$145]} VNForMapSelect($440, $400):int returns $125 {$440[$400]} N004 [000150] IND => N005 [000050] LCL_VAR V02 tmp1 u:2 (last use) => N006 [000151] EQ => N007 [000152] JTRUE => ***** BB12, STMT00037(after) N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) Visiting BB14 Reachable through pred BB12 The SSA definition for ByrefExposed (#2) at start of BB14 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB14 is $c1 {MemOpaque:L00} ***** BB14, STMT00040(before) N007 ( 8, 8) [000161] ---XG+----- * JTRUE void N006 ( 6, 6) [000160] J--XG+-N--- \--* NE int N004 ( 4, 3) [000158] ---XG+----- +--* IND int N003 ( 3, 4) [000240] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] N005 ( 1, 2) [000159] -----+----- \--* CNS_INT int 0 N001 [000153] LCL_VAR V07 tmp6 u:2 => N002 [000239] CNS_INT 24 Fseq[_recursionCount] => $1c5 {LngCns 24} N003 [000240] ADD => VNForHandle(_recursionCount) is $146, fieldType is int, size = 4 VNForMapSelect($c1, $146):mem returns $441 {$c1[$146]} VNForMapSelect($441, $400):int returns $12c {$441[$400]} N004 [000158] IND => N005 [000159] CNS_INT 0 => $40 {IntCns 0} N006 [000160] NE => N007 [000161] JTRUE => ***** BB14, STMT00040(after) N007 ( 8, 8) [000161] ---XG+----- * JTRUE void N006 ( 6, 6) [000160] J--XG+-N--- \--* NE int N004 ( 4, 3) [000158] ---XG+----- +--* IND int N003 ( 3, 4) [000240] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N005 ( 1, 2) [000159] -----+----- \--* CNS_INT int 0 $40 Visiting BB17 Reachable through pred BB14 The SSA definition for ByrefExposed (#2) at start of BB17 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB17 is $c1 {MemOpaque:L00} ***** BB17, STMT00041(before) N010 ( 11, 10) [000169] -A-XG+--R-- * STOREIND int N009 ( 3, 4) [000242] -----+-N--- +--* ADD byref N007 ( 1, 1) [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N008 ( 1, 2) [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] N006 ( 6, 6) [000167] ---XG+----- \--* ADD int N004 ( 4, 3) [000165] ---XG+----- +--* IND int N003 ( 3, 4) [000244] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] N005 ( 1, 2) [000166] -----+----- \--* CNS_INT int -1 N001 [000163] LCL_VAR V07 tmp6 u:2 => N002 [000243] CNS_INT 24 Fseq[_recursionCount] => $1c5 {LngCns 24} N003 [000244] ADD => VNForHandle(_recursionCount) is $146, fieldType is int, size = 4 VNForMapSelect($c1, $146):mem returns $441 {$c1[$146]} VNForMapSelect($441, $400):int returns $12c {$441[$400]} N004 [000165] IND => N005 [000166] CNS_INT -1 => $41 {IntCns -1} N006 [000167] ADD => N007 [000162] LCL_VAR V07 tmp6 u:2 (last use) => N008 [000241] CNS_INT 24 Fseq[_recursionCount] => $1c5 {LngCns 24} N009 [000242] ADD => VNForHandle(_recursionCount) is $146, fieldType is int, size = 4 VNForMapSelect($c1, $146):mem returns $441 {$c1[$146]} VNForMapStore($441, $400, $134):mem in BB17 returns $480 {$441[$400 := $134]} VNForMapStore($c1, $146, $480):heap in BB17 returns $4c0 {$c1[$146 := $480]} fgCurMemoryVN[GcHeap] assigned for StoreField at [000169] to VN: $4c0. N010 [000169] STOREIND => ***** BB17, STMT00041(after) N010 ( 11, 10) [000169] -A-XG+--R-- * STOREIND int N009 ( 3, 4) [000242] -----+-N--- +--* ADD byref N007 ( 1, 1) [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N008 ( 1, 2) [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N006 ( 6, 6) [000167] ---XG+----- \--* ADD int N004 ( 4, 3) [000165] ---XG+----- +--* IND int N003 ( 3, 4) [000244] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N005 ( 1, 2) [000166] -----+----- \--* CNS_INT int -1 $41 Visiting BB15 Reachable through pred BB14 The SSA definition for ByrefExposed (#2) at start of BB15 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB15 is $c1 {MemOpaque:L00} ***** BB15, STMT00042(before) N005 ( 6, 6) [000173] -A-XG+----- * STOREIND int N003 ( 3, 4) [000246] -----+-N--- +--* ADD byref N001 ( 1, 1) [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] N004 ( 1, 2) [000171] -----+----- \--* CNS_INT int 0 N001 [000170] LCL_VAR V07 tmp6 u:2 => N002 [000245] CNS_INT 16 Fseq[_owningThreadId] => $1c3 {LngCns 16} N003 [000246] ADD => N004 [000171] CNS_INT 0 => $40 {IntCns 0} VNForHandle(_owningThreadId) is $145, fieldType is int, size = 4 VNForMapSelect($c1, $145):mem returns $440 {$c1[$145]} VNForMapStore($440, $400, $40):mem in BB15 returns $481 {$440[$400 := $40]} VNForMapStore($c1, $145, $481):heap in BB15 returns $4c1 {$c1[$145 := $481]} fgCurMemoryVN[GcHeap] assigned for StoreField at [000173] to VN: $4c1. N005 [000173] STOREIND => ***** BB15, STMT00042(after) N005 ( 6, 6) [000173] -A-XG+----- * STOREIND int N003 ( 3, 4) [000246] -----+-N--- +--* ADD byref N001 ( 1, 1) [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N004 ( 1, 2) [000171] -----+----- \--* CNS_INT int 0 $40 --------- ***** BB15, STMT00054(before) N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 N001 [000249] LCL_VAR V07 tmp6 u:2 => N002 [000250] CNS_INT 20 Fseq[_state] => $1c6 {LngCns 20} N003 [000251] ADD => N004 [000203] CNS_INT -1 => $41 {IntCns -1} fgCurMemoryVN[GcHeap] assigned for Interlocked intrinsic at [000204] to VN: $c3. N005 [000204] XADD => N006 [000205] CNS_INT -1 => $41 {IntCns -1} N007 [000206] ADD => Tree [000212] assigned VN to local var V17/1: $13a {ADD($41, $246)} N008 [000212] STORE_LCL_VAR V17 tmp16 d:1 => ***** BB15, STMT00054(after) N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] $1c6 N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 $41 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 $41 --------- ***** BB15, STMT00053(before) N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 N001 [000209] LCL_VAR V17 tmp16 u:1 => $13a {ADD($41, $246)} Tree [000211] assigned VN to local var V19/1: $13a {ADD($41, $246)} N002 [000211] STORE_LCL_VAR V19 tmp18 d:1 => $VN.Void ***** BB15, STMT00053(after) N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 $13a --------- ***** BB15, STMT00046(before) N004 ( 5, 6) [000183] -----+----- * JTRUE void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V17 tmp16 u:1 (last use) N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 N001 [000216] LCL_VAR V17 tmp16 u:1 (last use) => $13a {ADD($41, $246)} N002 [000217] CNS_INT 128 => $4d {IntCns 128} N003 [000218] LT => $13d {LT_UN($13a, $4d)} N004 [000183] JTRUE => $VN.Void ***** BB15, STMT00046(after) N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int $13d N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V17 tmp16 u:1 (last use) $13a N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 $4d Visiting BB16 Reachable through pred BB15 The SSA definition for ByrefExposed (#5) at start of BB16 is $c3 {MemOpaque:NotInLoop} The SSA definition for GcHeap (#5) at start of BB16 is $c3 {MemOpaque:NotInLoop} ***** BB16, STMT00047(before) N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 u:1 (last use) N001 [000184] LCL_VAR V07 tmp6 u:2 (last use) => N002 [000185] LCL_VAR V19 tmp18 u:1 (last use) => $13a {ADD($41, $246)} fgCurMemoryVN[GcHeap] assigned for CALL at [000186] to VN: $c4. N003 [000186] CALL => $VN.Void ***** BB16, STMT00047(after) N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 u:1 (last use) $13a Visiting BB13 Reachable through pred BB12 The SSA definition for ByrefExposed (#2) at start of BB13 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB13 is $c1 {MemOpaque:L00} ***** BB13, STMT00039(before) N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() fgCurMemoryVN[GcHeap] assigned for CALL at [000155] to VN: $c5. N001 [000155] CALL => $VN.Void ***** BB13, STMT00039(after) N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void Visiting BB11 Reachable through pred BB10 The SSA definition for ByrefExposed (#2) at start of BB11 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB11 is $c1 {MemOpaque:L00} ***** BB11, STMT00018(before) N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class N001 [000052] CNS_INT(h) 0x420818 class => $147 {Hnd const: 0x0000000000420818 GTF_ICON_CLASS_HDL} N002 [000053] CALL help => $298 {JitNew($147, $8c)} Tree [000054] assigned VN to local var V08/2: $298 {JitNew($147, $8c)} N003 [000054] STORE_LCL_VAR V08 tmp7 d:2 => $VN.Void ***** BB11, STMT00018(after) N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST $298 N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class $147 --------- ***** BB11, STMT00019(before) N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 u:2 N001 [000055] LCL_VAR V08 tmp7 u:2 => $298 {JitNew($147, $8c)} fgCurMemoryVN[GcHeap] assigned for CALL at [000056] to VN: $c6. N002 [000056] CALL => $VN.Void ***** BB11, STMT00019(after) N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 u:2 $298 --------- ***** BB11, STMT00020(before) N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 u:2 (last use) N001 [000057] LCL_VAR V08 tmp7 u:2 (last use) => $298 {JitNew($147, $8c)} N002 [000058] CALL help => $29a {norm=$VN.Void, exc=$299 {HelperOpaqueExc($381)}} ***** BB11, STMT00020(after) N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 u:2 (last use) $298 Visiting BB18 Reachable through pred BB09 The SSA definition for ByrefExposed (#3) at start of BB18 is $c2 {MemOpaque:L00} The SSA definition for GcHeap (#3) at start of BB18 is $c2 {MemOpaque:L00} Visiting BB19 Reachable through pred BB15 The SSA definition for ByrefExposed (#2) at start of BB19 is $c1 {MemOpaque:L00} The SSA definition for GcHeap (#2) at start of BB19 is $c1 {MemOpaque:L00} ***** BB19, STMT00028(before) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 N001 [000092] CNS_INT 0 => $VN.Null Tree [000093] assigns to non-address-taken local V03; excluded from SSA, so value not tracked N002 [000093] STORE_LCL_VAR V03 tmp2 => $VN.Void ***** BB19, STMT00028(after) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 $VN.Null --------- ***** BB19, STMT00001(before) N001 ( 0, 0) [000002] -----+----- * RETURN void N001 [000002] RETURN => $VN.Void ***** BB19, STMT00001(after) N001 ( 0, 0) [000002] -----+----- * RETURN void $VN.Void Visiting BB02 Reachable through pred BB01 The SSA definition for ByrefExposed (#1) at start of BB02 is $c0 {InitVal($41)} The SSA definition for GcHeap (#1) at start of BB02 is $c0 {InitVal($41)} ***** BB02, STMT00030(before) N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' N001 [000222] CNS_INT(h) '"obj"' => $500 {Hnd const: 0x0000000000420A80 GTF_ICON_OBJ_HDL} fgCurMemoryVN[GcHeap] assigned for CALL at [000099] to VN: $c7. N002 [000099] CALL => $VN.Void ***** BB02, STMT00030(after) N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' $500 *************** Finishing PHASE Do value numbering Trees after Do value numbering --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} SSA MEM: ByrefExposed, GcHeap = m:1 ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000096] J----+-N--- \--* NE int $100 N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null $VN.Null SSA MEM: ByrefExposed, GcHeap = m:1 ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} SSA MEM: ByrefExposed, GcHeap = m:1 ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' $500 SSA MEM: ByrefExposed, GcHeap = m:9 ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} SSA MEM: ByrefExposed, GcHeap = m:1 ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 17, 4) [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void N004 ( 17, 4) [000104] n-C-G+----- \--* IND int N003 ( 16, 5) [000103] --C-G+-N--- \--* ADD byref $200 N001 ( 14, 2) [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR $180 N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] $1c0 ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 u:1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 $41 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 $42 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 3, 3) [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 $281 N004 ( 3, 3) [000226] ---X-+-N--- \--* COMMA ref $282 N002 ( 2, 2) [000224] ---X-+----- +--* NULLCHECK byte $281 N001 ( 1, 1) [000223] -----+----- | \--* LCL_VAR ref V00 arg0 u:1 $80 N003 ( 1, 1) [000225] -----+----- \--* LCL_VAR ref V00 arg0 u:1 (last use) $80 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void N006 ( 4, 7) [000111] -A---+----- \--* ADD long $2c1 N004 ( 2, 4) [000230] -A---+----- +--* COMMA long $2c0 N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 $182 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 $1c1 SSA MEM: ByrefExposed, GcHeap = m:1 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} SSA MEM: ByrefExposed, GcHeap = phi(m:3, m:1) ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 $2c1 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 11) [000064] -----+----- * JTRUE void $VN.Void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 $46 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 $40 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 $47 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 $40 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 $48 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 $48 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB09 [0007] STMT00055 ( ??? ... ??? ) N004 ( 0, 0) [000256] DA--------- * STORE_LCL_VAR int V09 tmp8 d:3 $VN.Void N003 ( 0, 0) [000255] ----------- \--* PHI int $340 N001 ( 0, 0) [000258] ----------- pred BB07 +--* PHI_ARG int V09 tmp8 u:2 N002 ( 0, 0) [000257] ----------- pred BB08 \--* PHI_ARG int V09 tmp8 u:1 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 (255, 12) [000084] -A-XG+----- * JTRUE void $284 N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int $11a N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 u:1 (last use) SSA MEM: ByrefExposed, GcHeap = m:3 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF $49 ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 $4a N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 $46 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST $298 N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class $147 ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 u:2 $298 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 u:2 (last use) $298 SSA MEM: ByrefExposed, GcHeap = m:8 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long $2c2 N002 ( 5, 10) [000134] #----+----- +--* IND long $380 N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell $142 N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] $1c3 ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 u:2 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] $3c0 N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 $1c3 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 u:1 (last use) N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 $1c4 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 $1c2 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void SSA MEM: ByrefExposed, GcHeap = m:7 ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 8) [000161] ---XG+----- * JTRUE void N006 ( 6, 6) [000160] J--XG+-N--- \--* NE int N004 ( 4, 3) [000158] ---XG+----- +--* IND int N003 ( 3, 4) [000240] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N005 ( 1, 2) [000159] -----+----- \--* CNS_INT int 0 $40 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N005 ( 6, 6) [000173] -A-XG+----- * STOREIND int N003 ( 3, 4) [000246] -----+-N--- +--* ADD byref N001 ( 1, 1) [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N004 ( 1, 2) [000171] -----+----- \--* CNS_INT int 0 $40 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] $1c6 N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 $41 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 $41 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 $13a ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int $13d N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V17 tmp16 u:1 (last use) $13a N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 $4d SSA MEM: ByrefExposed, GcHeap = m:5 ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} SSA MEM: ByrefExposed, GcHeap = m:5 ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 u:1 (last use) $13a SSA MEM: ByrefExposed, GcHeap = m:6 ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N010 ( 11, 10) [000169] -A-XG+--R-- * STOREIND int N009 ( 3, 4) [000242] -----+-N--- +--* ADD byref N007 ( 1, 1) [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N008 ( 1, 2) [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N006 ( 6, 6) [000167] ---XG+----- \--* ADD int N004 ( 4, 3) [000165] ---XG+----- +--* IND int N003 ( 3, 4) [000244] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N005 ( 1, 2) [000166] -----+----- \--* CNS_INT int -1 $41 SSA MEM: ByrefExposed, GcHeap = m:4 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} SSA MEM: ByrefExposed, GcHeap = m:3 SSA MEM: ByrefExposed, GcHeap = m:3 ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 $VN.Null ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) N001 ( 0, 0) [000002] -----+----- * RETURN void $VN.Void SSA MEM: ByrefExposed, GcHeap = m:2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist SSA checks completed successfully [deferred prior check failed -- skipping this check] *************** Starting PHASE Hoist loop code *************** In optHoistLoopCode() *************** Exception Handling table is empty optHoistThisLoop processing L00 header: BB04 Members (6): [BB04..BB09] Entry: BB03 -> BB04 Exit: BB04 -> BB10; BB05 -> BB10; BB09 -> BB18 Back: BB09 -> BB04 Loop body does not contain a call USEDEF (4)={V02 V04 V05 V09} INOUT (4)={V02 V04 V05 V09} LOOPVARS(4)={V02 V04 V05 V09} Considering hoisting in entry block BB04 because L00 has more than one exit -- BB04 (header block) optHoistLoopBlocks BB04 (weight= 8 ) of loop L00 (head: BB04) ----- PreOrderVisit for [000027] STORE_LCL_VAR ----- PreOrderVisit for [000026] IND ----- PreOrderVisit for [000025] LCL_VAR ----- PostOrderVisit for [000025] LCL_VAR CONST CSE is enabled Standard CSE Heuristic [000025] LCL_VAR: not hoistable: not handled by hoisting or CSE ----- PostOrderVisit for [000026] IND ----- PostOrderVisit for [000027] STORE_LCL_VAR [000027] not invariant: variant child ----- PreOrderVisit for [000034] JTRUE ----- PreOrderVisit for [000033] NE ----- PreOrderVisit for [000031] CAST ----- PreOrderVisit for [000028] LCL_VAR ----- PostOrderVisit for [000028] LCL_VAR [000028] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000031] CAST ----- PreOrderVisit for [000032] LCL_VAR ----- PostOrderVisit for [000032] LCL_VAR [000032] LCL_VAR: not hoistable: not handled by hoisting or CSE ----- PostOrderVisit for [000033] NE ----- PostOrderVisit for [000034] JTRUE [000034] not invariant: variant child Resetting m_pHoistedInCurLoop *************** Finishing PHASE Hoist loop code [no changes] *************** Starting PHASE VN based copy prop Copy Assertion for BB01 curSsaName stack: { } Copy Assertion for BB03 curSsaName stack: { [000000]:V00/1 } Live vars after [000007]: {V00} +{V02} => {V00 V02} Live vars after [000009]: {V00 V02} -{V02} => {V00} Live vars after [000015]: {V00} +{V02} => {V00 V02} Live vars after [000225]: {V00 V02} -{V00} => {V02} Live vars after [000227]: {V02} +{V20} => {V02 V20} Live vars after [000228]: {V02 V20} -{V20} => {V02} Live vars after [000024]: {V02} +{V04} => {V02 V04} Copy Assertion for BB04 curSsaName stack: { [000000]:V00/1 [000227]:V20/1 [000015]:V02/2 [000024]:V04/1 } Live vars after [000027]: {V02 V04} +{V05} => {V02 V04 V05} Copy Assertion for BB05 curSsaName stack: { [000000]:V00/1 [000227]:V20/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 } Copy Assertion for BB06 curSsaName stack: { [000000]:V00/1 [000227]:V20/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 } Copy Assertion for BB08 curSsaName stack: { [000000]:V00/1 [000227]:V20/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 } Live vars after [000074]: {V02 V04 V05} +{V09} => {V02 V04 V05 V09} Copy Assertion for BB07 curSsaName stack: { [000000]:V00/1 [000227]:V20/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 } Live vars after [000088]: {V02 V04 V05} +{V09} => {V02 V04 V05 V09} Copy Assertion for BB09 curSsaName stack: { [000000]:V00/1 [000227]:V20/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 } Live vars after [000076]: {V02 V04 V05 V09} -{V09} => {V02 V04 V05} Live vars after [000082]: {V02 V04 V05} -{V05} => {V02 V04} Copy Assertion for BB18 curSsaName stack: { [000256]:V09/3 [000000]:V00/1 [000227]:V20/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 } Copy Assertion for BB10 curSsaName stack: { [000000]:V00/1 [000227]:V20/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 } Live vars after [000116]: {V02 V05} +{V06} => {V02 V05 V06} Live vars after [000117]: {V02 V05 V06} -{V05} => {V02 V06} Copy Assertion for BB12 curSsaName stack: { [000000]:V00/1 [000227]:V20/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 [000116]:V06/1 } Live vars after [000138]: {V02 V06} +{V13} => {V02 V06 V13} Live vars after [000139]: {V02 V06 V13} -{V13} => {V02 V06} Live vars after [000126]: {V02 V06} -{V06} => {V02} Live vars after [000045]: {V02} +{V07} => {V02 V07} Live vars after [000050]: {V02 V07} -{V02} => {V07} Copy Assertion for BB14 curSsaName stack: { [000000]:V00/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 [000116]:V06/1 [000045]:V07/2 [000138]:V13/2 [000227]:V20/1 } Copy Assertion for BB17 curSsaName stack: { [000000]:V00/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 [000116]:V06/1 [000045]:V07/2 [000138]:V13/2 [000227]:V20/1 } Live vars after [000162]: {V07} -{V07} => {} Copy Assertion for BB15 curSsaName stack: { [000000]:V00/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 [000116]:V06/1 [000045]:V07/2 [000138]:V13/2 [000227]:V20/1 } Live vars after [000212]: {V07} +{V17} => {V07 V17} Live vars after [000211]: {V07 V17} +{V19} => {V07 V17 V19} Live vars after [000216]: {V07 V17 V19} -{V17} => {V07 V19} VN based copy assertion for [000216] V17 $13a by [000211] V19 $13a. N001 ( 1, 1) [000216] -----+----- * LCL_VAR int V17 tmp16 u:1 (last use) $13a copy propagated to: N001 ( 1, 1) [000216] -----+----- * LCL_VAR int V19 tmp18 u:1 (last use) $13a Copy Assertion for BB16 curSsaName stack: { [000000]:V00/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 [000116]:V06/1 [000045]:V07/2 [000138]:V13/2 [000212]:V17/1 [000211]:V19/1 [000227]:V20/1 } Live vars after [000184]: {V07 V19} -{V07} => {V19} Live vars after [000185]: {V19} -{V19} => {} Copy Assertion for BB13 curSsaName stack: { [000000]:V00/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 [000116]:V06/1 [000045]:V07/2 [000138]:V13/2 [000227]:V20/1 } Copy Assertion for BB11 curSsaName stack: { [000000]:V00/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 [000116]:V06/1 [000227]:V20/1 } Live vars after [000054]: {} +{V08} => {V08} Live vars after [000057]: {V08} -{V08} => {} Copy Assertion for BB19 curSsaName stack: { [000000]:V00/1 [000015]:V02/2 [000024]:V04/1 [000027]:V05/1 [000227]:V20/1 } Copy Assertion for BB02 curSsaName stack: { [000000]:V00/1 } *************** Finishing PHASE VN based copy prop Trees after VN based copy prop --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} SSA MEM: ByrefExposed, GcHeap = m:1 ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000096] J----+-N--- \--* NE int $100 N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null $VN.Null SSA MEM: ByrefExposed, GcHeap = m:1 ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} SSA MEM: ByrefExposed, GcHeap = m:1 ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' $500 SSA MEM: ByrefExposed, GcHeap = m:9 ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} SSA MEM: ByrefExposed, GcHeap = m:1 ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 17, 4) [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void N004 ( 17, 4) [000104] n-C-G+----- \--* IND int N003 ( 16, 5) [000103] --C-G+-N--- \--* ADD byref $200 N001 ( 14, 2) [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR $180 N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] $1c0 ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 u:1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 $41 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 $42 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 3, 3) [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 $281 N004 ( 3, 3) [000226] ---X-+-N--- \--* COMMA ref $282 N002 ( 2, 2) [000224] ---X-+----- +--* NULLCHECK byte $281 N001 ( 1, 1) [000223] -----+----- | \--* LCL_VAR ref V00 arg0 u:1 $80 N003 ( 1, 1) [000225] -----+----- \--* LCL_VAR ref V00 arg0 u:1 (last use) $80 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void N006 ( 4, 7) [000111] -A---+----- \--* ADD long $2c1 N004 ( 2, 4) [000230] -A---+----- +--* COMMA long $2c0 N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 $182 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 $1c1 SSA MEM: ByrefExposed, GcHeap = m:1 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} SSA MEM: ByrefExposed, GcHeap = phi(m:3, m:1) ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 $2c1 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 11) [000064] -----+----- * JTRUE void $VN.Void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 $46 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 $40 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 $47 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 $40 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 $48 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 $48 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB09 [0007] STMT00055 ( ??? ... ??? ) N004 ( 0, 0) [000256] DA--------- * STORE_LCL_VAR int V09 tmp8 d:3 $VN.Void N003 ( 0, 0) [000255] ----------- \--* PHI int $340 N001 ( 0, 0) [000258] ----------- pred BB07 +--* PHI_ARG int V09 tmp8 u:2 N002 ( 0, 0) [000257] ----------- pred BB08 \--* PHI_ARG int V09 tmp8 u:1 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 (255, 12) [000084] -A-XG+----- * JTRUE void $284 N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int $11a N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 u:1 (last use) SSA MEM: ByrefExposed, GcHeap = m:3 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF $49 ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 $4a N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 $46 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST $298 N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class $147 ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 u:2 $298 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 u:2 (last use) $298 SSA MEM: ByrefExposed, GcHeap = m:8 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long $2c2 N002 ( 5, 10) [000134] #----+----- +--* IND long $380 N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell $142 N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] $1c3 ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 u:2 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] $3c0 N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 $1c3 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 u:1 (last use) N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 $1c4 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 $1c2 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void SSA MEM: ByrefExposed, GcHeap = m:7 ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 8) [000161] ---XG+----- * JTRUE void N006 ( 6, 6) [000160] J--XG+-N--- \--* NE int N004 ( 4, 3) [000158] ---XG+----- +--* IND int N003 ( 3, 4) [000240] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N005 ( 1, 2) [000159] -----+----- \--* CNS_INT int 0 $40 SSA MEM: ByrefExposed, GcHeap = m:2 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N005 ( 6, 6) [000173] -A-XG+----- * STOREIND int N003 ( 3, 4) [000246] -----+-N--- +--* ADD byref N001 ( 1, 1) [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N004 ( 1, 2) [000171] -----+----- \--* CNS_INT int 0 $40 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] $1c6 N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 $41 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 $41 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 $13a ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int $13d N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 $4d SSA MEM: ByrefExposed, GcHeap = m:5 ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} SSA MEM: ByrefExposed, GcHeap = m:5 ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 u:1 (last use) $13a SSA MEM: ByrefExposed, GcHeap = m:6 ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N010 ( 11, 10) [000169] -A-XG+--R-- * STOREIND int N009 ( 3, 4) [000242] -----+-N--- +--* ADD byref N007 ( 1, 1) [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N008 ( 1, 2) [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N006 ( 6, 6) [000167] ---XG+----- \--* ADD int N004 ( 4, 3) [000165] ---XG+----- +--* IND int N003 ( 3, 4) [000244] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N005 ( 1, 2) [000166] -----+----- \--* CNS_INT int -1 $41 SSA MEM: ByrefExposed, GcHeap = m:4 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} SSA MEM: ByrefExposed, GcHeap = m:3 SSA MEM: ByrefExposed, GcHeap = m:3 ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} SSA MEM: ByrefExposed, GcHeap = m:2 ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 $VN.Null ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) N001 ( 0, 0) [000002] -----+----- * RETURN void $VN.Void SSA MEM: ByrefExposed, GcHeap = m:2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [info] NumUses overestimated for V17.1: IR 1 SSA 2 SSA checks completed successfully [deferred prior check failed -- skipping this check] *************** Starting PHASE Redundant branch opts --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- --- Trying RBO in BB09 --- Relop [000083] BB09 value unknown, trying inference BB09 has side effects; no threading --- Trying RBO in BB06 --- Relop [000069] BB06 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB05 --- Relop [000063] BB05 value unknown, trying inference No usable PhiDef VNs optRedundantRelop in BB15; jump tree is N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int $13d N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 $4d ... checking previous tree N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 $13a -- prev tree VN is not related ... checking previous tree N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] $1c6 N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 $41 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 $41 -- prev tree has side effects and is not next to jumpTree --- Trying RBO in BB15 --- Relop [000218] BB15 value unknown, trying inference BB15 has side effects; no threading --- Trying RBO in BB14 --- Relop [000160] BB14 value unknown, trying inference BB14 has side effects; no threading optRedundantRelop in BB12; jump tree is N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) ... checking previous tree N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 $1c2 -- prev tree defs untracked V03 --- Trying RBO in BB12 --- Relop [000151] BB12 value unknown, trying inference BB12 has side effects; no threading optRedundantRelop in BB10; jump tree is N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 $4a N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 $46 ... checking previous tree N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF $49 -- prev tree VN is not related --- Trying RBO in BB10 --- Relop [000124] BB10 value unknown, trying inference BB10 has side effects; no threading optRedundantRelop in BB04; jump tree is N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 ... checking previous tree N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 $2c1 -- prev tree VN is not related --- Trying RBO in BB04 --- Relop [000033] BB04 value unknown, trying inference BB04 has side effects; no threading --- Trying RBO in BB01 --- *************** Finishing PHASE Redundant branch opts [no changes] *************** Starting PHASE Optimize Valnum CSEs Standard CSE Heuristic Candidate CSE #01, key=$12c in BB17, [cost= 4, size= 3]: N004 ( 4, 3) CSE #01 (use)[000165] ---XG+----- * IND int N003 ( 3, 4) [000244] -----+-N--- \--* ADD byref N001 ( 1, 1) [000163] -----+----- +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000243] -----+----- \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 Blocks that generate CSE def/uses BB14 cseGen = 0000000000000003 CSE #01.c BB17 cseGen = 0000000000000003 CSE #01.c Performing DataFlow for ValnumCSE's After performing DataFlow for ValnumCSE's BB01 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB02 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB03 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB04 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB05 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB06 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB07 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB08 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB09 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB10 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB11 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB12 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB13 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB14 in: 0000000000000000 gen: 0000000000000003 CSE #01.c out: 0000000000000003 CSE #01.c BB15 in: 0000000000000003 CSE #01.c gen: 0000000000000000 out: 0000000000000003 CSE #01.c BB16 in: 0000000000000003 CSE #01.c gen: 0000000000000000 out: 0000000000000001 CSE #01 BB17 in: 0000000000000003 CSE #01.c gen: 0000000000000003 CSE #01.c out: 0000000000000003 CSE #01.c BB18 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 BB19 in: 0000000000000000 gen: 0000000000000000 out: 0000000000000000 Labeling the CSEs with Use/Def information BB14 [000158] Def of CSE #01 [weight=0.50] BB17 [000165] Use of CSE #01 [weight=0.50] ************ Trees at start of optValnumCSE_Heuristic() ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000096] J----+-N--- \--* NE int $100 N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null $VN.Null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' $500 ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 17, 4) [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void N004 ( 17, 4) [000104] n-C-G+----- \--* IND int N003 ( 16, 5) [000103] --C-G+-N--- \--* ADD byref $200 N001 ( 14, 2) [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR $180 N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] $1c0 ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 u:1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 $41 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 $42 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 3, 3) [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 $281 N004 ( 3, 3) [000226] ---X-+-N--- \--* COMMA ref $282 N002 ( 2, 2) [000224] ---X-+----- +--* NULLCHECK byte $281 N001 ( 1, 1) [000223] -----+----- | \--* LCL_VAR ref V00 arg0 u:1 $80 N003 ( 1, 1) [000225] -----+----- \--* LCL_VAR ref V00 arg0 u:1 (last use) $80 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void N006 ( 4, 7) [000111] -A---+----- \--* ADD long $2c1 N004 ( 2, 4) [000230] -A---+----- +--* COMMA long $2c0 N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 $182 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 $1c1 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 $2c1 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 11) [000064] -----+----- * JTRUE void $VN.Void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 $46 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 $40 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 $47 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 $40 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00055 ( ??? ... ??? ) N004 ( 0, 0) [000256] DA--------- * STORE_LCL_VAR int V09 tmp8 d:3 $VN.Void N003 ( 0, 0) [000255] ----------- \--* PHI int $340 N001 ( 0, 0) [000258] ----------- pred BB07 +--* PHI_ARG int V09 tmp8 u:2 N002 ( 0, 0) [000257] ----------- pred BB08 \--* PHI_ARG int V09 tmp8 u:1 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 (255, 12) [000084] -A-XG+----- * JTRUE void $284 N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int $11a N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 u:1 (last use) ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF $49 ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 $4a N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 $46 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST $298 N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class $147 ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 u:2 $298 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 u:2 (last use) $298 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long $2c2 N002 ( 5, 10) [000134] #----+----- +--* IND long $380 N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell $142 N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] $1c3 ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 u:2 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] $3c0 N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 $1c3 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 u:1 (last use) N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 $1c4 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 $1c2 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 8) [000161] ---XG+----- * JTRUE void N006 ( 6, 6) [000160] J--XG+-N--- \--* NE int N004 ( 4, 3) CSE #01 (def)[000158] ---XG+----- +--* IND int N003 ( 3, 4) [000240] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000153] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N005 ( 1, 2) [000159] -----+----- \--* CNS_INT int 0 $40 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N005 ( 6, 6) [000173] -A-XG+----- * STOREIND int N003 ( 3, 4) [000246] -----+-N--- +--* ADD byref N001 ( 1, 1) [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N004 ( 1, 2) [000171] -----+----- \--* CNS_INT int 0 $40 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] $1c6 N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 $41 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 $41 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 $13a ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int $13d N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 $4d ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 u:1 (last use) $13a ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N010 ( 11, 10) [000169] -A-XG+--R-- * STOREIND int N009 ( 3, 4) [000242] -----+-N--- +--* ADD byref N007 ( 1, 1) [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N008 ( 1, 2) [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N006 ( 6, 6) [000167] ---XG+----- \--* ADD int N004 ( 4, 3) CSE #01 (use)[000165] ---XG+----- +--* IND int N003 ( 3, 4) [000244] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000163] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000243] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N005 ( 1, 2) [000166] -----+----- \--* CNS_INT int -1 $41 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 $VN.Null ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) N001 ( 0, 0) [000002] -----+----- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- Standard CSE Heuristic Aggressive CSE Promotion cutoff is 200.000000 Moderate CSE Promotion cutoff is 100.000000 enregCount is 14 Framesize estimate is 0x0000 We have a small frame Sorted CSE candidates: CSE #01, {$12c, $294} useCnt=1: [def=50.000000, use=50.000000, cost= 4 ] :: N004 ( 4, 3) CSE #01 (def)[000158] ---XG+----- * IND int Considering CSE #01 {$12c, $294} [def=50.000000, use=50.000000, cost= 4 ] CSE Expression : N004 ( 4, 3) CSE #01 (def)[000158] ---XG+----- * IND int N003 ( 3, 4) [000240] -----+-N--- \--* ADD byref N001 ( 1, 1) [000153] -----+----- +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] -----+----- \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 Moderate CSE Promotion (CSE never live at call) (150.000000 >= 100.000000) cseRefCnt=150.000000, aggressiveRefCnt=200.000000, moderateRefCnt=100.000000 defCnt=50.000000, useCnt=50.000000, cost=4, size=3 def_cost=2, use_cost=1, extra_no_cost=4, extra_yes_cost=0 CSE cost savings check (204.000000 >= 150.000000) passes Promoting CSE: lvaGrabTemp returning 21 (V21 rat0) (a long lifetime temp) called for CSE #01: moderate. New refCnts for V21: refCnt = 2, refCntWtd = 1 New refCnts for V21: refCnt = 3, refCntWtd = 1.50 CSE #01 def at [000158] replaced in BB14 with def of V21 Finalizing defs for SSA insertion of V21 1 defs: [000259] Single-def local; putting into SSA directly [000259] d:1 Inserting each use created for defs into SSA Inserting use [000260] into SSA Reaching def is [000259] d:1 Working on the replacement of the CSE #01 use at [000165] in BB17 Inserting use [000262] into SSA Reaching def is [000259] d:1 Marked V21 as live into BB17 *************** Finishing PHASE Optimize Valnum CSEs Trees after Optimize Valnum CSEs --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000096] J----+-N--- \--* NE int $100 N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null $VN.Null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' $500 ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 17, 4) [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void N004 ( 17, 4) [000104] n-C-G+----- \--* IND int N003 ( 16, 5) [000103] --C-G+-N--- \--* ADD byref $200 N001 ( 14, 2) [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR $180 N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] $1c0 ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 u:1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 $41 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 $42 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 3, 3) [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 $281 N004 ( 3, 3) [000226] ---X-+-N--- \--* COMMA ref $282 N002 ( 2, 2) [000224] ---X-+----- +--* NULLCHECK byte $281 N001 ( 1, 1) [000223] -----+----- | \--* LCL_VAR ref V00 arg0 u:1 $80 N003 ( 1, 1) [000225] -----+----- \--* LCL_VAR ref V00 arg0 u:1 (last use) $80 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void N006 ( 4, 7) [000111] -A---+----- \--* ADD long $2c1 N004 ( 2, 4) [000230] -A---+----- +--* COMMA long $2c0 N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 $182 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 $1c1 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 $2c1 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 11) [000064] -----+----- * JTRUE void $VN.Void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 $46 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 $40 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 $47 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 $40 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00055 ( ??? ... ??? ) N004 ( 0, 0) [000256] DA--------- * STORE_LCL_VAR int V09 tmp8 d:3 $VN.Void N003 ( 0, 0) [000255] ----------- \--* PHI int $340 N001 ( 0, 0) [000258] ----------- pred BB07 +--* PHI_ARG int V09 tmp8 u:2 N002 ( 0, 0) [000257] ----------- pred BB08 \--* PHI_ARG int V09 tmp8 u:1 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 (255, 12) [000084] -A-XG+----- * JTRUE void $284 N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int $11a N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 u:1 (last use) ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF $49 ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 $4a N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 $46 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST $298 N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class $147 ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 u:2 $298 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 u:2 (last use) $298 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long $2c2 N002 ( 5, 10) [000134] #----+----- +--* IND long $380 N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell $142 N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] $1c3 ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 u:2 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] $3c0 N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 $1c3 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 u:1 (last use) N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 $1c4 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 $1c2 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N010 ( 15, 13) [000161] -A-XG+----- * JTRUE void N009 ( 13, 11) [000160] JA-XG+-N--- \--* NE int N007 ( 11, 8) [000261] -A-XG------ +--* COMMA int N005 ( 8, 6) [000259] DA-XG------ | +--* STORE_LCL_VAR int V21 cse0 d:1 N004 ( 4, 3) [000158] ---XG+----- | | \--* IND int N003 ( 3, 4) [000240] -----+-N--- | | \--* ADD byref N001 ( 1, 1) [000153] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] -----+----- | | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N006 ( 3, 2) [000260] ----------- | \--* LCL_VAR int V21 cse0 u:1 N008 ( 1, 2) [000159] -----+----- \--* CNS_INT int 0 $40 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N005 ( 6, 6) [000173] -A-XG+----- * STOREIND int N003 ( 3, 4) [000246] -----+-N--- +--* ADD byref N001 ( 1, 1) [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N004 ( 1, 2) [000171] -----+----- \--* CNS_INT int 0 $40 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] $1c6 N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 $41 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 $41 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 $13a ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int $13d N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 $4d ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 u:1 (last use) $13a ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 10, 9) [000169] -A-XG+--R-- * STOREIND int N006 ( 3, 4) [000242] -----+-N--- +--* ADD byref N004 ( 1, 1) [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N005 ( 1, 2) [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N003 ( 5, 5) [000167] ----G+----- \--* ADD int N001 ( 3, 2) [000262] ----------- +--* LCL_VAR int V21 cse0 u:1 N002 ( 1, 2) [000166] -----+----- \--* CNS_INT int -1 $41 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 $VN.Null ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) N001 ( 0, 0) [000002] -----+----- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Assertion prop GenTreeNode creates assertion: N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void In BB01 New Global Constant Assertion: ($80,$0) V00.01 != null, index = #01 GenTreeNode creates assertion: N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void In BB01 New Global Constant Assertion: ($80,$0) V00.01 == null, index = #02 GenTreeNode creates assertion: N002 ( 2, 3) [000031] -----+----- * CAST int <- ushort <- int In BB04 New Global Subrange Assertion: ($241,$0) V05.01 in [0..65535], index = #03 GenTreeNode creates assertion: N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte In BB12 New Global Constant Assertion: ($83,$0) V13.02 != null, index = #04 GenTreeNode creates assertion: N004 ( 4, 3) [000150] ---XG+----- * IND int In BB12 New Global Constant Assertion: ($87,$0) V07.02 != null, index = #05 GenTreeNode creates assertion: N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void In BB15 New Global Constant Assertion: ($13d,$40) Const_Loop_Bnd_Un {LT_UN($13a, $4d)} is not {IntCns 0}, index = #06 GenTreeNode creates assertion: N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void In BB15 New Global Constant Assertion: ($13d,$40) Const_Loop_Bnd_Un {LT_UN($13a, $4d)} is {IntCns 0}, index = #07 BB01 valueGen = #02 => BB03 valueGen = #01 BB02 valueGen = #NA BB03 valueGen = #01 BB04 valueGen = #NA => BB10 valueGen = #NA BB05 valueGen = #NA => BB10 valueGen = #NA BB06 valueGen = #NA => BB08 valueGen = #NA BB07 valueGen = #NA BB08 valueGen = #NA BB09 valueGen = #NA => BB04 valueGen = #NA BB10 valueGen = #NA => BB12 valueGen = #NA BB11 valueGen = #NA BB12 valueGen = #04 #05 => BB14 valueGen = #04 #05 BB13 valueGen = #NA BB14 valueGen = #05 => BB17 valueGen = #05 BB15 valueGen = #05 #07 => BB19 valueGen = #05 #06 BB16 valueGen = #NA BB17 valueGen = #05 BB18 valueGen = #NA BB19 valueGen = #NA BB01: in = #NA out = #02 BB03 = #01 BB02: in = #02 out = #02 BB03: in = #01 out = #01 BB04: in = #01 out = #01 BB10 = #01 BB05: in = #01 out = #01 BB10 = #01 BB06: in = #01 out = #01 BB08 = #01 BB07: in = #01 out = #01 BB08: in = #01 out = #01 BB09: in = #01 out = #01 BB04 = #01 BB10: in = #01 out = #01 BB12 = #01 BB11: in = #01 out = #01 BB12: in = #01 out = #01 #04 #05 BB14 = #01 #04 #05 BB13: in = #01 #04 #05 out = #01 #04 #05 BB14: in = #01 #04 #05 out = #01 #04 #05 BB17 = #01 #04 #05 BB15: in = #01 #04 #05 out = #01 #04 #05 #07 BB19 = #01 #04 #05 #06 BB16: in = #01 #04 #05 #07 out = #01 #04 #05 #07 BB17: in = #01 #04 #05 out = #01 #04 #05 BB18: in = #01 out = #01 BB19: in = #01 out = #01 Propagating #NA for BB01, stmt STMT00029, tree [000000], tree -> #NA Propagating #NA for BB01, stmt STMT00029, tree [000095], tree -> #NA Propagating #NA for BB01, stmt STMT00029, tree [000096], tree -> #NA Propagating #NA for BB01, stmt STMT00029, tree [000097], tree -> #01 Propagating #02 for BB02, stmt STMT00030, tree [000222], tree -> #NA Propagating #02 for BB02, stmt STMT00030, tree [000099], tree -> #NA Propagating #01 for BB03, stmt STMT00004, tree [000101], tree -> #NA Propagating #01 for BB03, stmt STMT00004, tree [000102], tree -> #NA Propagating #01 for BB03, stmt STMT00004, tree [000103], tree -> #NA Propagating #01 for BB03, stmt STMT00004, tree [000104], tree -> #NA Propagating #01 for BB03, stmt STMT00004, tree [000007], tree -> #NA Propagating #01 for BB03, stmt STMT00005, tree [000008], tree -> #NA Propagating #01 for BB03, stmt STMT00005, tree [000009], tree -> #NA Propagating #01 for BB03, stmt STMT00005, tree [000010], tree -> #NA Propagating #01 for BB03, stmt STMT00005, tree [000011], tree -> #NA Propagating #01 for BB03, stmt STMT00005, tree [000012], tree -> #NA Propagating #01 for BB03, stmt STMT00005, tree [000013], tree -> #NA Propagating #01 for BB03, stmt STMT00005, tree [000014], tree -> #NA Propagating #01 for BB03, stmt STMT00005, tree [000015], tree -> #NA Propagating #01 for BB03, stmt STMT00007, tree [000223], tree -> #NA Propagating #01 for BB03, stmt STMT00007, tree [000224], tree -> #01 VN based non-null prop in BB03: N002 ( 2, 2) [000224] ---X-+----- * NULLCHECK byte $281 Propagating #01 for BB03, stmt STMT00007, tree [000225], tree -> #NA Propagating #01 for BB03, stmt STMT00007, tree [000226], tree -> #NA Propagating #01 for BB03, stmt STMT00007, tree [000019], tree -> #NA Re-morphing this stmt: STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 3, 3) [000019] DA-X-+----- * STORE_LCL_VAR byref V03 tmp2 $281 N004 ( 3, 3) [000226] ---X-+-N--- \--* COMMA ref $282 N002 ( 2, 2) [000224] -----+----- +--* NULLCHECK byte $281 N001 ( 1, 1) [000223] -----+----- | \--* LCL_VAR ref V00 arg0 u:1 $80 N003 ( 1, 1) [000225] -----+----- \--* LCL_VAR ref V00 arg0 u:1 (last use) $80 NULLCHECK on [000223] will always succeed optAssertionPropMain morphed tree: N002 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 $281 N001 ( 1, 1) [000225] -------N--- \--* LCL_VAR ref V00 arg0 u:1 (last use) $80 Propagating #01 for BB03, stmt STMT00009, tree [000020], tree -> #NA Propagating #01 for BB03, stmt STMT00009, tree [000227], tree -> #NA Propagating #01 for BB03, stmt STMT00009, tree [000228], tree -> #NA Propagating #01 for BB03, stmt STMT00009, tree [000230], tree -> #NA Propagating #01 for BB03, stmt STMT00009, tree [000110], tree -> #NA Propagating #01 for BB03, stmt STMT00009, tree [000111], tree -> #NA Propagating #01 for BB03, stmt STMT00009, tree [000024], tree -> #NA Propagating #01 for BB04, stmt STMT00010, tree [000025], tree -> #NA Propagating #01 for BB04, stmt STMT00010, tree [000026], tree -> #NA Propagating #01 for BB04, stmt STMT00010, tree [000027], tree -> #NA Propagating #01 for BB04, stmt STMT00011, tree [000028], tree -> #NA Propagating #01 for BB04, stmt STMT00011, tree [000031], tree -> #NA Propagating #01 for BB04, stmt STMT00011, tree [000032], tree -> #NA Propagating #01 for BB04, stmt STMT00011, tree [000033], tree -> #NA Propagating #01 for BB04, stmt STMT00011, tree [000034], tree -> #NA Propagating #01 for BB05, stmt STMT00021, tree [000059], tree -> #NA Propagating #01 for BB05, stmt STMT00021, tree [000060], tree -> #NA Propagating #01 for BB05, stmt STMT00021, tree [000061], tree -> #NA Propagating #01 for BB05, stmt STMT00021, tree [000062], tree -> #NA Propagating #01 for BB05, stmt STMT00021, tree [000063], tree -> #NA Propagating #01 for BB05, stmt STMT00021, tree [000064], tree -> #NA Propagating #01 for BB06, stmt STMT00022, tree [000065], tree -> #NA Propagating #01 for BB06, stmt STMT00022, tree [000066], tree -> #NA Propagating #01 for BB06, stmt STMT00022, tree [000067], tree -> #NA Propagating #01 for BB06, stmt STMT00022, tree [000068], tree -> #NA Propagating #01 for BB06, stmt STMT00022, tree [000069], tree -> #NA Propagating #01 for BB06, stmt STMT00022, tree [000070], tree -> #NA Propagating #01 for BB07, stmt STMT00026, tree [000085], tree -> #NA Propagating #01 for BB07, stmt STMT00026, tree [000086], tree -> #NA Propagating #01 for BB07, stmt STMT00026, tree [000087], tree -> #NA Propagating #01 for BB07, stmt STMT00026, tree [000088], tree -> #NA Propagating #01 for BB08, stmt STMT00023, tree [000071], tree -> #NA Propagating #01 for BB08, stmt STMT00023, tree [000072], tree -> #NA Propagating #01 for BB08, stmt STMT00023, tree [000073], tree -> #NA Propagating #01 for BB08, stmt STMT00023, tree [000074], tree -> #NA Propagating #01 for BB09, stmt STMT00025, tree [000078], tree -> #NA Propagating #01 for BB09, stmt STMT00025, tree [000076], tree -> #NA Propagating #01 for BB09, stmt STMT00025, tree [000080], tree -> #NA Propagating #01 for BB09, stmt STMT00025, tree [000081], tree -> #NA Propagating #01 for BB09, stmt STMT00025, tree [000082], tree -> #NA Propagating #01 for BB09, stmt STMT00025, tree [000083], tree -> #NA Propagating #01 for BB09, stmt STMT00025, tree [000084], tree -> #NA Propagating #01 for BB10, stmt STMT00031, tree [000035], tree -> #NA Propagating #01 for BB10, stmt STMT00031, tree [000114], tree -> #NA Propagating #01 for BB10, stmt STMT00031, tree [000115], tree -> #NA Propagating #01 for BB10, stmt STMT00031, tree [000116], tree -> #NA Propagating #01 for BB10, stmt STMT00013, tree [000117], tree -> #NA Propagating #01 for BB10, stmt STMT00013, tree [000121], tree -> #NA Propagating #01 for BB10, stmt STMT00013, tree [000122], tree -> #NA Propagating #01 for BB10, stmt STMT00013, tree [000123], tree -> #NA Propagating #01 for BB10, stmt STMT00013, tree [000124], tree -> #NA Propagating #01 for BB10, stmt STMT00013, tree [000041], tree -> #NA Propagating #01 for BB11, stmt STMT00018, tree [000052], tree -> #NA Propagating #01 for BB11, stmt STMT00018, tree [000053], tree -> #NA Propagating #01 for BB11, stmt STMT00018, tree [000054], tree -> #NA Propagating #01 for BB11, stmt STMT00019, tree [000055], tree -> #NA Propagating #01 for BB11, stmt STMT00019, tree [000056], tree -> #NA Propagating #01 for BB11, stmt STMT00020, tree [000057], tree -> #NA Propagating #01 for BB11, stmt STMT00020, tree [000058], tree -> #NA Propagating #01 for BB12, stmt STMT00035, tree [000133], tree -> #NA Propagating #01 for BB12, stmt STMT00035, tree [000134], tree -> #NA Propagating #01 for BB12, stmt STMT00035, tree [000135], tree -> #NA Propagating #01 for BB12, stmt STMT00035, tree [000136], tree -> #NA Propagating #01 for BB12, stmt STMT00035, tree [000137], tree -> #NA Propagating #01 for BB12, stmt STMT00035, tree [000138], tree -> #NA Propagating #01 for BB12, stmt STMT00036, tree [000140], tree -> #NA Propagating #01 for BB12, stmt STMT00036, tree [000141], tree -> #04 Propagating #01 #04 for BB12, stmt STMT00015, tree [000139], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00015, tree [000234], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00015, tree [000235], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00015, tree [000236], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00015, tree [000126], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00015, tree [000144], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00015, tree [000145], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00015, tree [000146], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00015, tree [000147], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00015, tree [000130], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00015, tree [000045], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00016, tree [000047], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00016, tree [000048], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00037, tree [000049], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00037, tree [000237], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00037, tree [000238], tree -> #NA Propagating #01 #04 for BB12, stmt STMT00037, tree [000150], tree -> #05 Propagating #01 #04 #05 for BB12, stmt STMT00037, tree [000050], tree -> #NA Propagating #01 #04 #05 for BB12, stmt STMT00037, tree [000151], tree -> #NA Propagating #01 #04 #05 for BB12, stmt STMT00037, tree [000152], tree -> #NA Propagating #01 #04 #05 for BB13, stmt STMT00039, tree [000155], tree -> #NA Propagating #01 #04 #05 for BB14, stmt STMT00040, tree [000153], tree -> #NA Propagating #01 #04 #05 for BB14, stmt STMT00040, tree [000239], tree -> #NA Propagating #01 #04 #05 for BB14, stmt STMT00040, tree [000240], tree -> #NA Propagating #01 #04 #05 for BB14, stmt STMT00040, tree [000158], tree -> #05 VN based non-null prop in BB14: N004 ( 4, 3) [000158] ---XG+----- * IND int Propagating #01 #04 #05 for BB14, stmt STMT00040, tree [000259], tree -> #NA Propagating #01 #04 #05 for BB14, stmt STMT00040, tree [000260], tree -> #NA Propagating #01 #04 #05 for BB14, stmt STMT00040, tree [000261], tree -> #NA Propagating #01 #04 #05 for BB14, stmt STMT00040, tree [000159], tree -> #NA Propagating #01 #04 #05 for BB14, stmt STMT00040, tree [000160], tree -> #NA Propagating #01 #04 #05 for BB14, stmt STMT00040, tree [000161], tree -> #NA Re-morphing this stmt: STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N010 ( 15, 13) [000161] -A-XG+----- * JTRUE void N009 ( 13, 11) [000160] JA-XG+-N--- \--* NE int N007 ( 11, 8) [000261] -A-XG------ +--* COMMA int N005 ( 8, 6) [000259] DA-XG------ | +--* STORE_LCL_VAR int V21 cse0 d:1 N004 ( 4, 3) [000158] n---G+----- | | \--* IND int N003 ( 3, 4) [000240] -----+-N--- | | \--* ADD byref N001 ( 1, 1) [000153] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] -----+----- | | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N006 ( 3, 2) [000260] ----------- | \--* LCL_VAR int V21 cse0 u:1 N008 ( 1, 2) [000159] -----+----- \--* CNS_INT int 0 $40 optAssertionPropMain morphed tree: N010 ( 15, 13) [000161] -A--GO----- * JTRUE void N009 ( 13, 11) [000160] JA--GO-N--- \--* NE int N007 ( 11, 8) [000261] -A--GO----- +--* COMMA int N005 ( 8, 6) [000259] DA--GO----- | +--* STORE_LCL_VAR int V21 cse0 d:1 N004 ( 4, 3) [000158] n---GO----- | | \--* IND int N003 ( 3, 4) [000240] -------N--- | | \--* ADD byref N001 ( 1, 1) [000153] ----------- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] ----------- | | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N006 ( 3, 2) [000260] ----------- | \--* LCL_VAR int V21 cse0 u:1 N008 ( 1, 2) [000159] ----------- \--* CNS_INT int 0 $40 Propagating #01 #04 #05 for BB15, stmt STMT00042, tree [000170], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00042, tree [000245], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00042, tree [000246], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00042, tree [000171], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00042, tree [000173], tree -> #05 VN based non-null prop in BB15: N005 ( 6, 6) [000173] -A-XG+----- * STOREIND int Re-morphing this stmt: STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N005 ( 6, 6) [000173] nA--G+----- * STOREIND int N003 ( 3, 4) [000246] -----+-N--- +--* ADD byref N001 ( 1, 1) [000170] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N004 ( 1, 2) [000171] -----+----- \--* CNS_INT int 0 $40 optAssertionPropMain morphed tree: N005 ( 6, 6) [000173] nA--GO----- * STOREIND int N003 ( 3, 4) [000246] -------N--- +--* ADD byref N001 ( 1, 1) [000170] ----------- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] ----------- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N004 ( 1, 2) [000171] ----------- \--* CNS_INT int 0 $40 Propagating #01 #04 #05 for BB15, stmt STMT00054, tree [000249], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00054, tree [000250], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00054, tree [000251], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00054, tree [000203], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00054, tree [000204], tree -> #05 Propagating #01 #04 #05 for BB15, stmt STMT00054, tree [000205], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00054, tree [000206], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00054, tree [000212], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00053, tree [000209], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00053, tree [000211], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00046, tree [000216], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00046, tree [000217], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00046, tree [000218], tree -> #NA Propagating #01 #04 #05 for BB15, stmt STMT00046, tree [000183], tree -> #06 Propagating #01 #04 #05 #07 for BB16, stmt STMT00047, tree [000184], tree -> #NA Propagating #01 #04 #05 #07 for BB16, stmt STMT00047, tree [000185], tree -> #NA Propagating #01 #04 #05 #07 for BB16, stmt STMT00047, tree [000186], tree -> #NA Propagating #01 #04 #05 for BB17, stmt STMT00041, tree [000262], tree -> #NA Propagating #01 #04 #05 for BB17, stmt STMT00041, tree [000166], tree -> #NA Propagating #01 #04 #05 for BB17, stmt STMT00041, tree [000167], tree -> #NA Propagating #01 #04 #05 for BB17, stmt STMT00041, tree [000162], tree -> #NA Propagating #01 #04 #05 for BB17, stmt STMT00041, tree [000241], tree -> #NA Propagating #01 #04 #05 for BB17, stmt STMT00041, tree [000242], tree -> #NA Propagating #01 #04 #05 for BB17, stmt STMT00041, tree [000169], tree -> #05 VN based non-null prop in BB17: N007 ( 10, 9) [000169] -A-XG+--R-- * STOREIND int Re-morphing this stmt: STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 10, 9) [000169] nA--G+--R-- * STOREIND int N006 ( 3, 4) [000242] -----+-N--- +--* ADD byref N004 ( 1, 1) [000162] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N005 ( 1, 2) [000241] -----+----- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N003 ( 5, 5) [000167] ----G+----- \--* ADD int N001 ( 3, 2) [000262] ----------- +--* LCL_VAR int V21 cse0 u:1 N002 ( 1, 2) [000166] -----+----- \--* CNS_INT int -1 $41 optAssertionPropMain morphed tree: N007 ( 10, 9) [000169] nA--GO--R-- * STOREIND int N006 ( 3, 4) [000242] -------N--- +--* ADD byref N004 ( 1, 1) [000162] ----------- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N005 ( 1, 2) [000241] ----------- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N003 ( 5, 5) [000167] ----G------ \--* ADD int N001 ( 3, 2) [000262] ----------- +--* LCL_VAR int V21 cse0 u:1 N002 ( 1, 2) [000166] ----------- \--* CNS_INT int -1 $41 Propagating #01 for BB19, stmt STMT00028, tree [000092], tree -> #NA Propagating #01 for BB19, stmt STMT00028, tree [000093], tree -> #NA Propagating #01 for BB19, stmt STMT00001, tree [000002], tree -> #NA *************** Finishing PHASE Assertion prop Trees after Assertion prop --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB03 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000096] J----+-N--- \--* NE int $100 N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null $VN.Null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' $500 ------------ BB03 [0015] [000..001) -> BB04(1) (always), preds={BB01} succs={BB04} ***** BB03 [0015] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 17, 4) [000007] DAC-G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void N004 ( 17, 4) [000104] n-C-G+----- \--* IND int N003 ( 16, 5) [000103] --C-G+-N--- \--* ADD byref $200 N001 ( 14, 2) [000101] H-C-G+----- +--* CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR $180 N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] $1c0 ***** BB03 [0015] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 u:1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 $41 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 $42 ***** BB03 [0015] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 $281 N001 ( 1, 1) [000225] -------N--- \--* LCL_VAR ref V00 arg0 u:1 (last use) $80 ***** BB03 [0015] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void N006 ( 4, 7) [000111] -A---+----- \--* ADD long $2c1 N004 ( 2, 4) [000230] -A---+----- +--* COMMA long $2c0 N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 $182 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 $1c1 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB03} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 $2c1 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 11) [000064] -----+----- * JTRUE void $VN.Void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 $46 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 $40 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 $47 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 $40 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00055 ( ??? ... ??? ) N004 ( 0, 0) [000256] DA--------- * STORE_LCL_VAR int V09 tmp8 d:3 $VN.Void N003 ( 0, 0) [000255] ----------- \--* PHI int $340 N001 ( 0, 0) [000258] ----------- pred BB07 +--* PHI_ARG int V09 tmp8 u:2 N002 ( 0, 0) [000257] ----------- pred BB08 \--* PHI_ARG int V09 tmp8 u:1 ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 (255, 12) [000084] -A-XG+----- * JTRUE void $284 N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int $11a N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 u:1 (last use) ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF $49 ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 $4a N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 $46 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST $298 N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class $147 ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 u:2 $298 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 u:2 (last use) $298 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long $2c2 N002 ( 5, 10) [000134] #----+----- +--* IND long $380 N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell $142 N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] $1c3 ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 u:2 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] $3c0 N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 $1c3 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 u:1 (last use) N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 $1c4 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 $1c2 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N010 ( 15, 13) [000161] -A--GO----- * JTRUE void N009 ( 13, 11) [000160] JA--GO-N--- \--* NE int N007 ( 11, 8) [000261] -A--GO----- +--* COMMA int N005 ( 8, 6) [000259] DA--GO----- | +--* STORE_LCL_VAR int V21 cse0 d:1 N004 ( 4, 3) [000158] n---GO----- | | \--* IND int N003 ( 3, 4) [000240] -------N--- | | \--* ADD byref N001 ( 1, 1) [000153] ----------- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] ----------- | | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N006 ( 3, 2) [000260] ----------- | \--* LCL_VAR int V21 cse0 u:1 N008 ( 1, 2) [000159] ----------- \--* CNS_INT int 0 $40 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N005 ( 6, 6) [000173] nA--GO----- * STOREIND int N003 ( 3, 4) [000246] -------N--- +--* ADD byref N001 ( 1, 1) [000170] ----------- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] ----------- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N004 ( 1, 2) [000171] ----------- \--* CNS_INT int 0 $40 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] $1c6 N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 $41 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 $41 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 $13a ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int $13d N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 $4d ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 u:1 (last use) $13a ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 10, 9) [000169] nA--GO--R-- * STOREIND int N006 ( 3, 4) [000242] -------N--- +--* ADD byref N004 ( 1, 1) [000162] ----------- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N005 ( 1, 2) [000241] ----------- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N003 ( 5, 5) [000167] ----G------ \--* ADD int N001 ( 3, 2) [000262] ----------- +--* LCL_VAR int V21 cse0 u:1 N002 ( 1, 2) [000166] ----------- \--* CNS_INT int -1 $41 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 $VN.Null ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) N001 ( 0, 0) [000002] -----+----- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Optimize index checks *************** Finishing PHASE Optimize index checks [no changes] *************** Starting PHASE Optimize Induction Variables *************** In optInductionVariables() After computing the dominance tree: BB01 : BB03 BB02 BB03 : BB04 BB04 : BB05 BB10 BB19 BB05 : BB06 BB10 : BB12 BB11 BB12 : BB14 BB13 BB14 : BB17 BB15 BB15 : BB16 BB06 : BB08 BB07 BB09 BB09 : BB18 Identifying loops in DFS tree with following reverse post order: RPO -> BB [pre, post] 00 -> BB01[0, 18] 01 -> BB03[2, 17] 02 -> BB04[3, 16] 03 -> BB05[4, 15] 04 -> BB10[11, 14] 05 -> BB12[13, 13] 06 -> BB14[15, 12] 07 -> BB17[18, 11] 08 -> BB15[16, 10] 09 -> BB16[17, 9] 10 -> BB13[14, 8] 11 -> BB11[12, 7] 12 -> BB06[5, 6] 13 -> BB08[10, 5] 14 -> BB07[6, 4] 15 -> BB09[7, 3] 16 -> BB18[8, 2] 17 -> BB19[9, 1] 18 -> BB02[1, 0] BB09 -> BB04 is a backedge BB04 is the header of a DFS loop with 1 back edges Loop has 6 blocks BB04 -> BB10 is an exit edge BB05 -> BB10 is an exit edge BB09 -> BB18 is an exit edge BB03 -> BB04 is an entry edge Added loop L00 with header BB04 Found 1 loops *************** Natural loop graph L00 header: BB04 Members (6): [BB04..BB09] Entry: BB03 -> BB04 Exit: BB04 -> BB10; BB05 -> BB10; BB09 -> BB18 Back: BB09 -> BB04 Optimizing induction variables: Processing L00 header: BB04 Members (6): [BB04..BB09] Entry: BB03 -> BB04 Exit: BB04 -> BB10; BB05 -> BB10; BB09 -> BB18 Back: BB09 -> BB04 Considering L00 for strength reduction... Bound on backedge taken count is Considering primary IVs Checking if we should make L00 downwards counted Considering exiting block BB09 No; exit node has side effects Considering exiting block BB05 No; operand of condition [000063] is already 0 Considering exiting block BB04 Found no potentially removable locals when making this loop downwards counted Now looking for unnecessary primary IVs *************** Finishing PHASE Optimize Induction Variables [no changes] *************** Starting PHASE VN-based dead store removal Considering [000015] for removal... -- no; first explicit def of a non-STRUCT local Considering [000045] for removal... -- no; last def not in the same block Considering [000054] for removal... -- no; last def not in the same block Considering [000088] for removal... -- no; last def not in the same block Considering [000256] for removal... -- no; last def not in the same block Considering [000138] for removal... -- no; last def not in the same block *************** Finishing PHASE VN-based dead store removal [no changes] *************** Starting PHASE VN based intrinsic expansion *************** Finishing PHASE VN based intrinsic expansion [no changes] Removing PHI functions *************** Starting PHASE Stress gtSplitTree *************** Finishing PHASE Stress gtSplitTree [no changes] *************** Starting PHASE Remove empty finally 3 No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally 3 [no changes] *************** Starting PHASE Remove empty try 3 *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try 3 [no changes] *************** Starting PHASE Remove empty try-catch-fault 3 *************** In fgRemoveEmptyTryCatchOrTryFault() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try-catch-fault 3 [no changes] *************** Starting PHASE Create EH funclets *************** Finishing PHASE Create EH funclets [no changes] *************** Starting PHASE Expand casts *************** Finishing PHASE Expand casts [no changes] *************** Starting PHASE Expand runtime lookups *************** Finishing PHASE Expand runtime lookups [no changes] *************** Starting PHASE Expand static init Nothing to expand. *************** Finishing PHASE Expand static init [no changes] *************** Starting PHASE Expand TLS access Expanding thread static local access for [000101] in BB03: N001 ( 14, 2) [000101] H-C-G+----- * CALL help byref CORINFO_HELP_READYTORUN_THREADSTATIC_BASE_NOCTOR $180 tlsRootObject= 0000000000420480 tlsIndexObject= 0000000000420478 offsetOfThreadLocalStoragePointer= 88 threadStaticBaseSlow= 0000000000420488 New Basic Block BB20 [0040] created. BB04 previous predecessor was BB03, now is BB20 setting likelihood of BB20 -> BB04 from 1 to 1 setting likelihood of BB03 -> BB20 to 1 lvaGrabTemp returning 22 (V22 rat0) called for Final offset. Initializing arg info for 266.CALL: Args for call [000266] CALL after AddFinalArgsAndDetermineABIInfo: Morphing args for 266.CALL: Args for [000266].CALL after fgMorphArgs: OutgoingArgsStackSize is 0 lvaGrabTemp returning 23 (V23 rat1) called for TlsRootAddr access. New Basic Block BB21 [0041] created. Initializing arg info for 276.CALL: Argument 0 ABI info: [00..08) reg x0 Args for call [000276] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000277].LCL_VAR long (By value), 1 reg: x0] Morphing args for 276.CALL: Sorting the arguments: Deferred argument ('x0'): [000277] ----------- * LCL_VAR long V23 rat1 Moved to late list Register placement order: x0 Args for [000276].CALL after fgMorphArgs: CallArg[[000277].LCL_VAR long (By value), 1 reg: x0, isLate, processed] OutgoingArgsStackSize is 0 New Basic Block BB22 [0042] created. New Basic Block BB23 [0043] created. setting likelihood of BB21 -> BB23 to 1 setting likelihood of BB21 -> BB22 to 0 setting likelihood of BB22 -> BB20 to 1 setting likelihood of BB23 -> BB20 to 1 tlsRootNullCondBB: BB21 fallbackBb: BB22 fastPathBb: BB23 *************** Finishing PHASE Expand TLS access Trees after Expand TLS access --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB21(1) (always) i hascall nullcheck BB21 [0041] 1 BB03 1 [???..???)-> BB23(1),BB22(0) ( cond ) internal BB22 [0042] 1 BB21 0 [???..???)-> BB20(1) (always) rare internal BB23 [0043] 1 BB21 1 [???..???)-> BB20(1) (always) internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000096] J----+-N--- \--* NE int $100 N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null $VN.Null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' $500 ------------ BB03 [0015] [???..???) -> BB21(1) (always), preds={BB01} succs={BB21} ------------ BB21 [0041] [???..???) -> BB23(1),BB22(0) (cond), preds={BB03} succs={BB22,BB23} ***** BB21 [0041] STMT00056 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 N002 ( 19, 10) [000266] --CXG------ \--* CALL ind _tls_get_addr long N001 ( 2, 8) [000265] H---------- calli tgt \--* CNS_INT(h) long 0x420480 UNKNOWN ***** BB21 [0041] STMT00058 ( ??? ... ??? ) N003 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 N002 ( 6, 4) [000269] #---------- \--* IND ref N001 ( 3, 2) [000268] ----------- \--* LCL_VAR long V23 rat1 ***** BB21 [0041] STMT00057 ( ??? ... ??? ) N004 ( 10, 7) [000274] ----------- * JTRUE void N003 ( 8, 5) [000273] ----------- \--* NE int N001 ( 3, 2) [000272] ----------- +--* LCL_VAR ref V22 rat0 N002 ( 1, 2) [000271] ----------- \--* CNS_INT long 0 ------------ BB22 [0042] [???..???) -> BB20(1) (always), preds={BB21} succs={BB20} ***** BB22 [0042] STMT00059 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 N003 ( 22, 13) [000276] --CXG------ \--* CALL ind ref N002 ( 2, 8) [000275] H---------- calli tgt \--* CNS_INT(h) long 0x420488 tls N001 ( 3, 2) [000277] ----------- arg0 in x0 \--* LCL_VAR long V23 rat1 ------------ BB23 [0043] [???..???) -> BB20(1) (always), preds={BB21} succs={BB20} ***** BB23 [0043] STMT00060 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 N001 ( 3, 2) [000279] ----------- \--* LCL_VAR ref V22 rat0 ------------ BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} ***** BB20 [0040] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void N004 ( 6, 4) [000104] n---G+----- \--* IND int N003 ( 5, 5) [000103] ----G+-N--- \--* ADD byref $200 N001 ( 3, 2) [000263] ----------- +--* LCL_VAR ref V22 rat0 N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] $1c0 ***** BB20 [0040] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 u:1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 $41 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 $42 ***** BB20 [0040] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 $281 N001 ( 1, 1) [000225] -------N--- \--* LCL_VAR ref V00 arg0 u:1 (last use) $80 ***** BB20 [0040] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void N006 ( 4, 7) [000111] -A---+----- \--* ADD long $2c1 N004 ( 2, 4) [000230] -A---+----- +--* COMMA long $2c0 N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 $182 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 $1c1 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 $2c1 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 11) [000064] -----+----- * JTRUE void $VN.Void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 $46 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 $40 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 $47 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 $40 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 (255, 12) [000084] -A-XG+----- * JTRUE void $284 N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int $11a N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 u:1 (last use) ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF $49 ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 $4a N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 $46 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST $298 N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class $147 ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 u:2 $298 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 u:2 (last use) $298 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long $2c2 N002 ( 5, 10) [000134] #----+----- +--* IND long $380 N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell $142 N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] $1c3 ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 u:2 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] $3c0 N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 $1c3 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 u:1 (last use) N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 $1c4 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 $1c2 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N010 ( 15, 13) [000161] -A--GO----- * JTRUE void N009 ( 13, 11) [000160] JA--GO-N--- \--* NE int N007 ( 11, 8) [000261] -A--GO----- +--* COMMA int N005 ( 8, 6) [000259] DA--GO----- | +--* STORE_LCL_VAR int V21 cse0 d:1 N004 ( 4, 3) [000158] n---GO----- | | \--* IND int N003 ( 3, 4) [000240] -------N--- | | \--* ADD byref N001 ( 1, 1) [000153] ----------- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] ----------- | | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N006 ( 3, 2) [000260] ----------- | \--* LCL_VAR int V21 cse0 u:1 N008 ( 1, 2) [000159] ----------- \--* CNS_INT int 0 $40 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N005 ( 6, 6) [000173] nA--GO----- * STOREIND int N003 ( 3, 4) [000246] -------N--- +--* ADD byref N001 ( 1, 1) [000170] ----------- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] ----------- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N004 ( 1, 2) [000171] ----------- \--* CNS_INT int 0 $40 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] $1c6 N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 $41 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 $41 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 $13a ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int $13d N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 $4d ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 u:1 (last use) $13a ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 10, 9) [000169] nA--GO--R-- * STOREIND int N006 ( 3, 4) [000242] -------N--- +--* ADD byref N004 ( 1, 1) [000162] ----------- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N005 ( 1, 2) [000241] ----------- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N003 ( 5, 5) [000167] ----G------ \--* ADD int N001 ( 3, 2) [000262] ----------- +--* LCL_VAR int V21 cse0 u:1 N002 ( 1, 2) [000166] ----------- \--* CNS_INT int -1 $41 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 $VN.Null ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) N001 ( 0, 0) [000002] -----+----- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Expand stack array allocation *************** Finishing PHASE Expand stack array allocation [no changes] *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Create throw helper blocks *************** Finishing PHASE Create throw helper blocks [no changes] *************** Starting PHASE Optimize bools *************** In optOptimizeBools() optimized 0 BBJ_COND cases, 0 BBJ_RETURN cases in 1 passes *************** Finishing PHASE Optimize bools Trees after Optimize bools --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB21(1) (always) i hascall nullcheck BB21 [0041] 1 BB03 1 [???..???)-> BB23(1),BB22(0) ( cond ) internal BB22 [0042] 1 BB21 0 [???..???)-> BB20(1) (always) rare internal BB23 [0043] 1 BB21 1 [???..???)-> BB20(1) (always) internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000096] J----+-N--- \--* NE int $100 N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null $VN.Null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' $500 ------------ BB03 [0015] [???..???) -> BB21(1) (always), preds={BB01} succs={BB21} ------------ BB21 [0041] [???..???) -> BB23(1),BB22(0) (cond), preds={BB03} succs={BB22,BB23} ***** BB21 [0041] STMT00056 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 N002 ( 19, 10) [000266] --CXG------ \--* CALL ind _tls_get_addr long N001 ( 2, 8) [000265] H---------- calli tgt \--* CNS_INT(h) long 0x420480 UNKNOWN ***** BB21 [0041] STMT00058 ( ??? ... ??? ) N003 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 N002 ( 6, 4) [000269] #---------- \--* IND ref N001 ( 3, 2) [000268] ----------- \--* LCL_VAR long V23 rat1 ***** BB21 [0041] STMT00057 ( ??? ... ??? ) N004 ( 10, 7) [000274] ----------- * JTRUE void N003 ( 8, 5) [000273] ----------- \--* NE int N001 ( 3, 2) [000272] ----------- +--* LCL_VAR ref V22 rat0 N002 ( 1, 2) [000271] ----------- \--* CNS_INT long 0 ------------ BB22 [0042] [???..???) -> BB20(1) (always), preds={BB21} succs={BB20} ***** BB22 [0042] STMT00059 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 N003 ( 22, 13) [000276] --CXG------ \--* CALL ind ref N002 ( 2, 8) [000275] H---------- calli tgt \--* CNS_INT(h) long 0x420488 tls N001 ( 3, 2) [000277] ----------- arg0 in x0 \--* LCL_VAR long V23 rat1 ------------ BB23 [0043] [???..???) -> BB20(1) (always), preds={BB21} succs={BB20} ***** BB23 [0043] STMT00060 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 N001 ( 3, 2) [000279] ----------- \--* LCL_VAR ref V22 rat0 ------------ BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} ***** BB20 [0040] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void N004 ( 6, 4) [000104] n---G+----- \--* IND int N003 ( 5, 5) [000103] ----G+-N--- \--* ADD byref $200 N001 ( 3, 2) [000263] ----------- +--* LCL_VAR ref V22 rat0 N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] $1c0 ***** BB20 [0040] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 u:1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 $41 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 $42 ***** BB20 [0040] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 $281 N001 ( 1, 1) [000225] -------N--- \--* LCL_VAR ref V00 arg0 u:1 (last use) $80 ***** BB20 [0040] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void N006 ( 4, 7) [000111] -A---+----- \--* ADD long $2c1 N004 ( 2, 4) [000230] -A---+----- +--* COMMA long $2c0 N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 $182 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 $1c1 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 $2c1 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 11) [000064] -----+----- * JTRUE void $VN.Void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 $46 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 $40 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 $47 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 $40 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 (255, 12) [000084] -A-XG+----- * JTRUE void $284 N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int $11a N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 u:1 (last use) ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF $49 ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 $4a N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 $46 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST $298 N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class $147 ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 u:2 $298 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 u:2 (last use) $298 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long $2c2 N002 ( 5, 10) [000134] #----+----- +--* IND long $380 N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell $142 N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] $1c3 ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 u:2 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] $3c0 N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 $1c3 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 u:1 (last use) N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 $1c4 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 $1c2 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N010 ( 15, 13) [000161] -A--GO----- * JTRUE void N009 ( 13, 11) [000160] JA--GO-N--- \--* NE int N007 ( 11, 8) [000261] -A--GO----- +--* COMMA int N005 ( 8, 6) [000259] DA--GO----- | +--* STORE_LCL_VAR int V21 cse0 d:1 N004 ( 4, 3) [000158] n---GO----- | | \--* IND int N003 ( 3, 4) [000240] -------N--- | | \--* ADD byref N001 ( 1, 1) [000153] ----------- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] ----------- | | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N006 ( 3, 2) [000260] ----------- | \--* LCL_VAR int V21 cse0 u:1 N008 ( 1, 2) [000159] ----------- \--* CNS_INT int 0 $40 ------------ BB15 [0029] [000..001) -> BB19(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB19} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N005 ( 6, 6) [000173] nA--GO----- * STOREIND int N003 ( 3, 4) [000246] -------N--- +--* ADD byref N001 ( 1, 1) [000170] ----------- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] ----------- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N004 ( 1, 2) [000171] ----------- \--* CNS_INT int 0 $40 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] $1c6 N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 $41 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 $41 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 $13a ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int $13d N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 $4d ------------ BB16 [0030] [000..001) -> BB19(1) (always), preds={BB15} succs={BB19} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 u:1 (last use) $13a ------------ BB17 [0031] [000..001) -> BB19(1) (always), preds={BB14} succs={BB19} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 10, 9) [000169] nA--GO--R-- * STOREIND int N006 ( 3, 4) [000242] -------N--- +--* ADD byref N004 ( 1, 1) [000162] ----------- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N005 ( 1, 2) [000241] ----------- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N003 ( 5, 5) [000167] ----G------ \--* ADD int N001 ( 3, 2) [000262] ----------- +--* LCL_VAR int V21 cse0 u:1 N002 ( 1, 2) [000166] ----------- \--* CNS_INT int -1 $41 ------------ BB18 [0039] [000..???) -> BB19(1) (always), preds={BB09} succs={BB19} ------------ BB19 [0032] [000..007) (return), preds={BB15,BB16,BB17,BB18} succs={} ***** BB19 [0032] STMT00028 ( 0x000[E-] ... ??? ) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 $VN.Null ***** BB19 [0032] STMT00001 ( 0x006[E-] ... ??? ) N001 ( 0, 0) [000002] -----+----- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE If conversion Conditionally executing BB07 and BB08 inside BB06 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 $47 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 $40 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 $48 Skipping if-conversion inside loop (via weight) *************** Finishing PHASE If conversion [no changes] *************** Starting PHASE Optimize layout *************** In fgUpdateFlowGraph() Before updating the flow graph: --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB21(1) (always) i hascall nullcheck BB21 [0041] 1 BB03 1 [???..???)-> BB23(1),BB22(0) ( cond ) internal BB22 [0042] 1 BB21 0 [???..???)-> BB20(1) (always) rare internal BB23 [0043] 1 BB21 1 [???..???)-> BB20(1) (always) internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB19(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB19(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB19(1) (always) i BB18 [0039] 1 BB09 0.25 [000..???)-> BB19(1) (always) internal BB19 [0032] 4 BB15,BB16,BB17,BB18 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- Compacting BB21 into BB03: *************** In fgDebugCheckBBlist Compacting BB19 into BB18: Second block has 3 other incoming edges *************** In fgDebugCheckBBlist After updating the flow graph: --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i hascall nullcheck BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) rare internal BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgUpdateFlowGraph() Before updating the flow graph: --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i hascall nullcheck BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) rare internal BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize layout Trees after Optimize layout --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i hascall nullcheck BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) rare internal BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i BB11 [0010] 1 BB10 0 [000..001) (throw ) i rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ***** BB01 [0000] STMT00029 ( INL02 @ 0x000[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000096] J----+-N--- \--* NE int $100 N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -----+----- \--* CNS_INT ref null $VN.Null ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} ***** BB02 [0014] STMT00030 ( INL02 @ 0x003[E-] ... ??? ) <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void N001 ( 2, 8) [000222] H----+----- arg0 in x0 \--* CNS_INT(h) ref '"obj"' $500 ------------ BB03 [0015] [???..???) -> BB23(1),BB22(0) (cond), preds={BB01} succs={BB22,BB23} ***** BB03 [0015] STMT00056 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 N002 ( 19, 10) [000266] --CXG------ \--* CALL ind _tls_get_addr long N001 ( 2, 8) [000265] H---------- calli tgt \--* CNS_INT(h) long 0x420480 UNKNOWN ***** BB03 [0015] STMT00058 ( ??? ... ??? ) N003 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 N002 ( 6, 4) [000269] #---------- \--* IND ref N001 ( 3, 2) [000268] ----------- \--* LCL_VAR long V23 rat1 ***** BB03 [0015] STMT00057 ( ??? ... ??? ) N004 ( 10, 7) [000274] ----------- * JTRUE void N003 ( 8, 5) [000273] ----------- \--* NE int N001 ( 3, 2) [000272] ----------- +--* LCL_VAR ref V22 rat0 N002 ( 1, 2) [000271] ----------- \--* CNS_INT long 0 ------------ BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} ***** BB22 [0042] STMT00059 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 N003 ( 22, 13) [000276] --CXG------ \--* CALL ind ref N002 ( 2, 8) [000275] H---------- calli tgt \--* CNS_INT(h) long 0x420488 tls N001 ( 3, 2) [000277] ----------- arg0 in x0 \--* LCL_VAR long V23 rat1 ------------ BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} ***** BB23 [0043] STMT00060 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 N001 ( 3, 2) [000279] ----------- \--* LCL_VAR ref V22 rat0 ------------ BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} ***** BB20 [0040] STMT00004 ( INL01 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void N004 ( 6, 4) [000104] n---G+----- \--* IND int N003 ( 5, 5) [000103] ----G+-N--- \--* ADD byref $200 N001 ( 3, 2) [000263] ----------- +--* LCL_VAR ref V22 rat0 N002 ( 1, 2) [000102] -----+----- \--* CNS_INT long 40 Fseq[t_currentManagedThreadId] $1c0 ***** BB20 [0040] STMT00005 ( INL01 @ 0x011[E-] ... ??? ) <- INLRT @ 0x000[E-] N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void N007 ( 7, 9) [000014] -----+----- \--* OR int N001 ( 1, 1) [000008] -----+----- +--* LCL_VAR int V02 tmp1 u:1 N006 ( 5, 7) [000013] -----+----- \--* RSH int N004 ( 3, 4) [000011] -----+----- +--* ADD int N002 ( 1, 1) [000009] -----+----- | +--* LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- | \--* CNS_INT int -1 $41 N005 ( 1, 2) [000012] -----+----- \--* CNS_INT int 31 $42 ***** BB20 [0040] STMT00007 ( INL01 @ 0x01A[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 $281 N001 ( 1, 1) [000225] -------N--- \--* LCL_VAR ref V00 arg0 u:1 (last use) $80 ***** BB20 [0040] STMT00009 ( INL01 @ 0x021[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void N006 ( 4, 7) [000111] -A---+----- \--* ADD long $2c1 N004 ( 2, 4) [000230] -A---+----- +--* COMMA long $2c0 N002 ( 1, 3) [000227] DA---+----- | +--* STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N001 ( 1, 1) [000020] -----+----- | | \--* LCL_VAR byref V03 tmp2 $182 N003 ( 1, 1) [000228] -----+----- | \--* LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -----+----- \--* CNS_INT long -4 $1c1 ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} ***** BB04 [0002] STMT00010 ( INL01 @ 0x029[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 N002 ( 3, 2) [000026] ---XG+----- \--* IND int N001 ( 1, 1) [000025] -----+----- \--* LCL_VAR long V04 tmp3 u:1 $2c1 ***** BB04 [0002] STMT00011 ( INL01 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x000[E-] N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void N004 ( 4, 5) [000033] N----+-N-U- \--* NE int N002 ( 2, 3) [000031] -----+----- +--* CAST int <- ushort <- int N001 ( 1, 1) [000028] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N003 ( 1, 1) [000032] -----+----- \--* LCL_VAR int V02 tmp1 u:2 ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ***** BB05 [0003] STMT00021 ( INL01 @ 0x038[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 11) [000064] -----+----- * JTRUE void $VN.Void N005 ( 5, 9) [000063] J----+-N--- \--* NE int N003 ( 3, 6) [000061] -----+----- +--* AND int N001 ( 1, 1) [000059] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- | \--* CNS_INT int 0x8000000 $46 N004 ( 1, 2) [000062] -----+----- \--* CNS_INT int 0 $40 ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ***** BB06 [0004] STMT00022 ( INL01 @ 0x042[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void N005 ( 5, 7) [000069] J----+-N--- \--* NE int N003 ( 3, 4) [000067] -----+----- +--* AND int N001 ( 1, 1) [000065] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- | \--* CNS_INT int 0x3F0000 $47 N004 ( 1, 2) [000068] -----+----- \--* CNS_INT int 0 $40 ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB07 [0005] STMT00026 ( INL01 @ 0x04C[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void N003 ( 3, 4) [000087] -----+----- \--* AND int N001 ( 1, 1) [000085] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ***** BB08 [0006] STMT00023 ( INL01 @ 0x056[E-] ... ??? ) <- INLRT @ 0x000[E-] N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void N003 ( 3, 4) [000073] -----+----- \--* ADD int N001 ( 1, 1) [000071] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- \--* CNS_INT int -0x10000 $48 ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ***** BB09 [0007] STMT00025 ( INL01 @ 0x060[E-] ... ??? ) <- INLRT @ 0x000[E-] N007 (255, 12) [000084] -A-XG+----- * JTRUE void $284 N006 (255, 10) [000083] NA-XG+-N-U- \--* NE int N004 (255, 8) [000081] -A-XG+----- +--* CMPXCHG int $11a N001 ( 1, 1) [000078] -----+-N--- | +--* LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- | +--* LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- | \--* LCL_VAR int V05 tmp4 u:1 N005 ( 1, 1) [000082] -----+----- \--* LCL_VAR int V05 tmp4 u:1 (last use) ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ***** BB10 [0009] STMT00031 ( INL06 @ 0x000[E-] ... ??? ) <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void N003 ( 3, 6) [000115] -----+----- \--* AND int N001 ( 1, 1) [000035] -----+----- +--* LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- \--* CNS_INT int 0x3FFFFFF $49 ***** BB10 [0009] STMT00013 ( INL01 @ 0x06F[E-] ... ??? ) <- INLRT @ 0x000[E-] N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void N005 ( 5, 11) [000124] J----+-N--- \--* EQ int N003 ( 3, 6) [000122] -----+----- +--* AND int N001 ( 1, 1) [000117] -----+----- | +--* LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- | \--* CNS_INT int 0xC000000 $4a N004 ( 1, 4) [000123] -----+----- \--* CNS_INT int 0x8000000 $46 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} ***** BB11 [0010] STMT00018 ( INL01 @ 0x07A[E-] ... ??? ) <- INLRT @ 0x000[E-] N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void N002 ( 16, 11) [000053] --C--+----- \--* CALL help ref CORINFO_HELP_NEWSFAST $298 N001 ( 2, 8) [000052] H----+----- arg0 in x0 \--* CNS_INT(h) long 0x420818 class $147 ***** BB11 [0010] STMT00019 ( INL01 @ ??? ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void N001 ( 3, 2) [000055] -----+----- this in x0 \--* LCL_VAR ref V08 tmp7 u:2 $298 ***** BB11 [0010] STMT00020 ( INL01 @ 0x07F[--] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a N001 ( 3, 2) [000057] -----+----- arg0 in x0 \--* LCL_VAR ref V08 tmp7 u:2 (last use) $298 ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ***** BB12 [0011] STMT00035 ( INL09 @ 0x000[E-] ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 N005 ( 8, 12) [000137] ---XG+----- \--* IND ref N004 ( 7, 13) [000136] -----+-N--- \--* ADD long $2c2 N002 ( 5, 10) [000134] #----+----- +--* IND long $380 N001 ( 2, 8) [000133] H----+----- | \--* CNS_INT(h) long 0x4208C8 static base addr cell $142 N003 ( 1, 2) [000135] -----+----- \--* CNS_INT long 16 Fseq[s_entries] $1c3 ***** BB12 [0011] STMT00036 ( INL09 @ ??? ... ??? ) <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte N001 ( 1, 1) [000140] -----+----- \--* LCL_VAR ref V13 tmp12 u:2 ***** BB12 [0011] STMT00015 ( INL01 @ 0x080[E-] ... ??? ) <- INLRT @ 0x000[E-] N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 N010 ( 11, 14) [000130] ---XG+----- \--* IND ref N009 ( 9, 13) [000147] ----G+-N--- \--* ADD byref N004 ( 2, 5) [000236] -----+----- +--* ARR_ADDR byref System.Threading.SyncTable+Entry[] $3c0 N003 ( 2, 5) [000235] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000139] -----+----- | +--* LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- | \--* CNS_INT long 16 $1c3 N008 ( 6, 7) [000146] -----+----- \--* LSH long N006 ( 4, 4) [000144] -----+----- +--* CAST long <- int N005 ( 3, 2) [000126] -----+----- | \--* LCL_VAR int V06 tmp5 u:1 (last use) N007 ( 1, 2) [000145] -----+----- \--* CNS_INT long 5 $1c4 ***** BB12 [0011] STMT00016 ( INL01 @ 0x088[E-] ... ??? ) <- INLRT @ 0x000[E-] N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000047] -----+----- \--* CNS_INT long 0 $1c2 ***** BB12 [0011] STMT00037 ( INL10 @ 0x000[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 8, 7) [000152] ---XG+----- * JTRUE void N006 ( 6, 5) [000151] J--XG+-N--- \--* EQ int N004 ( 4, 3) [000150] ---XG+----- +--* IND int N003 ( 3, 4) [000238] -----+-N--- | \--* ADD byref N001 ( 1, 1) [000049] -----+----- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N005 ( 1, 1) [000050] -----+----- \--* LCL_VAR int V02 tmp1 u:2 (last use) ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} ***** BB13 [0025] STMT00039 ( INL10 @ 0x009[E-] ... ??? ) <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ***** BB14 [0026] STMT00040 ( INL11 @ 0x000[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N010 ( 15, 13) [000161] -A--GO----- * JTRUE void N009 ( 13, 11) [000160] JA--GO-N--- \--* NE int N007 ( 11, 8) [000261] -A--GO----- +--* COMMA int N005 ( 8, 6) [000259] DA--GO----- | +--* STORE_LCL_VAR int V21 cse0 d:1 N004 ( 4, 3) [000158] n---GO----- | | \--* IND int N003 ( 3, 4) [000240] -------N--- | | \--* ADD byref N001 ( 1, 1) [000153] ----------- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] ----------- | | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N006 ( 3, 2) [000260] ----------- | \--* LCL_VAR int V21 cse0 u:1 N008 ( 1, 2) [000159] ----------- \--* CNS_INT int 0 $40 ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} ***** BB15 [0029] STMT00042 ( INL11 @ 0x008[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N005 ( 6, 6) [000173] nA--GO----- * STOREIND int N003 ( 3, 4) [000246] -------N--- +--* ADD byref N001 ( 1, 1) [000170] ----------- | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] ----------- | \--* CNS_INT long 16 Fseq[_owningThreadId] $1c3 N004 ( 1, 2) [000171] ----------- \--* CNS_INT int 0 $40 ***** BB15 [0029] STMT00054 ( INL12 @ ??? ... ??? ) <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 N007 ( 7, 10) [000206] -A-XG+----- \--* ADD int N005 ( 5, 7) [000204] -A-XG+----- +--* XADD int N003 ( 3, 4) [000251] -----+----- | +--* ADD byref N001 ( 1, 1) [000249] -----+----- | | +--* LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- | | \--* CNS_INT long 20 Fseq[_state] $1c6 N004 ( 1, 2) [000203] -----+----- | \--* CNS_INT int -1 $41 N006 ( 1, 2) [000205] -----+----- \--* CNS_INT int -1 $41 ***** BB15 [0029] STMT00053 ( INL15 @ 0x000[E-] ... ??? ) <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void N001 ( 1, 1) [000209] -----+----- \--* LCL_VAR int V17 tmp16 u:1 $13a ***** BB15 [0029] STMT00046 ( INL11 @ 0x016[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void N003 ( 3, 4) [000218] N----+-N-U- \--* LT int $13d N001 ( 1, 1) [000216] -----+----- +--* LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -----+----- \--* CNS_INT int 128 $4d ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} ***** BB16 [0030] STMT00047 ( INL11 @ 0x01F[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void N001 ( 1, 1) [000184] -----+----- this in x0 +--* LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- arg1 in x1 \--* LCL_VAR int V19 tmp18 u:1 (last use) $13a ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} ***** BB17 [0031] STMT00041 ( INL11 @ 0x027[E-] ... ??? ) <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N007 ( 10, 9) [000169] nA--GO--R-- * STOREIND int N006 ( 3, 4) [000242] -------N--- +--* ADD byref N004 ( 1, 1) [000162] ----------- | +--* LCL_VAR ref V07 tmp6 u:2 (last use) N005 ( 1, 2) [000241] ----------- | \--* CNS_INT long 24 Fseq[_recursionCount] $1c5 N003 ( 5, 5) [000167] ----G------ \--* ADD int N001 ( 3, 2) [000262] ----------- +--* LCL_VAR int V21 cse0 u:1 N002 ( 1, 2) [000166] ----------- \--* CNS_INT int -1 $41 ------------ BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} ***** BB18 [0039] STMT00028 ( 0x000[E-] ... ??? ) N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void N001 ( 1, 2) [000092] -----+----- \--* CNS_INT byref 0 $VN.Null ***** BB18 [0039] STMT00001 ( 0x006[E-] ... ??? ) N001 ( 0, 0) [000002] -----+----- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Recognize Switch *************** Finishing PHASE Recognize Switch [no changes] *************** Starting PHASE Rationalize IR *************** Finishing PHASE Rationalize IR Trees after Rationalize IR --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i LIR BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i LIR hascall nullcheck BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i LIR BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i LIR nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} [000281] ----------- IL_OFFSET void INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -----+----- t95 = CNS_INT ref null $VN.Null /--* t0 ref +--* t95 ref N003 ( 3, 4) [000096] J----+-N--- t96 = * NE int $100 /--* t96 int N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} [000282] ----------- IL_OFFSET void INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000222] H----+----- t222 = CNS_INT(h) ref '"obj"' $500 /--* t222 ref arg0 in x0 N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void ------------ BB03 [0015] [???..???) -> BB23(1),BB22(0) (cond), preds={BB01} succs={BB22,BB23} [000283] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN /--* t265 long calli tgt N002 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long /--* t266 long N003 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 N001 ( 3, 2) [000268] ----------- t268 = LCL_VAR long V23 rat1 /--* t268 long N002 ( 6, 4) [000269] #---------- t269 = * IND ref /--* t269 ref N003 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 N001 ( 3, 2) [000272] ----------- t272 = LCL_VAR ref V22 rat0 N002 ( 1, 2) [000271] ----------- t271 = CNS_INT long 0 /--* t272 ref +--* t271 long N003 ( 8, 5) [000273] ----------- t273 = * NE int /--* t273 int N004 ( 10, 7) [000274] ----------- * JTRUE void ------------ BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} [000284] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 N002 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls /--* t277 long arg0 in x0 +--* t275 long calli tgt N003 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref /--* t276 ref N004 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 ------------ BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} [000285] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000279] ----------- t279 = LCL_VAR ref V22 rat0 /--* t279 ref N002 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 ------------ BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} [000286] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000263] ----------- t263 = LCL_VAR ref V22 rat0 N002 ( 1, 2) [000102] -----+----- t102 = CNS_INT long 40 Fseq[t_currentManagedThreadId] $1c0 /--* t263 ref +--* t102 long N003 ( 5, 5) [000103] ----G+-N--- t103 = * ADD byref $200 /--* t103 byref N004 ( 6, 4) [000104] n---G+----- t104 = * IND int /--* t104 int N005 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void [000287] ----------- IL_OFFSET void INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000008] -----+----- t8 = LCL_VAR int V02 tmp1 u:1 N002 ( 1, 1) [000009] -----+----- t9 = LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -----+----- t10 = CNS_INT int -1 $41 /--* t9 int +--* t10 int N004 ( 3, 4) [000011] -----+----- t11 = * ADD int N005 ( 1, 2) [000012] -----+----- t12 = CNS_INT int 31 $42 /--* t11 int +--* t12 int N006 ( 5, 7) [000013] -----+----- t13 = * RSH int /--* t8 int +--* t13 int N007 ( 7, 9) [000014] -----+----- t14 = * OR int /--* t14 int N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void [000288] ----------- IL_OFFSET void INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000225] -------N--- t225 = LCL_VAR ref V00 arg0 u:1 (last use) $80 /--* t225 ref N002 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 $281 [000289] ----------- IL_OFFSET void INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000020] -----+----- t20 = LCL_VAR byref V03 tmp2 $182 /--* t20 byref N002 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N003 ( 1, 1) [000228] -----+----- t228 = LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -----+----- t110 = CNS_INT long -4 $1c1 /--* t228 long +--* t110 long N006 ( 4, 7) [000111] -A---+----- t111 = * ADD long $2c1 /--* t111 long N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} [000290] ----------- IL_OFFSET void INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000025] -----+----- t25 = LCL_VAR long V04 tmp3 u:1 $2c1 /--* t25 long N002 ( 3, 2) [000026] ---XG+----- t26 = * IND int /--* t26 int N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 [000291] ----------- IL_OFFSET void INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 /--* t28 int N002 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int N003 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 /--* t31 int +--* t32 int N004 ( 4, 5) [000033] N----+-N-U- t33 = * NE int /--* t33 int N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} [000292] ----------- IL_OFFSET void INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000059] -----+----- t59 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -----+----- t60 = CNS_INT int 0x8000000 $46 /--* t59 int +--* t60 int N003 ( 3, 6) [000061] -----+----- t61 = * AND int N004 ( 1, 2) [000062] -----+----- t62 = CNS_INT int 0 $40 /--* t61 int +--* t62 int N005 ( 5, 9) [000063] J----+-N--- t63 = * NE int /--* t63 int N006 ( 7, 11) [000064] -----+----- * JTRUE void $VN.Void ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} [000293] ----------- IL_OFFSET void INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -----+----- t66 = CNS_INT int 0x3F0000 $47 /--* t65 int +--* t66 int N003 ( 3, 4) [000067] -----+----- t67 = * AND int N004 ( 1, 2) [000068] -----+----- t68 = CNS_INT int 0 $40 /--* t67 int +--* t68 int N005 ( 5, 7) [000069] J----+-N--- t69 = * NE int /--* t69 int N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} [000294] ----------- IL_OFFSET void INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000085] -----+----- t85 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -----+----- t86 = CNS_INT int -0x10000 $48 /--* t85 int +--* t86 int N003 ( 3, 4) [000087] -----+----- t87 = * AND int /--* t87 int N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} [000295] ----------- IL_OFFSET void INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000071] -----+----- t71 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -----+----- t72 = CNS_INT int -0x10000 $48 /--* t71 int +--* t72 int N003 ( 3, 4) [000073] -----+----- t73 = * ADD int /--* t73 int N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} [000296] ----------- IL_OFFSET void INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 /--* t78 long +--* t76 int +--* t80 int N004 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int $11a N005 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 (last use) /--* t81 int +--* t82 int N006 (255, 10) [000083] NA-XG+-N-U- t83 = * NE int /--* t83 int N007 (255, 12) [000084] -A-XG+----- * JTRUE void $284 ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} [000297] ----------- IL_OFFSET void INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000035] -----+----- t35 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -----+----- t114 = CNS_INT int 0x3FFFFFF $49 /--* t35 int +--* t114 int N003 ( 3, 6) [000115] -----+----- t115 = * AND int /--* t115 int N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void [000298] ----------- IL_OFFSET void INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -----+----- t121 = CNS_INT int 0xC000000 $4a /--* t117 int +--* t121 int N003 ( 3, 6) [000122] -----+----- t122 = * AND int N004 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 $46 /--* t122 int +--* t123 int N005 ( 5, 11) [000124] J----+-N--- t124 = * EQ int /--* t124 int N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} [000299] ----------- IL_OFFSET void INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class $147 /--* t52 long arg0 in x0 N002 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST $298 /--* t53 ref N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void [000300] ----------- IL_OFFSET void INL01 @ ??? <- INLRT @ 0x000[E-] N001 ( 3, 2) [000055] -----+----- t55 = LCL_VAR ref V08 tmp7 u:2 $298 /--* t55 ref this in x0 N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void [000301] ----------- IL_OFFSET void INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000057] -----+----- t57 = LCL_VAR ref V08 tmp7 u:2 (last use) $298 /--* t57 ref arg0 in x0 N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} [000302] ----------- IL_OFFSET void INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000133] H----+----- t133 = CNS_INT(h) long 0x4208C8 static base addr cell $142 /--* t133 long N002 ( 5, 10) [000134] #----+----- t134 = * IND long $380 N003 ( 1, 2) [000135] -----+----- t135 = CNS_INT long 16 Fseq[s_entries] $1c3 /--* t134 long +--* t135 long N004 ( 7, 13) [000136] -----+-N--- t136 = * ADD long $2c2 /--* t136 long N005 ( 8, 12) [000137] ---XG+----- t137 = * IND ref /--* t137 ref N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 [000303] ----------- IL_OFFSET void INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000140] -----+----- t140 = LCL_VAR ref V13 tmp12 u:2 /--* t140 ref N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte [000304] ----------- IL_OFFSET void INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000139] -----+----- t139 = LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -----+----- t234 = CNS_INT long 16 $1c3 /--* t139 ref +--* t234 long N003 ( 2, 5) [000235] -----+-N--- t235 = * ADD byref N005 ( 3, 2) [000126] -----+----- t126 = LCL_VAR int V06 tmp5 u:1 (last use) /--* t126 int N006 ( 4, 4) [000144] -----+----- t144 = * CAST long <- int N007 ( 1, 2) [000145] -----+----- t145 = CNS_INT long 5 $1c4 /--* t144 long +--* t145 long N008 ( 6, 7) [000146] -----+----- t146 = * LSH long /--* t235 byref +--* t146 long N009 ( 9, 13) [000147] ----G+-N--- t147 = * ADD byref /--* t147 byref N010 ( 11, 14) [000130] ---XG+----- t130 = * IND ref /--* t130 ref N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 [000305] ----------- IL_OFFSET void INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] N001 ( 1, 2) [000047] -----+----- t47 = CNS_INT long 0 $1c2 /--* t47 long N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void [000306] ----------- IL_OFFSET void INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000237] -----+----- t237 = CNS_INT long 16 Fseq[_owningThreadId] $1c3 /--* t49 ref +--* t237 long N003 ( 3, 4) [000238] -----+-N--- t238 = * ADD byref /--* t238 byref N004 ( 4, 3) [000150] ---XG+----- t150 = * IND int N005 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 (last use) /--* t150 int +--* t50 int N006 ( 6, 5) [000151] J--XG+-N--- t151 = * EQ int /--* t151 int N007 ( 8, 7) [000152] ---XG+----- * JTRUE void ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} [000307] ----------- IL_OFFSET void INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} [000308] ----------- IL_OFFSET void INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000153] ----------- t153 = LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000239] ----------- t239 = CNS_INT long 24 Fseq[_recursionCount] $1c5 /--* t153 ref +--* t239 long N003 ( 3, 4) [000240] -------N--- t240 = * ADD byref /--* t240 byref N004 ( 4, 3) [000158] n---GO----- t158 = * IND int /--* t158 int N005 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 N006 ( 3, 2) [000260] ----------- t260 = LCL_VAR int V21 cse0 u:1 N008 ( 1, 2) [000159] ----------- t159 = CNS_INT int 0 $40 /--* t260 int +--* t159 int N009 ( 13, 11) [000160] JA--GO-N--- t160 = * NE int /--* t160 int N010 ( 15, 13) [000161] -A--GO----- * JTRUE void ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} [000309] ----------- IL_OFFSET void INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000170] ----------- t170 = LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000245] ----------- t245 = CNS_INT long 16 Fseq[_owningThreadId] $1c3 /--* t170 ref +--* t245 long N003 ( 3, 4) [000246] -------N--- t246 = * ADD byref N004 ( 1, 2) [000171] ----------- t171 = CNS_INT int 0 $40 /--* t246 byref +--* t171 int N005 ( 6, 6) [000173] nA--GO----- * STOREIND int [000310] ----------- IL_OFFSET void INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000249] -----+----- t249 = LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -----+----- t250 = CNS_INT long 20 Fseq[_state] $1c6 /--* t249 ref +--* t250 long N003 ( 3, 4) [000251] -----+----- t251 = * ADD byref N004 ( 1, 2) [000203] -----+----- t203 = CNS_INT int -1 $41 /--* t251 byref +--* t203 int N005 ( 5, 7) [000204] -A-XG+----- t204 = * XADD int N006 ( 1, 2) [000205] -----+----- t205 = CNS_INT int -1 $41 /--* t204 int +--* t205 int N007 ( 7, 10) [000206] -A-XG+----- t206 = * ADD int /--* t206 int N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 [000311] ----------- IL_OFFSET void INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000209] -----+----- t209 = LCL_VAR int V17 tmp16 u:1 $13a /--* t209 int N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void [000312] ----------- IL_OFFSET void INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -----+----- t217 = CNS_INT int 128 $4d /--* t216 int +--* t217 int N003 ( 3, 4) [000218] N----+-N-U- t218 = * LT int $13d /--* t218 int N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} [000313] ----------- IL_OFFSET void INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000184] -----+----- t184 = LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- t185 = LCL_VAR int V19 tmp18 u:1 (last use) $13a /--* t184 ref this in x0 +--* t185 int arg1 in x1 N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} [000314] ----------- IL_OFFSET void INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000262] ----------- t262 = LCL_VAR int V21 cse0 u:1 N002 ( 1, 2) [000166] ----------- t166 = CNS_INT int -1 $41 /--* t262 int +--* t166 int N003 ( 5, 5) [000167] ----G------ t167 = * ADD int N004 ( 1, 1) [000162] ----------- t162 = LCL_VAR ref V07 tmp6 u:2 (last use) N005 ( 1, 2) [000241] ----------- t241 = CNS_INT long 24 Fseq[_recursionCount] $1c5 /--* t162 ref +--* t241 long N006 ( 3, 4) [000242] -------N--- t242 = * ADD byref /--* t242 byref +--* t167 int N007 ( 10, 9) [000169] nA--GO----- * STOREIND int ------------ BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} [000315] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 2) [000092] -----+----- t92 = CNS_INT byref 0 $VN.Null /--* t92 byref N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void [000316] ----------- IL_OFFSET void INLRT @ 0x006[E-] N001 ( 0, 0) [000002] -----+----- RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Lowering nodeinfo Lowering JTRUE: N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -c---+----- t95 = CNS_INT ref null $VN.Null /--* t0 ref +--* t95 ref N003 ( 3, 4) [000096] J----+-N--- t96 = * NE int $100 /--* t96 int N004 ( 5, 6) [000097] -----+----- * JTRUE void $VN.Void Lowered to JCMP lowering call (before): N001 ( 2, 8) [000222] H----+----- t222 = CNS_INT(h) ref '"obj"' $500 /--* t222 ref arg0 in x0 N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void args: ====== late: ====== lowering arg : N001 ( 2, 8) [000222] H----+----- * CNS_INT(h) ref '"obj"' $500 new node is : [000317] ----------- * PUTARG_REG ref REG x0 lowering call (after): N001 ( 2, 8) [000222] H----+----- t222 = CNS_INT(h) ref '"obj"' $500 /--* t222 ref [000317] ----------- t317 = * PUTARG_REG ref REG x0 /--* t317 ref arg0 in x0 N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void lowering call (before): N001 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN /--* t265 long calli tgt N002 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long args: ====== late: ====== lowering call (after): N001 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN /--* t265 long calli tgt N002 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long lowering store lcl var/field (before): N001 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN /--* t265 long calli tgt N002 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long /--* t266 long N003 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 lowering store lcl var/field (after): N001 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN /--* t265 long calli tgt N002 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long /--* t266 long N003 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 lowering store lcl var/field (before): N001 ( 3, 2) [000268] ----------- t268 = LCL_VAR long V23 rat1 /--* t268 long N002 ( 6, 4) [000269] #---------- t269 = * IND ref /--* t269 ref N003 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 lowering store lcl var/field (after): N001 ( 3, 2) [000268] ----------- t268 = LCL_VAR long V23 rat1 /--* t268 long N002 ( 6, 4) [000269] #---------- t269 = * IND ref /--* t269 ref N003 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 Lowering JTRUE: N001 ( 3, 2) [000272] ----------- t272 = LCL_VAR ref V22 rat0 N002 ( 1, 2) [000271] -c--------- t271 = CNS_INT long 0 /--* t272 ref +--* t271 long N003 ( 8, 5) [000273] ----------- t273 = * NE int /--* t273 int N004 ( 10, 7) [000274] ----------- * JTRUE void Lowered to JCMP lowering call (before): N001 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 N002 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls /--* t277 long arg0 in x0 +--* t275 long calli tgt N003 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref args: ====== late: ====== lowering arg : N001 ( 3, 2) [000277] ----------- * LCL_VAR long V23 rat1 new node is : [000318] ----------- * PUTARG_REG long REG x0 lowering call (after): N001 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 /--* t277 long [000318] ----------- t318 = * PUTARG_REG long REG x0 N002 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls /--* t318 long arg0 in x0 +--* t275 long calli tgt N003 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref lowering store lcl var/field (before): N001 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 /--* t277 long [000318] ----------- t318 = * PUTARG_REG long REG x0 N002 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls /--* t318 long arg0 in x0 +--* t275 long calli tgt N003 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref /--* t276 ref N004 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 lowering store lcl var/field (after): N001 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 /--* t277 long [000318] ----------- t318 = * PUTARG_REG long REG x0 N002 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls /--* t318 long arg0 in x0 +--* t275 long calli tgt N003 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref /--* t276 ref N004 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 lowering store lcl var/field (before): N001 ( 3, 2) [000279] ----------- t279 = LCL_VAR ref V22 rat0 /--* t279 ref N002 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 lowering store lcl var/field (after): N001 ( 3, 2) [000279] ----------- t279 = LCL_VAR ref V22 rat0 /--* t279 ref N002 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 Notify VM instruction set (ArmBase_Arm64) must be supported. Addressing mode: Base N001 ( 3, 2) [000263] ----------- * LCL_VAR ref V22 rat0 + 40 Removing unused node: N002 ( 1, 2) [000102] -c---+----- * CNS_INT long 40 Fseq[t_currentManagedThreadId] $1c0 New addressing mode node: N003 ( 5, 5) [000103] -----+----- * LEA(b+40) byref lowering store lcl var/field (before): N001 ( 3, 2) [000263] ----------- t263 = LCL_VAR ref V22 rat0 /--* t263 ref N003 ( 5, 5) [000103] -c---+----- t103 = * LEA(b+40) byref /--* t103 byref N004 ( 6, 4) [000104] n---G+----- t104 = * IND int /--* t104 int N005 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void lowering store lcl var/field (after): N001 ( 3, 2) [000263] ----------- t263 = LCL_VAR ref V22 rat0 /--* t263 ref N003 ( 5, 5) [000103] -c---+----- t103 = * LEA(b+40) byref /--* t103 byref N004 ( 6, 4) [000104] n---G+----- t104 = * IND int /--* t104 int N005 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void ..could not turn [000008] or [000013] into a def of flags, bailing lowering store lcl var/field (before): N001 ( 1, 1) [000008] -----+----- t8 = LCL_VAR int V02 tmp1 u:1 N002 ( 1, 1) [000009] -----+----- t9 = LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -c---+----- t10 = CNS_INT int -1 $41 /--* t9 int +--* t10 int N004 ( 3, 4) [000011] -----+----- t11 = * ADD int N005 ( 1, 2) [000012] -c---+----- t12 = CNS_INT int 31 $42 /--* t11 int +--* t12 int N006 ( 5, 7) [000013] -c---+----- t13 = * RSH int /--* t8 int +--* t13 int N007 ( 7, 9) [000014] -----+----- t14 = * OR int /--* t14 int N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void lowering store lcl var/field (after): N001 ( 1, 1) [000008] -----+----- t8 = LCL_VAR int V02 tmp1 u:1 N002 ( 1, 1) [000009] -----+----- t9 = LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -c---+----- t10 = CNS_INT int -1 $41 /--* t9 int +--* t10 int N004 ( 3, 4) [000011] -----+----- t11 = * ADD int N005 ( 1, 2) [000012] -c---+----- t12 = CNS_INT int 31 $42 /--* t11 int +--* t12 int N006 ( 5, 7) [000013] -c---+----- t13 = * RSH int /--* t8 int +--* t13 int N007 ( 7, 9) [000014] -----+----- t14 = * OR int /--* t14 int N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [000225] -------N--- t225 = LCL_VAR ref V00 arg0 u:1 (last use) $80 /--* t225 ref N002 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 $281 lowering store lcl var/field (after): N001 ( 1, 1) [000225] -------N--- t225 = LCL_VAR ref V00 arg0 u:1 (last use) $80 /--* t225 ref N002 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 $281 lowering store lcl var/field (before): N001 ( 1, 1) [000020] -----+----- t20 = LCL_VAR byref V03 tmp2 $182 /--* t20 byref N002 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void lowering store lcl var/field (after): N001 ( 1, 1) [000020] -----+----- t20 = LCL_VAR byref V03 tmp2 $182 /--* t20 byref N002 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void lowering store lcl var/field (before): N003 ( 1, 1) [000228] -----+----- t228 = LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -c---+----- t110 = CNS_INT long -4 $1c1 /--* t228 long +--* t110 long N006 ( 4, 7) [000111] -A---+----- t111 = * ADD long $2c1 /--* t111 long N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void lowering store lcl var/field (after): N003 ( 1, 1) [000228] -----+----- t228 = LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -c---+----- t110 = CNS_INT long -4 $1c1 /--* t228 long +--* t110 long N006 ( 4, 7) [000111] -A---+----- t111 = * ADD long $2c1 /--* t111 long N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [000025] -----+----- t25 = LCL_VAR long V04 tmp3 u:1 $2c1 /--* t25 long N002 ( 3, 2) [000026] ---XG+----- t26 = * IND int /--* t26 int N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 lowering store lcl var/field (after): N001 ( 1, 1) [000025] -----+----- t25 = LCL_VAR long V04 tmp3 u:1 $2c1 /--* t25 long N002 ( 3, 2) [000026] ---XG+----- t26 = * IND int /--* t26 int N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 LowerCast for: N002 ( 2, 3) [000031] -----+----- * CAST int <- ushort <- int Lowering JTRUE: N001 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 /--* t28 int N002 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int N003 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 /--* t31 int +--* t32 int N004 ( 4, 5) [000033] N----+-N-U- t33 = * NE int /--* t33 int N005 ( 6, 7) [000034] -----+----- * JTRUE void $VN.Void Lowering condition: N001 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 /--* t28 int N002 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int N003 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 /--* t31 int +--* t32 int N004 ( 4, 5) [000033] N----+-N-U- t33 = * NE int Lowering JTRUE Result: N001 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 /--* t28 int N002 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int N003 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 /--* t31 int +--* t32 int N004 ( 4, 5) [000033] -----+-N-U- * CMP void N005 ( 6, 7) [000034] -----+----- JCC void cond=UNE ..could not turn [000059] or [000060] into a def of flags, bailing Lowering JTRUE: N001 ( 1, 1) [000059] -----+----- t59 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -c---+----- t60 = CNS_INT int 0x8000000 $46 /--* t59 int +--* t60 int N005 ( 5, 9) [000063] J----+-N--- t63 = * TEST_NE int /--* t63 int N006 ( 7, 11) [000064] -----+----- * JTRUE void $VN.Void Lowered to JTEST ..could not turn [000065] or [000066] into a def of flags, bailing Lowering JTRUE: N001 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -c---+----- t66 = CNS_INT int 0x3F0000 $47 /--* t65 int +--* t66 int N005 ( 5, 7) [000069] J----+-N--- t69 = * TEST_NE int /--* t69 int N006 ( 7, 9) [000070] -----+----- * JTRUE void $VN.Void Lowering condition: N001 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -c---+----- t66 = CNS_INT int 0x3F0000 $47 /--* t65 int +--* t66 int N005 ( 5, 7) [000069] J----+-N--- t69 = * TEST_NE int Lowering JTRUE Result: N001 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -c---+----- t66 = CNS_INT int 0x3F0000 $47 /--* t65 int +--* t66 int N005 ( 5, 7) [000069] -----+-N--- * TEST void N006 ( 7, 9) [000070] -----+----- JCC void cond=UNE ..could not turn [000085] or [000086] into a def of flags, bailing lowering store lcl var/field (before): N001 ( 1, 1) [000085] -----+----- t85 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -c---+----- t86 = CNS_INT int -0x10000 $48 /--* t85 int +--* t86 int N003 ( 3, 4) [000087] -----+----- t87 = * AND int /--* t87 int N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void lowering store lcl var/field (after): N001 ( 1, 1) [000085] -----+----- t85 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -c---+----- t86 = CNS_INT int -0x10000 $48 /--* t85 int +--* t86 int N003 ( 3, 4) [000087] -----+----- t87 = * AND int /--* t87 int N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [000071] -----+----- t71 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -c---+----- t72 = CNS_INT int -0x10000 $48 /--* t71 int +--* t72 int N003 ( 3, 4) [000073] -----+----- t73 = * ADD int /--* t73 int N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void lowering store lcl var/field (after): N001 ( 1, 1) [000071] -----+----- t71 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -c---+----- t72 = CNS_INT int -0x10000 $48 /--* t71 int +--* t72 int N003 ( 3, 4) [000073] -----+----- t73 = * ADD int /--* t73 int N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void Lowering JTRUE: N001 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 /--* t78 long +--* t76 int +--* t80 int N004 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int $11a N005 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 (last use) /--* t81 int +--* t82 int N006 (255, 10) [000083] NA-XG+-N-U- t83 = * NE int /--* t83 int N007 (255, 12) [000084] -A-XG+----- * JTRUE void $284 Lowering condition: N001 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 /--* t78 long +--* t76 int +--* t80 int N004 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int $11a N005 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 (last use) /--* t81 int +--* t82 int N006 (255, 10) [000083] NA-XG+-N-U- t83 = * NE int Lowering JTRUE Result: N001 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 /--* t78 long +--* t76 int +--* t80 int N004 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int $11a N005 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 (last use) /--* t81 int +--* t82 int N006 (255, 10) [000083] -A-XG+-N-U- * CMP void N007 (255, 12) [000084] -A-XG+----- JCC void cond=UNE ..could not turn [000035] or [000114] into a def of flags, bailing lowering store lcl var/field (before): N001 ( 1, 1) [000035] -----+----- t35 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -c---+----- t114 = CNS_INT int 0x3FFFFFF $49 /--* t35 int +--* t114 int N003 ( 3, 6) [000115] -----+----- t115 = * AND int /--* t115 int N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void lowering store lcl var/field (after): N001 ( 1, 1) [000035] -----+----- t35 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -c---+----- t114 = CNS_INT int 0x3FFFFFF $49 /--* t35 int +--* t114 int N003 ( 3, 6) [000115] -----+----- t115 = * AND int /--* t115 int N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void ..could not turn [000117] or [000121] into a def of flags, bailing Lowering JTRUE: N001 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -c---+----- t121 = CNS_INT int 0xC000000 $4a /--* t117 int +--* t121 int N003 ( 3, 6) [000122] -----+----- t122 = * AND int N004 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 $46 /--* t122 int +--* t123 int N005 ( 5, 11) [000124] J----+-N--- t124 = * EQ int /--* t124 int N006 ( 7, 13) [000041] -----+----- * JTRUE void $VN.Void Lowering condition: N001 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -c---+----- t121 = CNS_INT int 0xC000000 $4a /--* t117 int +--* t121 int N003 ( 3, 6) [000122] -----+----- t122 = * AND int N004 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 $46 /--* t122 int +--* t123 int N005 ( 5, 11) [000124] J----+-N--- t124 = * EQ int Lowering JTRUE Result: N001 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -c---+----- t121 = CNS_INT int 0xC000000 $4a /--* t117 int +--* t121 int N003 ( 3, 6) [000122] -----+----- t122 = * AND int N004 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 $46 /--* t122 int +--* t123 int N005 ( 5, 11) [000124] -----+-N--- * CMP void N006 ( 7, 13) [000041] -----+----- JCC void cond=UEQ lowering call (before): N001 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class $147 /--* t52 long arg0 in x0 N002 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST $298 args: ====== late: ====== lowering arg : N001 ( 2, 8) [000052] H----+----- * CNS_INT(h) long 0x420818 class $147 new node is : [000319] ----------- * PUTARG_REG long REG x0 lowering call (after): N001 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class $147 /--* t52 long [000319] ----------- t319 = * PUTARG_REG long REG x0 /--* t319 long arg0 in x0 N002 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST $298 lowering store lcl var/field (before): N001 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class $147 /--* t52 long [000319] ----------- t319 = * PUTARG_REG long REG x0 /--* t319 long arg0 in x0 N002 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST $298 /--* t53 ref N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void lowering store lcl var/field (after): N001 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class $147 /--* t52 long [000319] ----------- t319 = * PUTARG_REG long REG x0 /--* t319 long arg0 in x0 N002 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST $298 /--* t53 ref N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void lowering call (before): N001 ( 3, 2) [000055] -----+----- t55 = LCL_VAR ref V08 tmp7 u:2 $298 /--* t55 ref this in x0 N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void args: ====== late: ====== lowering arg : N001 ( 3, 2) [000055] -----+----- * LCL_VAR ref V08 tmp7 u:2 $298 new node is : [000320] ----------- * PUTARG_REG ref REG x0 lowering call (after): N001 ( 3, 2) [000055] -----+----- t55 = LCL_VAR ref V08 tmp7 u:2 $298 /--* t55 ref [000320] ----------- t320 = * PUTARG_REG ref REG x0 /--* t320 ref this in x0 N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void lowering call (before): N001 ( 3, 2) [000057] -----+----- t57 = LCL_VAR ref V08 tmp7 u:2 (last use) $298 /--* t57 ref arg0 in x0 N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a args: ====== late: ====== lowering arg : N001 ( 3, 2) [000057] -----+----- * LCL_VAR ref V08 tmp7 u:2 (last use) $298 new node is : [000321] ----------- * PUTARG_REG ref REG x0 lowering call (after): N001 ( 3, 2) [000057] -----+----- t57 = LCL_VAR ref V08 tmp7 u:2 (last use) $298 /--* t57 ref [000321] ----------- t321 = * PUTARG_REG ref REG x0 /--* t321 ref arg0 in x0 N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a Addressing mode: Base N002 ( 5, 10) [000134] #----+----- * IND long $380 + 16 Removing unused node: N003 ( 1, 2) [000135] -c---+----- * CNS_INT long 16 Fseq[s_entries] $1c3 New addressing mode node: N004 ( 7, 13) [000136] -----+----- * LEA(b+16) long lowering store lcl var/field (before): N001 ( 2, 8) [000133] H----+----- t133 = CNS_INT(h) long 0x4208C8 static base addr cell $142 /--* t133 long N002 ( 5, 10) [000134] #----+----- t134 = * IND long $380 /--* t134 long N004 ( 7, 13) [000136] -c---+----- t136 = * LEA(b+16) long /--* t136 long N005 ( 8, 12) [000137] ---XG+----- t137 = * IND ref /--* t137 ref N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 lowering store lcl var/field (after): N001 ( 2, 8) [000133] H----+----- t133 = CNS_INT(h) long 0x4208C8 static base addr cell $142 /--* t133 long N002 ( 5, 10) [000134] #----+----- t134 = * IND long $380 /--* t134 long N004 ( 7, 13) [000136] -c---+----- t136 = * LEA(b+16) long /--* t136 long N005 ( 8, 12) [000137] ---XG+----- t137 = * IND ref /--* t137 ref N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 LowerCast for: N006 ( 4, 4) [000144] -----+----- * CAST long <- int Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N003 ( 2, 5) [000235] -----+-N--- * ADD byref + Index * 1 + 0 N008 ( 6, 7) [000146] -----+----- * BFIZ long New addressing mode node: N009 ( 9, 13) [000147] -----+----- * LEA(b+(i*1)+0) byref lowering store lcl var/field (before): N001 ( 1, 1) [000139] -----+----- t139 = LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -c---+----- t234 = CNS_INT long 16 $1c3 /--* t139 ref +--* t234 long N003 ( 2, 5) [000235] -----+-N--- t235 = * ADD byref N005 ( 3, 2) [000126] -----+----- t126 = LCL_VAR int V06 tmp5 u:1 (last use) /--* t126 int N006 ( 4, 4) [000144] -c---+----- t144 = * CAST long <- int N007 ( 1, 2) [000145] -c---+----- t145 = CNS_INT long 5 $1c4 /--* t144 long +--* t145 long N008 ( 6, 7) [000146] -----+----- t146 = * BFIZ long /--* t235 byref +--* t146 long N009 ( 9, 13) [000147] -c---+----- t147 = * LEA(b+(i*1)+0) byref /--* t147 byref N010 ( 11, 14) [000130] ---XG+----- t130 = * IND ref /--* t130 ref N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000139] -----+----- t139 = LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -c---+----- t234 = CNS_INT long 16 $1c3 /--* t139 ref +--* t234 long N003 ( 2, 5) [000235] -----+-N--- t235 = * ADD byref N005 ( 3, 2) [000126] -----+----- t126 = LCL_VAR int V06 tmp5 u:1 (last use) /--* t126 int N006 ( 4, 4) [000144] -c---+----- t144 = * CAST long <- int N007 ( 1, 2) [000145] -c---+----- t145 = CNS_INT long 5 $1c4 /--* t144 long +--* t145 long N008 ( 6, 7) [000146] -----+----- t146 = * BFIZ long /--* t235 byref +--* t146 long N009 ( 9, 13) [000147] -c---+----- t147 = * LEA(b+(i*1)+0) byref /--* t147 byref N010 ( 11, 14) [000130] ---XG+----- t130 = * IND ref /--* t130 ref N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 lowering store lcl var/field (before): N001 ( 1, 2) [000047] -----+----- t47 = CNS_INT long 0 $1c2 /--* t47 long N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void lowering store lcl var/field (after): N001 ( 1, 2) [000047] -c---+----- t47 = CNS_INT long 0 $1c2 /--* t47 long N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void Addressing mode: Base N001 ( 1, 1) [000049] -----+----- * LCL_VAR ref V07 tmp6 u:2 + 16 Removing unused node: N002 ( 1, 2) [000237] -c---+----- * CNS_INT long 16 Fseq[_owningThreadId] $1c3 New addressing mode node: N003 ( 3, 4) [000238] -----+----- * LEA(b+16) byref Lowering JTRUE: N001 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 /--* t49 ref N003 ( 3, 4) [000238] -c---+----- t238 = * LEA(b+16) byref /--* t238 byref N004 ( 4, 3) [000150] ---XG+----- t150 = * IND int N005 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 (last use) /--* t150 int +--* t50 int N006 ( 6, 5) [000151] J--XG+-N--- t151 = * EQ int /--* t151 int N007 ( 8, 7) [000152] ---XG+----- * JTRUE void Lowering condition: N001 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 /--* t49 ref N003 ( 3, 4) [000238] -c---+----- t238 = * LEA(b+16) byref /--* t238 byref N004 ( 4, 3) [000150] ---XG+----- t150 = * IND int N005 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 (last use) /--* t150 int +--* t50 int N006 ( 6, 5) [000151] J--XG+-N--- t151 = * EQ int Lowering JTRUE Result: N001 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 /--* t49 ref N003 ( 3, 4) [000238] -c---+----- t238 = * LEA(b+16) byref /--* t238 byref N004 ( 4, 3) [000150] ---XG+----- t150 = * IND int N005 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 (last use) /--* t150 int +--* t50 int N006 ( 6, 5) [000151] ---XG+-N--- * CMP void N007 ( 8, 7) [000152] ---XG+----- JCC void cond=UEQ lowering call (before): N001 ( 14, 2) [000155] --CXG+----- CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void args: ====== late: ====== lowering call (after): N001 ( 14, 2) [000155] --CXG+----- CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void Addressing mode: Base N001 ( 1, 1) [000153] ----------- * LCL_VAR ref V07 tmp6 u:2 + 24 Removing unused node: N002 ( 1, 2) [000239] -c--------- * CNS_INT long 24 Fseq[_recursionCount] $1c5 New addressing mode node: N003 ( 3, 4) [000240] ----------- * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 1) [000153] ----------- t153 = LCL_VAR ref V07 tmp6 u:2 /--* t153 ref N003 ( 3, 4) [000240] -c--------- t240 = * LEA(b+24) byref /--* t240 byref N004 ( 4, 3) [000158] n---GO----- t158 = * IND int /--* t158 int N005 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000153] ----------- t153 = LCL_VAR ref V07 tmp6 u:2 /--* t153 ref N003 ( 3, 4) [000240] -c--------- t240 = * LEA(b+24) byref /--* t240 byref N004 ( 4, 3) [000158] n---GO----- t158 = * IND int /--* t158 int N005 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 Lowering JTRUE: N006 ( 3, 2) [000260] ----------- t260 = LCL_VAR int V21 cse0 u:1 N008 ( 1, 2) [000159] -c--------- t159 = CNS_INT int 0 $40 /--* t260 int +--* t159 int N009 ( 13, 11) [000160] JA--GO-N--- t160 = * NE int /--* t160 int N010 ( 15, 13) [000161] -A--GO----- * JTRUE void Lowered to JCMP Addressing mode: Base N001 ( 1, 1) [000170] ----------- * LCL_VAR ref V07 tmp6 u:2 + 16 Removing unused node: N002 ( 1, 2) [000245] -c--------- * CNS_INT long 16 Fseq[_owningThreadId] $1c3 New addressing mode node: N003 ( 3, 4) [000246] ----------- * LEA(b+16) byref Notify VM instruction set (Atomics) must be supported. lowering store lcl var/field (before): N001 ( 1, 1) [000249] -----+----- t249 = LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -c---+----- t250 = CNS_INT long 20 Fseq[_state] $1c6 /--* t249 ref +--* t250 long N003 ( 3, 4) [000251] -----+----- t251 = * ADD byref N004 ( 1, 2) [000203] -c---+----- t203 = CNS_INT int -1 $41 /--* t251 byref +--* t203 int N005 ( 5, 7) [000204] -A-XG+----- t204 = * XADD int N006 ( 1, 2) [000205] -c---+----- t205 = CNS_INT int -1 $41 /--* t204 int +--* t205 int N007 ( 7, 10) [000206] -A-XG+----- t206 = * ADD int /--* t206 int N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000249] -----+----- t249 = LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -c---+----- t250 = CNS_INT long 20 Fseq[_state] $1c6 /--* t249 ref +--* t250 long N003 ( 3, 4) [000251] -----+----- t251 = * ADD byref N004 ( 1, 2) [000203] -c---+----- t203 = CNS_INT int -1 $41 /--* t251 byref +--* t203 int N005 ( 5, 7) [000204] -A-XG+----- t204 = * XADD int N006 ( 1, 2) [000205] -c---+----- t205 = CNS_INT int -1 $41 /--* t204 int +--* t205 int N007 ( 7, 10) [000206] -A-XG+----- t206 = * ADD int /--* t206 int N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000209] -----+----- t209 = LCL_VAR int V17 tmp16 u:1 $13a /--* t209 int N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void lowering store lcl var/field (after): N001 ( 1, 1) [000209] -----+----- t209 = LCL_VAR int V17 tmp16 u:1 $13a /--* t209 int N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void Lowering JTRUE: N001 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -c---+----- t217 = CNS_INT int 128 $4d /--* t216 int +--* t217 int N003 ( 3, 4) [000218] N----+-N-U- t218 = * LT int $13d /--* t218 int N004 ( 5, 6) [000183] -----+----- * JTRUE void $VN.Void Lowering condition: N001 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -c---+----- t217 = CNS_INT int 128 $4d /--* t216 int +--* t217 int N003 ( 3, 4) [000218] N----+-N-U- t218 = * LT int $13d Lowering JTRUE Result: N001 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -c---+----- t217 = CNS_INT int 128 $4d /--* t216 int +--* t217 int N003 ( 3, 4) [000218] -----+-N-U- * CMP void N004 ( 5, 6) [000183] -----+----- JCC void cond=ULT lowering call (before): N001 ( 1, 1) [000184] -----+----- t184 = LCL_VAR ref V07 tmp6 u:2 (last use) N002 ( 3, 2) [000185] -----+----- t185 = LCL_VAR int V19 tmp18 u:1 (last use) $13a /--* t184 ref this in x0 +--* t185 int arg1 in x1 N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [000184] -----+----- * LCL_VAR ref V07 tmp6 u:2 (last use) new node is : [000322] ----------- * PUTARG_REG ref REG x0 lowering arg : N002 ( 3, 2) [000185] -----+----- * LCL_VAR int V19 tmp18 u:1 (last use) $13a new node is : [000323] ----------- * PUTARG_REG int REG x1 lowering call (after): N001 ( 1, 1) [000184] -----+----- t184 = LCL_VAR ref V07 tmp6 u:2 (last use) /--* t184 ref [000322] ----------- t322 = * PUTARG_REG ref REG x0 N002 ( 3, 2) [000185] -----+----- t185 = LCL_VAR int V19 tmp18 u:1 (last use) $13a /--* t185 int [000323] ----------- t323 = * PUTARG_REG int REG x1 /--* t322 ref this in x0 +--* t323 int arg1 in x1 N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void Addressing mode: Base N004 ( 1, 1) [000162] ----------- * LCL_VAR ref V07 tmp6 u:2 (last use) + 24 Removing unused node: N005 ( 1, 2) [000241] -c--------- * CNS_INT long 24 Fseq[_recursionCount] $1c5 New addressing mode node: N006 ( 3, 4) [000242] ----------- * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 2) [000092] -----+----- t92 = CNS_INT byref 0 $VN.Null /--* t92 byref N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void lowering store lcl var/field (after): N001 ( 1, 2) [000092] -c---+----- t92 = CNS_INT byref 0 $VN.Null /--* t92 byref N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void lowering return node N001 ( 0, 0) [000002] -----+----- * RETURN void $VN.Void ============ 0 parameter register to local mappings Lower has completed modifying nodes. --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i LIR BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i LIR hascall nullcheck BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i LIR BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i LIR nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} [000281] ----------- IL_OFFSET void INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -c---+----- t95 = CNS_INT ref null $VN.Null /--* t0 ref +--* t95 ref N004 ( 5, 6) [000097] -----+----- * JCMP void ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} [000282] ----------- IL_OFFSET void INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000222] H----+----- t222 = CNS_INT(h) ref '"obj"' $500 /--* t222 ref [000317] ----------- t317 = * PUTARG_REG ref REG x0 /--* t317 ref arg0 in x0 N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void ------------ BB03 [0015] [???..???) -> BB23(1),BB22(0) (cond), preds={BB01} succs={BB22,BB23} [000283] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN /--* t265 long calli tgt N002 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long /--* t266 long N003 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 N001 ( 3, 2) [000268] ----------- t268 = LCL_VAR long V23 rat1 /--* t268 long N002 ( 6, 4) [000269] #---------- t269 = * IND ref /--* t269 ref N003 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 N001 ( 3, 2) [000272] ----------- t272 = LCL_VAR ref V22 rat0 N002 ( 1, 2) [000271] -c--------- t271 = CNS_INT long 0 /--* t272 ref +--* t271 long N004 ( 10, 7) [000274] ----------- * JCMP void ------------ BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} [000284] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 /--* t277 long [000318] ----------- t318 = * PUTARG_REG long REG x0 N002 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls /--* t318 long arg0 in x0 +--* t275 long calli tgt N003 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref /--* t276 ref N004 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 ------------ BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} [000285] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000279] ----------- t279 = LCL_VAR ref V22 rat0 /--* t279 ref N002 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 ------------ BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} [000286] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000263] ----------- t263 = LCL_VAR ref V22 rat0 /--* t263 ref N003 ( 5, 5) [000103] -c---+----- t103 = * LEA(b+40) byref /--* t103 byref N004 ( 6, 4) [000104] n---G+----- t104 = * IND int /--* t104 int N005 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void [000287] ----------- IL_OFFSET void INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000008] -----+----- t8 = LCL_VAR int V02 tmp1 u:1 N002 ( 1, 1) [000009] -----+----- t9 = LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -c---+----- t10 = CNS_INT int -1 $41 /--* t9 int +--* t10 int N004 ( 3, 4) [000011] -----+----- t11 = * ADD int N005 ( 1, 2) [000012] -c---+----- t12 = CNS_INT int 31 $42 /--* t11 int +--* t12 int N006 ( 5, 7) [000013] -c---+----- t13 = * RSH int /--* t8 int +--* t13 int N007 ( 7, 9) [000014] -----+----- t14 = * OR int /--* t14 int N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void [000288] ----------- IL_OFFSET void INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000225] -------N--- t225 = LCL_VAR ref V00 arg0 u:1 (last use) $80 /--* t225 ref N002 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 $281 [000289] ----------- IL_OFFSET void INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000020] -----+----- t20 = LCL_VAR byref V03 tmp2 $182 /--* t20 byref N002 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N003 ( 1, 1) [000228] -----+----- t228 = LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -c---+----- t110 = CNS_INT long -4 $1c1 /--* t228 long +--* t110 long N006 ( 4, 7) [000111] -A---+----- t111 = * ADD long $2c1 /--* t111 long N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} [000290] ----------- IL_OFFSET void INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000025] -----+----- t25 = LCL_VAR long V04 tmp3 u:1 $2c1 /--* t25 long N002 ( 3, 2) [000026] ---XG+----- t26 = * IND int /--* t26 int N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 [000291] ----------- IL_OFFSET void INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 /--* t28 int N002 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int N003 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 /--* t31 int +--* t32 int N004 ( 4, 5) [000033] -----+-N-U- * CMP void N005 ( 6, 7) [000034] -----+----- JCC void cond=UNE ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} [000292] ----------- IL_OFFSET void INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000059] -----+----- t59 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -c---+----- t60 = CNS_INT int 0x8000000 $46 /--* t59 int +--* t60 int N006 ( 7, 11) [000064] -----+----- * JTEST void ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} [000293] ----------- IL_OFFSET void INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -c---+----- t66 = CNS_INT int 0x3F0000 $47 /--* t65 int +--* t66 int N005 ( 5, 7) [000069] -----+-N--- * TEST void N006 ( 7, 9) [000070] -----+----- JCC void cond=UNE ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} [000294] ----------- IL_OFFSET void INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000085] -----+----- t85 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -c---+----- t86 = CNS_INT int -0x10000 $48 /--* t85 int +--* t86 int N003 ( 3, 4) [000087] -----+----- t87 = * AND int /--* t87 int N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} [000295] ----------- IL_OFFSET void INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000071] -----+----- t71 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -c---+----- t72 = CNS_INT int -0x10000 $48 /--* t71 int +--* t72 int N003 ( 3, 4) [000073] -----+----- t73 = * ADD int /--* t73 int N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} [000296] ----------- IL_OFFSET void INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 /--* t78 long +--* t76 int +--* t80 int N004 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int $11a N005 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 (last use) /--* t81 int +--* t82 int N006 (255, 10) [000083] -A-XG+-N-U- * CMP void N007 (255, 12) [000084] -A-XG+----- JCC void cond=UNE ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} [000297] ----------- IL_OFFSET void INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000035] -----+----- t35 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -c---+----- t114 = CNS_INT int 0x3FFFFFF $49 /--* t35 int +--* t114 int N003 ( 3, 6) [000115] -----+----- t115 = * AND int /--* t115 int N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void [000298] ----------- IL_OFFSET void INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -c---+----- t121 = CNS_INT int 0xC000000 $4a /--* t117 int +--* t121 int N003 ( 3, 6) [000122] -----+----- t122 = * AND int N004 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 $46 /--* t122 int +--* t123 int N005 ( 5, 11) [000124] -----+-N--- * CMP void N006 ( 7, 13) [000041] -----+----- JCC void cond=UEQ ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} [000299] ----------- IL_OFFSET void INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class $147 /--* t52 long [000319] ----------- t319 = * PUTARG_REG long REG x0 /--* t319 long arg0 in x0 N002 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST $298 /--* t53 ref N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void [000300] ----------- IL_OFFSET void INL01 @ ??? <- INLRT @ 0x000[E-] N001 ( 3, 2) [000055] -----+----- t55 = LCL_VAR ref V08 tmp7 u:2 $298 /--* t55 ref [000320] ----------- t320 = * PUTARG_REG ref REG x0 /--* t320 ref this in x0 N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void [000301] ----------- IL_OFFSET void INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000057] -----+----- t57 = LCL_VAR ref V08 tmp7 u:2 (last use) $298 /--* t57 ref [000321] ----------- t321 = * PUTARG_REG ref REG x0 /--* t321 ref arg0 in x0 N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} [000302] ----------- IL_OFFSET void INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000133] H----+----- t133 = CNS_INT(h) long 0x4208C8 static base addr cell $142 /--* t133 long N002 ( 5, 10) [000134] #----+----- t134 = * IND long $380 /--* t134 long N004 ( 7, 13) [000136] -c---+----- t136 = * LEA(b+16) long /--* t136 long N005 ( 8, 12) [000137] ---XG+----- t137 = * IND ref /--* t137 ref N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 [000303] ----------- IL_OFFSET void INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000140] -----+----- t140 = LCL_VAR ref V13 tmp12 u:2 /--* t140 ref N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte [000304] ----------- IL_OFFSET void INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000139] -----+----- t139 = LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -c---+----- t234 = CNS_INT long 16 $1c3 /--* t139 ref +--* t234 long N003 ( 2, 5) [000235] -----+-N--- t235 = * ADD byref N005 ( 3, 2) [000126] -----+----- t126 = LCL_VAR int V06 tmp5 u:1 (last use) /--* t126 int N006 ( 4, 4) [000144] -c---+----- t144 = * CAST long <- int N007 ( 1, 2) [000145] -c---+----- t145 = CNS_INT long 5 $1c4 /--* t144 long +--* t145 long N008 ( 6, 7) [000146] -----+----- t146 = * BFIZ long /--* t235 byref +--* t146 long N009 ( 9, 13) [000147] -c---+----- t147 = * LEA(b+(i*1)+0) byref /--* t147 byref N010 ( 11, 14) [000130] ---XG+----- t130 = * IND ref /--* t130 ref N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 [000305] ----------- IL_OFFSET void INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] N001 ( 1, 2) [000047] -c---+----- t47 = CNS_INT long 0 $1c2 /--* t47 long N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void [000306] ----------- IL_OFFSET void INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 /--* t49 ref N003 ( 3, 4) [000238] -c---+----- t238 = * LEA(b+16) byref /--* t238 byref N004 ( 4, 3) [000150] ---XG+----- t150 = * IND int N005 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 (last use) /--* t150 int +--* t50 int N006 ( 6, 5) [000151] ---XG+-N--- * CMP void N007 ( 8, 7) [000152] ---XG+----- JCC void cond=UEQ ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} [000307] ----------- IL_OFFSET void INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} [000308] ----------- IL_OFFSET void INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000153] ----------- t153 = LCL_VAR ref V07 tmp6 u:2 /--* t153 ref N003 ( 3, 4) [000240] -c--------- t240 = * LEA(b+24) byref /--* t240 byref N004 ( 4, 3) [000158] n---GO----- t158 = * IND int /--* t158 int N005 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 N006 ( 3, 2) [000260] ----------- t260 = LCL_VAR int V21 cse0 u:1 N008 ( 1, 2) [000159] -c--------- t159 = CNS_INT int 0 $40 /--* t260 int +--* t159 int N010 ( 15, 13) [000161] -A--GO----- * JCMP void ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} [000309] ----------- IL_OFFSET void INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000170] ----------- t170 = LCL_VAR ref V07 tmp6 u:2 /--* t170 ref N003 ( 3, 4) [000246] -c--------- t246 = * LEA(b+16) byref N004 ( 1, 2) [000171] -c--------- t171 = CNS_INT int 0 $40 /--* t246 byref +--* t171 int N005 ( 6, 6) [000173] nA--GO----- * STOREIND int [000310] ----------- IL_OFFSET void INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000249] -----+----- t249 = LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -c---+----- t250 = CNS_INT long 20 Fseq[_state] $1c6 /--* t249 ref +--* t250 long N003 ( 3, 4) [000251] -----+----- t251 = * ADD byref N004 ( 1, 2) [000203] -c---+----- t203 = CNS_INT int -1 $41 /--* t251 byref +--* t203 int N005 ( 5, 7) [000204] -A-XG+----- t204 = * XADD int N006 ( 1, 2) [000205] -c---+----- t205 = CNS_INT int -1 $41 /--* t204 int +--* t205 int N007 ( 7, 10) [000206] -A-XG+----- t206 = * ADD int /--* t206 int N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 [000311] ----------- IL_OFFSET void INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000209] -----+----- t209 = LCL_VAR int V17 tmp16 u:1 $13a /--* t209 int N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void [000312] ----------- IL_OFFSET void INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 (last use) $13a N002 ( 1, 2) [000217] -c---+----- t217 = CNS_INT int 128 $4d /--* t216 int +--* t217 int N003 ( 3, 4) [000218] -----+-N-U- * CMP void N004 ( 5, 6) [000183] -----+----- JCC void cond=ULT ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} [000313] ----------- IL_OFFSET void INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000184] -----+----- t184 = LCL_VAR ref V07 tmp6 u:2 (last use) /--* t184 ref [000322] ----------- t322 = * PUTARG_REG ref REG x0 N002 ( 3, 2) [000185] -----+----- t185 = LCL_VAR int V19 tmp18 u:1 (last use) $13a /--* t185 int [000323] ----------- t323 = * PUTARG_REG int REG x1 /--* t322 ref this in x0 +--* t323 int arg1 in x1 N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} [000314] ----------- IL_OFFSET void INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000262] ----------- t262 = LCL_VAR int V21 cse0 u:1 N002 ( 1, 2) [000166] -c--------- t166 = CNS_INT int -1 $41 /--* t262 int +--* t166 int N003 ( 5, 5) [000167] ----G------ t167 = * ADD int N004 ( 1, 1) [000162] ----------- t162 = LCL_VAR ref V07 tmp6 u:2 (last use) /--* t162 ref N006 ( 3, 4) [000242] -c--------- t242 = * LEA(b+24) byref /--* t242 byref +--* t167 int N007 ( 10, 9) [000169] nA--GO----- * STOREIND int ------------ BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} [000315] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 2) [000092] -c---+----- t92 = CNS_INT byref 0 $VN.Null /--* t92 byref N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void [000316] ----------- IL_OFFSET void INLRT @ 0x006[E-] N001 ( 0, 0) [000002] -----+----- RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V23: refCnt = 1, refCntWtd = 2 New refCnts for V23: refCnt = 2, refCntWtd = 4 New refCnts for V22: refCnt = 1, refCntWtd = 2 New refCnts for V22: refCnt = 2, refCntWtd = 4 New refCnts for V23: refCnt = 3, refCntWtd = 4 New refCnts for V22: refCnt = 3, refCntWtd = 4 New refCnts for V22: refCnt = 4, refCntWtd = 6 New refCnts for V22: refCnt = 5, refCntWtd = 8 New refCnts for V22: refCnt = 6, refCntWtd = 10 New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 2, refCntWtd = 2 New refCnts for V02: refCnt = 3, refCntWtd = 3 New refCnts for V02: refCnt = 4, refCntWtd = 4 New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V20: refCnt = 1, refCntWtd = 2 New refCnts for V20: refCnt = 2, refCntWtd = 4 New refCnts for V04: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 2, refCntWtd = 9 New refCnts for V05: refCnt = 1, refCntWtd = 8 New refCnts for V05: refCnt = 2, refCntWtd = 16 New refCnts for V02: refCnt = 5, refCntWtd = 12 New refCnts for V05: refCnt = 3, refCntWtd = 20 New refCnts for V05: refCnt = 4, refCntWtd = 24 New refCnts for V05: refCnt = 5, refCntWtd = 26 New refCnts for V09: refCnt = 1, refCntWtd = 2 New refCnts for V05: refCnt = 6, refCntWtd = 28 New refCnts for V09: refCnt = 2, refCntWtd = 4 New refCnts for V04: refCnt = 3, refCntWtd = 13 New refCnts for V09: refCnt = 3, refCntWtd = 8 New refCnts for V05: refCnt = 7, refCntWtd = 32 New refCnts for V05: refCnt = 8, refCntWtd = 36 New refCnts for V05: refCnt = 9, refCntWtd = 36.50 New refCnts for V06: refCnt = 1, refCntWtd = 0.50 New refCnts for V05: refCnt = 10, refCntWtd = 37 New refCnts for V08: refCnt = 1, refCntWtd = 0 New refCnts for V08: refCnt = 2, refCntWtd = 0 New refCnts for V08: refCnt = 3, refCntWtd = 0 New refCnts for V13: refCnt = 1, refCntWtd = 1 New refCnts for V13: refCnt = 2, refCntWtd = 2 New refCnts for V13: refCnt = 3, refCntWtd = 3 New refCnts for V06: refCnt = 2, refCntWtd = 1 New refCnts for V07: refCnt = 1, refCntWtd = 0.50 New refCnts for V03: refCnt = 3, refCntWtd = 2.50 New refCnts for V07: refCnt = 2, refCntWtd = 1 New refCnts for V02: refCnt = 6, refCntWtd = 12.50 New refCnts for V07: refCnt = 3, refCntWtd = 1.50 New refCnts for V21: refCnt = 1, refCntWtd = 0.50 New refCnts for V21: refCnt = 2, refCntWtd = 1 New refCnts for V07: refCnt = 4, refCntWtd = 2 New refCnts for V07: refCnt = 5, refCntWtd = 2.50 New refCnts for V17: refCnt = 1, refCntWtd = 1 New refCnts for V17: refCnt = 2, refCntWtd = 2 New refCnts for V19: refCnt = 1, refCntWtd = 0.50 New refCnts for V19: refCnt = 2, refCntWtd = 1 New refCnts for V07: refCnt = 6, refCntWtd = 3 New refCnts for V19: refCnt = 3, refCntWtd = 1.50 New refCnts for V21: refCnt = 3, refCntWtd = 1.50 New refCnts for V07: refCnt = 7, refCntWtd = 3.50 New refCnts for V03: refCnt = 4, refCntWtd = 3.50 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 4, refCntWtd = 4 *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 arg0 ref class-hnd single-def ; V01 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V02 tmp1 int "Inline stloc first use temp" ; V03 tmp2 byref pinned "Inline stloc first use temp" ; V04 tmp3 long "Inline stloc first use temp" ; V05 tmp4 int "Inline stloc first use temp" ; V06 tmp5 int ld-addr-op "Inline ldloca(s) first use temp" ; V07 tmp6 ref class-hnd exact single-def "Inline stloc first use temp" ; V08 tmp7 ref class-hnd exact single-def "NewObj constructor temp" ; V09 tmp8 int ; V10 tmp9 int "Inline stloc first use temp" ; V11 tmp10 long "Inlining Arg" ; V12 tmp11 int "Inlining Arg" ; V13 tmp12 ref single-def "MemoryMarshal.GetArrayDataReference array" ; V14 tmp13 struct ld-addr-op "Inline stloc first use temp" ; V15 tmp14 struct ld-addr-op "NewObj constructor temp" ; V16 tmp15 byref "Inlining Arg" ; V17 tmp16 int "Inlining Arg" ; V18 tmp17 int "field V14._state (fldOffset=0x0)" P-INDEP ; V19 tmp18 int "field V15._state (fldOffset=0x0)" P-INDEP ; V20 tmp19 long "Cast away GC" ; V21 cse0 int "CSE #01: moderate" ; V22 rat0 ref "Final offset" ; V23 rat1 long "TlsRootAddr access" In fgLocalVarLivenessInit Local V01 should not be enregistered because: struct size does not match reg size Tracked variable (15 out of 24) table: V05 tmp4 [ int]: refCnt = 10, refCntWtd = 37 V04 tmp3 [ long]: refCnt = 3, refCntWtd = 13 V02 tmp1 [ int]: refCnt = 6, refCntWtd = 12.50 V22 rat0 [ ref]: refCnt = 6, refCntWtd = 10 V09 tmp8 [ int]: refCnt = 3, refCntWtd = 8 V00 arg0 [ ref]: refCnt = 4, refCntWtd = 4 V23 rat1 [ long]: refCnt = 3, refCntWtd = 4 V20 tmp19 [ long]: refCnt = 2, refCntWtd = 4 V07 tmp6 [ ref]: refCnt = 7, refCntWtd = 3.50 V13 tmp12 [ ref]: refCnt = 3, refCntWtd = 3 V17 tmp16 [ int]: refCnt = 2, refCntWtd = 2 V19 tmp18 [ int]: refCnt = 3, refCntWtd = 1.50 V21 cse0 [ int]: refCnt = 3, refCntWtd = 1.50 V06 tmp5 [ int]: refCnt = 2, refCntWtd = 1 V08 tmp7 [ ref]: refCnt = 3, refCntWtd = 0 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V00} DEF(0)={ } BB02 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB03 USE(0)={ } + ByrefExposed + GcHeap DEF(2)={V22 V23} + ByrefExposed* + GcHeap* BB22 USE(1)={ V23} + ByrefExposed + GcHeap DEF(1)={V22 } + ByrefExposed* + GcHeap* BB23 USE(1)={V22} DEF(1)={V22} BB20 USE(2)={ V22 V00 } + ByrefExposed + GcHeap DEF(3)={V04 V02 V20} BB04 USE(2)={ V04 V02} + ByrefExposed + GcHeap DEF(1)={V05 } BB05 USE(1)={V05} DEF(0)={ } BB06 USE(1)={V05} DEF(0)={ } BB07 USE(1)={V05 } DEF(1)={ V09} BB08 USE(1)={V05 } DEF(1)={ V09} BB09 USE(3)={V05 V04 V09} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB10 USE(1)={V05 } DEF(1)={ V06} BB11 USE(0)={ } + ByrefExposed + GcHeap DEF(1)={V08} + ByrefExposed* + GcHeap* BB12 USE(2)={V02 V06} + ByrefExposed + GcHeap DEF(2)={ V07 V13 } BB13 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB14 USE(1)={V07 } + ByrefExposed + GcHeap DEF(1)={ V21} BB15 USE(1)={V07 } + ByrefExposed + GcHeap DEF(2)={ V17 V19} + ByrefExposed* + GcHeap* BB16 USE(2)={V07 V19} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB17 USE(2)={V07 V21} DEF(0)={ } + ByrefExposed + GcHeap BB18 USE(0)={} DEF(0)={} ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (1)={V00} + ByrefExposed + GcHeap OUT(1)={V00} + ByrefExposed + GcHeap BB02 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} BB03 IN (1)={ V00 } + ByrefExposed + GcHeap OUT(3)={V22 V00 V23} + ByrefExposed + GcHeap BB22 IN (2)={ V00 V23} + ByrefExposed + GcHeap OUT(2)={V22 V00 } + ByrefExposed + GcHeap BB23 IN (2)={V22 V00} + ByrefExposed + GcHeap OUT(2)={V22 V00} + ByrefExposed + GcHeap BB20 IN (2)={ V22 V00} + ByrefExposed + GcHeap OUT(2)={V04 V02 } + ByrefExposed + GcHeap BB04 IN (2)={ V04 V02} + ByrefExposed + GcHeap OUT(3)={V05 V04 V02} + ByrefExposed + GcHeap BB05 IN (3)={V05 V04 V02} + ByrefExposed + GcHeap OUT(3)={V05 V04 V02} + ByrefExposed + GcHeap BB06 IN (3)={V05 V04 V02} + ByrefExposed + GcHeap OUT(3)={V05 V04 V02} + ByrefExposed + GcHeap BB07 IN (3)={V05 V04 V02 } + ByrefExposed + GcHeap OUT(4)={V05 V04 V02 V09} + ByrefExposed + GcHeap BB08 IN (3)={V05 V04 V02 } + ByrefExposed + GcHeap OUT(4)={V05 V04 V02 V09} + ByrefExposed + GcHeap BB09 IN (4)={V05 V04 V02 V09} + ByrefExposed + GcHeap OUT(2)={ V04 V02 } + ByrefExposed + GcHeap BB10 IN (2)={V05 V02 } + ByrefExposed + GcHeap OUT(2)={ V02 V06} + ByrefExposed + GcHeap BB11 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} BB12 IN (2)={V02 V06} + ByrefExposed + GcHeap OUT(1)={ V07 } + ByrefExposed + GcHeap BB13 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} BB14 IN (1)={V07 } + ByrefExposed + GcHeap OUT(2)={V07 V21} + ByrefExposed + GcHeap BB15 IN (1)={V07 } + ByrefExposed + GcHeap OUT(2)={V07 V19} + ByrefExposed + GcHeap BB16 IN (2)={V07 V19} + ByrefExposed + GcHeap OUT(0)={ } BB17 IN (2)={V07 V21} OUT(0)={ } BB18 IN (0)={} OUT(0)={} *************** In fgUpdateFlowGraph() Before updating the flow graph: --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i LIR BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i LIR hascall nullcheck BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i LIR BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i LIR nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V23: refCnt = 1, refCntWtd = 2 New refCnts for V23: refCnt = 2, refCntWtd = 4 New refCnts for V22: refCnt = 1, refCntWtd = 2 New refCnts for V22: refCnt = 2, refCntWtd = 4 New refCnts for V23: refCnt = 3, refCntWtd = 4 New refCnts for V22: refCnt = 3, refCntWtd = 4 New refCnts for V22: refCnt = 4, refCntWtd = 6 New refCnts for V22: refCnt = 5, refCntWtd = 8 New refCnts for V22: refCnt = 6, refCntWtd = 10 New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 2, refCntWtd = 2 New refCnts for V02: refCnt = 3, refCntWtd = 3 New refCnts for V02: refCnt = 4, refCntWtd = 4 New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V20: refCnt = 1, refCntWtd = 2 New refCnts for V20: refCnt = 2, refCntWtd = 4 New refCnts for V04: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 2, refCntWtd = 9 New refCnts for V05: refCnt = 1, refCntWtd = 8 New refCnts for V05: refCnt = 2, refCntWtd = 16 New refCnts for V02: refCnt = 5, refCntWtd = 12 New refCnts for V05: refCnt = 3, refCntWtd = 20 New refCnts for V05: refCnt = 4, refCntWtd = 24 New refCnts for V05: refCnt = 5, refCntWtd = 26 New refCnts for V09: refCnt = 1, refCntWtd = 2 New refCnts for V05: refCnt = 6, refCntWtd = 28 New refCnts for V09: refCnt = 2, refCntWtd = 4 New refCnts for V04: refCnt = 3, refCntWtd = 13 New refCnts for V09: refCnt = 3, refCntWtd = 8 New refCnts for V05: refCnt = 7, refCntWtd = 32 New refCnts for V05: refCnt = 8, refCntWtd = 36 New refCnts for V05: refCnt = 9, refCntWtd = 36.50 New refCnts for V06: refCnt = 1, refCntWtd = 0.50 New refCnts for V05: refCnt = 10, refCntWtd = 37 New refCnts for V08: refCnt = 1, refCntWtd = 0 New refCnts for V08: refCnt = 2, refCntWtd = 0 New refCnts for V08: refCnt = 3, refCntWtd = 0 New refCnts for V13: refCnt = 1, refCntWtd = 1 New refCnts for V13: refCnt = 2, refCntWtd = 2 New refCnts for V13: refCnt = 3, refCntWtd = 3 New refCnts for V06: refCnt = 2, refCntWtd = 1 New refCnts for V07: refCnt = 1, refCntWtd = 0.50 New refCnts for V03: refCnt = 3, refCntWtd = 2.50 New refCnts for V07: refCnt = 2, refCntWtd = 1 New refCnts for V02: refCnt = 6, refCntWtd = 12.50 New refCnts for V07: refCnt = 3, refCntWtd = 1.50 New refCnts for V21: refCnt = 1, refCntWtd = 0.50 New refCnts for V21: refCnt = 2, refCntWtd = 1 New refCnts for V07: refCnt = 4, refCntWtd = 2 New refCnts for V07: refCnt = 5, refCntWtd = 2.50 New refCnts for V17: refCnt = 1, refCntWtd = 1 New refCnts for V17: refCnt = 2, refCntWtd = 2 New refCnts for V19: refCnt = 1, refCntWtd = 0.50 New refCnts for V19: refCnt = 2, refCntWtd = 1 New refCnts for V07: refCnt = 6, refCntWtd = 3 New refCnts for V19: refCnt = 3, refCntWtd = 1.50 New refCnts for V21: refCnt = 3, refCntWtd = 1.50 New refCnts for V07: refCnt = 7, refCntWtd = 3.50 New refCnts for V03: refCnt = 4, refCntWtd = 3.50 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 4, refCntWtd = 4 *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i LIR BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i LIR hascall nullcheck BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i LIR BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i LIR nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} [000281] ----------- IL_OFFSET void INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR ref V00 arg0 u:1 $80 N002 ( 1, 2) [000095] -c---+----- t95 = CNS_INT ref null $VN.Null /--* t0 ref +--* t95 ref N004 ( 5, 6) [000097] -----+----- * JCMP void ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} [000282] ----------- IL_OFFSET void INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000222] H----+----- t222 = CNS_INT(h) ref '"obj"' $500 /--* t222 ref [000317] ----------- t317 = * PUTARG_REG ref REG x0 /--* t317 ref arg0 in x0 N002 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) $VN.Void ------------ BB03 [0015] [???..???) -> BB23(1),BB22(0) (cond), preds={BB01} succs={BB22,BB23} [000283] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN /--* t265 long calli tgt N002 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long /--* t266 long N003 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 N001 ( 3, 2) [000268] ----------- t268 = LCL_VAR long V23 rat1 /--* t268 long N002 ( 6, 4) [000269] #---------- t269 = * IND ref /--* t269 ref N003 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 N001 ( 3, 2) [000272] ----------- t272 = LCL_VAR ref V22 rat0 N002 ( 1, 2) [000271] -c--------- t271 = CNS_INT long 0 /--* t272 ref +--* t271 long N004 ( 10, 7) [000274] ----------- * JCMP void ------------ BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} [000284] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 (last use) /--* t277 long [000318] ----------- t318 = * PUTARG_REG long REG x0 N002 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls /--* t318 long arg0 in x0 +--* t275 long calli tgt N003 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref /--* t276 ref N004 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 ------------ BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} [000285] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000279] ----------- t279 = LCL_VAR ref V22 rat0 (last use) /--* t279 ref N002 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 ------------ BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} [000286] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000263] ----------- t263 = LCL_VAR ref V22 rat0 (last use) /--* t263 ref N003 ( 5, 5) [000103] -c---+----- t103 = * LEA(b+40) byref /--* t103 byref N004 ( 6, 4) [000104] n---G+----- t104 = * IND int /--* t104 int N005 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 $VN.Void [000287] ----------- IL_OFFSET void INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000008] -----+----- t8 = LCL_VAR int V02 tmp1 u:1 N002 ( 1, 1) [000009] -----+----- t9 = LCL_VAR int V02 tmp1 u:1 (last use) N003 ( 1, 2) [000010] -c---+----- t10 = CNS_INT int -1 $41 /--* t9 int +--* t10 int N004 ( 3, 4) [000011] -----+----- t11 = * ADD int N005 ( 1, 2) [000012] -c---+----- t12 = CNS_INT int 31 $42 /--* t11 int +--* t12 int N006 ( 5, 7) [000013] -c---+----- t13 = * RSH int /--* t8 int +--* t13 int N007 ( 7, 9) [000014] -----+----- t14 = * OR int /--* t14 int N008 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 $VN.Void [000288] ----------- IL_OFFSET void INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000225] -------N--- t225 = LCL_VAR ref V00 arg0 u:1 (last use) $80 /--* t225 ref N002 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 $281 [000289] ----------- IL_OFFSET void INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000020] -----+----- t20 = LCL_VAR byref V03 tmp2 $182 /--* t20 byref N002 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 $VN.Void N003 ( 1, 1) [000228] -----+----- t228 = LCL_VAR long V20 tmp19 u:1 (last use) $2c0 N005 ( 1, 2) [000110] -c---+----- t110 = CNS_INT long -4 $1c1 /--* t228 long +--* t110 long N006 ( 4, 7) [000111] -A---+----- t111 = * ADD long $2c1 /--* t111 long N007 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 $VN.Void ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} [000290] ----------- IL_OFFSET void INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000025] -----+----- t25 = LCL_VAR long V04 tmp3 u:1 $2c1 /--* t25 long N002 ( 3, 2) [000026] ---XG+----- t26 = * IND int /--* t26 int N003 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 $284 [000291] ----------- IL_OFFSET void INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 /--* t28 int N002 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int N003 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 /--* t31 int +--* t32 int N004 ( 4, 5) [000033] -----+-N-U- * CMP void N005 ( 6, 7) [000034] -----+----- JCC void cond=UNE ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} [000292] ----------- IL_OFFSET void INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000059] -----+----- t59 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000060] -c---+----- t60 = CNS_INT int 0x8000000 $46 /--* t59 int +--* t60 int N006 ( 7, 11) [000064] -----+----- * JTEST void ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} [000293] ----------- IL_OFFSET void INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000066] -c---+----- t66 = CNS_INT int 0x3F0000 $47 /--* t65 int +--* t66 int N005 ( 5, 7) [000069] -----+-N--- * TEST void N006 ( 7, 9) [000070] -----+----- JCC void cond=UNE ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} [000294] ----------- IL_OFFSET void INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000085] -----+----- t85 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000086] -c---+----- t86 = CNS_INT int -0x10000 $48 /--* t85 int +--* t86 int N003 ( 3, 4) [000087] -----+----- t87 = * AND int /--* t87 int N004 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 $VN.Void ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} [000295] ----------- IL_OFFSET void INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000071] -----+----- t71 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 2) [000072] -c---+----- t72 = CNS_INT int -0x10000 $48 /--* t71 int +--* t72 int N003 ( 3, 4) [000073] -----+----- t73 = * ADD int /--* t73 int N004 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 $VN.Void ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} [000296] ----------- IL_OFFSET void INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 $2c1 N002 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 (last use) $340 N003 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 /--* t78 long +--* t76 int +--* t80 int N004 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int $11a N005 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 (last use) /--* t81 int +--* t82 int N006 (255, 10) [000083] -A-XG+-N-U- * CMP void N007 (255, 12) [000084] -A-XG+----- JCC void cond=UNE ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} [000297] ----------- IL_OFFSET void INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000035] -----+----- t35 = LCL_VAR int V05 tmp4 u:1 N002 ( 1, 4) [000114] -c---+----- t114 = CNS_INT int 0x3FFFFFF $49 /--* t35 int +--* t114 int N003 ( 3, 6) [000115] -----+----- t115 = * AND int /--* t115 int N004 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 $VN.Void [000298] ----------- IL_OFFSET void INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 (last use) N002 ( 1, 4) [000121] -c---+----- t121 = CNS_INT int 0xC000000 $4a /--* t117 int +--* t121 int N003 ( 3, 6) [000122] -----+----- t122 = * AND int N004 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 $46 /--* t122 int +--* t123 int N005 ( 5, 11) [000124] -----+-N--- * CMP void N006 ( 7, 13) [000041] -----+----- JCC void cond=UEQ ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} [000299] ----------- IL_OFFSET void INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class $147 /--* t52 long [000319] ----------- t319 = * PUTARG_REG long REG x0 /--* t319 long arg0 in x0 N002 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST $298 /--* t53 ref N003 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 $VN.Void [000300] ----------- IL_OFFSET void INL01 @ ??? <- INLRT @ 0x000[E-] N001 ( 3, 2) [000055] -----+----- t55 = LCL_VAR ref V08 tmp7 u:2 $298 /--* t55 ref [000320] ----------- t320 = * PUTARG_REG ref REG x0 /--* t320 ref this in x0 N002 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this $VN.Void [000301] ----------- IL_OFFSET void INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000057] -----+----- t57 = LCL_VAR ref V08 tmp7 u:2 (last use) $298 /--* t57 ref [000321] ----------- t321 = * PUTARG_REG ref REG x0 /--* t321 ref arg0 in x0 N002 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW $29a ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} [000302] ----------- IL_OFFSET void INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001 ( 2, 8) [000133] H----+----- t133 = CNS_INT(h) long 0x4208C8 static base addr cell $142 /--* t133 long N002 ( 5, 10) [000134] #----+----- t134 = * IND long $380 /--* t134 long N004 ( 7, 13) [000136] -c---+----- t136 = * LEA(b+16) long /--* t136 long N005 ( 8, 12) [000137] ---XG+----- t137 = * IND ref /--* t137 ref N006 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 $289 [000303] ----------- IL_OFFSET void INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000140] -----+----- t140 = LCL_VAR ref V13 tmp12 u:2 /--* t140 ref N002 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte [000304] ----------- IL_OFFSET void INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000139] -----+----- t139 = LCL_VAR ref V13 tmp12 u:2 (last use) N002 ( 1, 2) [000234] -c---+----- t234 = CNS_INT long 16 $1c3 /--* t139 ref +--* t234 long N003 ( 2, 5) [000235] -----+-N--- t235 = * ADD byref N005 ( 3, 2) [000126] -----+----- t126 = LCL_VAR int V06 tmp5 u:1 (last use) /--* t126 int N006 ( 4, 4) [000144] -c---+----- t144 = * CAST long <- int N007 ( 1, 2) [000145] -c---+----- t145 = CNS_INT long 5 $1c4 /--* t144 long +--* t145 long N008 ( 6, 7) [000146] -----+----- t146 = * BFIZ long /--* t235 byref +--* t146 long N009 ( 9, 13) [000147] -c---+----- t147 = * LEA(b+(i*1)+0) byref /--* t147 byref N010 ( 11, 14) [000130] ---XG+----- t130 = * IND ref /--* t130 ref N011 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 [000305] ----------- IL_OFFSET void INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] N001 ( 1, 2) [000047] -c---+----- t47 = CNS_INT long 0 $1c2 /--* t47 long N002 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void [000306] ----------- IL_OFFSET void INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 /--* t49 ref N003 ( 3, 4) [000238] -c---+----- t238 = * LEA(b+16) byref /--* t238 byref N004 ( 4, 3) [000150] ---XG+----- t150 = * IND int N005 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 (last use) /--* t150 int +--* t50 int N006 ( 6, 5) [000151] ---XG+-N--- * CMP void N007 ( 8, 7) [000152] ---XG+----- JCC void cond=UEQ ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} [000307] ----------- IL_OFFSET void INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 14, 2) [000155] --CXG+----- CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() $VN.Void ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} [000308] ----------- IL_OFFSET void INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000153] ----------- t153 = LCL_VAR ref V07 tmp6 u:2 /--* t153 ref N003 ( 3, 4) [000240] -c--------- t240 = * LEA(b+24) byref /--* t240 byref N004 ( 4, 3) [000158] n---GO----- t158 = * IND int /--* t158 int N005 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 N006 ( 3, 2) [000260] ----------- t260 = LCL_VAR int V21 cse0 u:1 N008 ( 1, 2) [000159] -c--------- t159 = CNS_INT int 0 $40 /--* t260 int +--* t159 int N010 ( 15, 13) [000161] -A--GO----- * JCMP void ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} [000309] ----------- IL_OFFSET void INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000170] ----------- t170 = LCL_VAR ref V07 tmp6 u:2 /--* t170 ref N003 ( 3, 4) [000246] -c--------- t246 = * LEA(b+16) byref N004 ( 1, 2) [000171] -c--------- t171 = CNS_INT int 0 $40 /--* t246 byref +--* t171 int N005 ( 6, 6) [000173] nA--GO----- * STOREIND int [000310] ----------- IL_OFFSET void INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000249] -----+----- t249 = LCL_VAR ref V07 tmp6 u:2 N002 ( 1, 2) [000250] -c---+----- t250 = CNS_INT long 20 Fseq[_state] $1c6 /--* t249 ref +--* t250 long N003 ( 3, 4) [000251] -----+----- t251 = * ADD byref N004 ( 1, 2) [000203] -c---+----- t203 = CNS_INT int -1 $41 /--* t251 byref +--* t203 int N005 ( 5, 7) [000204] -A-XG+----- t204 = * XADD int N006 ( 1, 2) [000205] -c---+----- t205 = CNS_INT int -1 $41 /--* t204 int +--* t205 int N007 ( 7, 10) [000206] -A-XG+----- t206 = * ADD int /--* t206 int N008 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 [000311] ----------- IL_OFFSET void INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000209] -----+----- t209 = LCL_VAR int V17 tmp16 u:1 (last use) $13a /--* t209 int N002 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 $VN.Void [000312] ----------- IL_OFFSET void INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 $13a N002 ( 1, 2) [000217] -c---+----- t217 = CNS_INT int 128 $4d /--* t216 int +--* t217 int N003 ( 3, 4) [000218] -----+-N-U- * CMP void N004 ( 5, 6) [000183] -----+----- JCC void cond=ULT ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} [000313] ----------- IL_OFFSET void INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 1, 1) [000184] -----+----- t184 = LCL_VAR ref V07 tmp6 u:2 (last use) /--* t184 ref [000322] ----------- t322 = * PUTARG_REG ref REG x0 N002 ( 3, 2) [000185] -----+----- t185 = LCL_VAR int V19 tmp18 u:1 (last use) $13a /--* t185 int [000323] ----------- t323 = * PUTARG_REG int REG x1 /--* t322 ref this in x0 +--* t323 int arg1 in x1 N003 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this $VN.Void ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} [000314] ----------- IL_OFFSET void INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001 ( 3, 2) [000262] ----------- t262 = LCL_VAR int V21 cse0 u:1 (last use) N002 ( 1, 2) [000166] -c--------- t166 = CNS_INT int -1 $41 /--* t262 int +--* t166 int N003 ( 5, 5) [000167] ----G------ t167 = * ADD int N004 ( 1, 1) [000162] ----------- t162 = LCL_VAR ref V07 tmp6 u:2 (last use) /--* t162 ref N006 ( 3, 4) [000242] -c--------- t242 = * LEA(b+24) byref /--* t242 byref +--* t167 int N007 ( 10, 9) [000169] nA--GO----- * STOREIND int ------------ BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} [000315] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 2) [000092] -c---+----- t92 = CNS_INT byref 0 $VN.Null /--* t92 byref N002 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 $VN.Void [000316] ----------- IL_OFFSET void INLRT @ 0x006[E-] N001 ( 0, 0) [000002] -----+----- RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Calculate stack level slots *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use: {V00} def: {} in: {V00} out: {V00} BB02 use: {} def: {} in: {} out: {} BB03 use: {} def: {V22 V23} in: {V00} out: {V00 V22 V23} BB22 use: {V23} def: {V22} in: {V00 V23} out: {V00 V22} BB23 use: {V22} def: {V22} in: {V00 V22} out: {V00 V22} BB20 use: {V00 V22} def: {V02 V04 V20} in: {V00 V22} out: {V02 V04} BB04 use: {V02 V04} def: {V05} in: {V02 V04} out: {V02 V04 V05} BB05 use: {V05} def: {} in: {V02 V04 V05} out: {V02 V04 V05} BB06 use: {V05} def: {} in: {V02 V04 V05} out: {V02 V04 V05} BB07 use: {V05} def: {V09} in: {V02 V04 V05} out: {V02 V04 V05 V09} BB08 use: {V05} def: {V09} in: {V02 V04 V05} out: {V02 V04 V05 V09} BB09 use: {V04 V05 V09} def: {} in: {V02 V04 V05 V09} out: {V02 V04} BB10 use: {V05} def: {V06} in: {V02 V05} out: {V02 V06} BB11 use: {} def: {V08} in: {} out: {} BB12 use: {V02 V06} def: {V07 V13} in: {V02 V06} out: {V07} BB13 use: {} def: {} in: {} out: {} BB14 use: {V07} def: {V21} in: {V07} out: {V07 V21} BB15 use: {V07} def: {V17 V19} in: {V07} out: {V07 V19} BB16 use: {V07 V19} def: {} in: {V07 V19} out: {} BB17 use: {V07 V21} def: {} in: {V07 V21} out: {} BB18 use: {} def: {} in: {} out: {} Interval 0: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 0: (V00) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 1: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 1: (V02) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 2: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 2: (V04) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 3: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 3: (V05) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 4: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 4: (V06) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 5: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 5: (V07) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 6: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 6: (V08) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 7: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 7: (V09) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 8: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 8: (V13) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 9: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 9: (V17) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 10: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 10: (V19) int (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 11: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 11: (V20) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 12: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 12: (V21) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 13: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 13: (V22) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 14: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] Interval 14: (V23) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[] FP callee save candidate vars: None floatVarCount = 0; hasLoops = true, singleExit = true ; Decided to create an EBP based frame for ETW stackwalking (BasicBlock Count) *************** In lvaAssignFrameOffsets(REGALLOC_FRAME_LAYOUT) Assign V02 tmp1, size=4, stkOffs=-0x64 Pad V03 tmp2, size=8, stkOffs=-0x6b, pad=7 Assign V03 tmp2, size=8, stkOffs=-0x73 Pad V04 tmp3, size=8, stkOffs=-0x7a, pad=7 Assign V04 tmp3, size=8, stkOffs=-0x82 Assign V05 tmp4, size=4, stkOffs=-0x86 Assign V06 tmp5, size=4, stkOffs=-0x8a Assign V09 tmp8, size=4, stkOffs=-0x8e Assign V10 tmp9, size=4, stkOffs=-0x92 Pad V11 tmp10, size=8, stkOffs=-0x99, pad=7 Assign V11 tmp10, size=8, stkOffs=-0xa1 Assign V12 tmp11, size=4, stkOffs=-0xa5 Pad V14 tmp13, size=8, stkOffs=-0xac, pad=7 Assign V14 tmp13, size=8, stkOffs=-0xb4 Pad V15 tmp14, size=8, stkOffs=-0xbb, pad=7 Assign V15 tmp14, size=8, stkOffs=-0xc3 Pad V16 tmp15, size=8, stkOffs=-0xca, pad=7 Assign V16 tmp15, size=8, stkOffs=-0xd2 Assign V17 tmp16, size=4, stkOffs=-0xd6 Assign V18 tmp17, size=4, stkOffs=-0xda Assign V19 tmp18, size=4, stkOffs=-0xde Pad V20 tmp19, size=8, stkOffs=-0xe5, pad=7 Assign V20 tmp19, size=8, stkOffs=-0xed Assign V21 cse0, size=4, stkOffs=-0xf1 Pad V23 rat1, size=8, stkOffs=-0xf8, pad=7 Assign V23 rat1, size=8, stkOffs=-0x100 Pad V00 arg0, size=8, stkOffs=-0x107, pad=7 Assign V00 arg0, size=8, stkOffs=-0x10f Pad V07 tmp6, size=8, stkOffs=-0x116, pad=7 Assign V07 tmp6, size=8, stkOffs=-0x11e Pad V08 tmp7, size=8, stkOffs=-0x125, pad=7 Assign V08 tmp7, size=8, stkOffs=-0x12d Pad V13 tmp12, size=8, stkOffs=-0x134, pad=7 Assign V13 tmp12, size=8, stkOffs=-0x13c Pad V22 rat0, size=8, stkOffs=-0x143, pad=7 Assign V22 rat0, size=8, stkOffs=-0x14b Setting genSaveFpLrWithAllCalleeSavedRegisters to false --- delta bump 368 for FP frame, 16 inside frame for FP/LR relocation --- virtual stack offset to actual stack offset delta is 368 -- V00 was -271, now 113 -- V01 was 0, now 368 -- V02 was -100, now 284 -- V03 was -115, now 269 -- V04 was -130, now 254 -- V05 was -134, now 250 -- V06 was -138, now 246 -- V07 was -286, now 98 -- V08 was -301, now 83 -- V09 was -142, now 242 -- V10 was -146, now 238 -- V11 was -161, now 223 -- V12 was -165, now 219 -- V13 was -316, now 68 -- V14 was -180, now 204 -- V15 was -195, now 189 -- V16 was -210, now 174 -- V17 was -214, now 170 -- V18 was -218, now 166 -- V19 was -222, now 162 -- V20 was -237, now 147 -- V21 was -241, now 143 -- V22 was -331, now 53 -- V23 was -256, now 128 compRsvdRegCheck frame size = 368 compArgSize = 8 Returning true (ARM64) Reserved REG_OPT_RSVD (xip1) due to large frame TUPLE STYLE DUMP BEFORE LSRA Identifying loops in DFS tree with following reverse post order: RPO -> BB [pre, post] 00 -> BB01[0, 20] 01 -> BB03[2, 19] 02 -> BB23[20, 18] 03 -> BB22[3, 17] 04 -> BB20[4, 16] 05 -> BB04[5, 15] 06 -> BB05[6, 14] 07 -> BB10[12, 13] 08 -> BB12[14, 12] 09 -> BB14[16, 11] 10 -> BB17[19, 10] 11 -> BB15[17, 9] 12 -> BB16[18, 8] 13 -> BB13[15, 7] 14 -> BB11[13, 6] 15 -> BB06[7, 5] 16 -> BB08[11, 4] 17 -> BB07[8, 3] 18 -> BB09[9, 2] 19 -> BB18[10, 1] 20 -> BB02[1, 0] BB09 -> BB04 is a backedge BB04 is the header of a DFS loop with 1 back edges Loop has 6 blocks BB04 -> BB10 is an exit edge BB05 -> BB10 is an exit edge BB09 -> BB18 is an exit edge BB20 -> BB04 is an entry edge Added loop L00 with header BB04 Found 1 loops *************** Natural loop graph L00 header: BB04 Members (6): [BB04..BB09] Entry: BB20 -> BB04 Exit: BB04 -> BB10; BB05 -> BB10; BB09 -> BB18 Back: BB09 -> BB04 Start LSRA Block Sequence: Current block: BB01 Current block: BB03 Current block: BB23 Current block: BB22 Current block: BB20 Current block: BB04 Current block: BB05 Current block: BB06 Current block: BB08 Current block: BB07 Current block: BB09 Current block: BB10 Current block: BB12 Current block: BB14 Current block: BB17 Current block: BB15 Current block: BB16 Current block: BB13 Current block: BB11 Current block: BB18 Current block: BB02 Final LSRA Block Sequence: BB01 ( 1 ) BB03 ( 1 ) BB23 ( 1 ) BB22 ( 0 ) BB20 ( 1 ) BB04 ( 8 ) critical-in critical-out BB05 ( 4 ) critical-out BB06 ( 4 ) BB08 ( 2 ) BB07 ( 2 ) BB09 ( 4 ) critical-out BB10 ( 0.50) critical-in BB12 ( 0.50) BB14 ( 0.50) BB17 ( 0.50) BB15 ( 0.50) critical-out BB16 ( 0.50) BB13 ( 0.50) BB11 ( 0 ) BB18 ( 1 ) critical-in BB02 ( 0.50) BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ===== N000. IL_OFFSET INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N001. V00(t0) N002. CNS_INT null N004. JCMP ; t0 BB03 [0015] [???..???) -> BB23(1),BB22(0) (cond), preds={BB01} succs={BB22,BB23} ===== N000. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001. t265 = CNS_INT(h) 0x420480 UNKNOWN N002. t266 = CALL ind _tls_get_addr; t265 N003. V23(t267); t266 N001. V23(t268) N002. t269 = IND ; t268 N003. V22(t270); t269 N001. V22(t272) N002. CNS_INT 0 N004. JCMP ; t272 BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} ===== N000. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001. V22(t279*) N002. V22(t280); t279* BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} ===== N000. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001. V23(t277*) N000. t318 = PUTARG_REG; t277* N002. t275 = CNS_INT(h) 0x420488 tls N003. t276 = CALL ind ; t318,t275 N004. V22(t278); t276 BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} ===== N000. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N001. V22(t263*) N003. t103 = LEA(b+40); t263* N004. t104 = IND ; t103 N005. V02(t7); t104 N000. IL_OFFSET INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] N001. V02(t8) N002. V02(t9*) N003. CNS_INT -1 N004. t11 = ADD ; t9* N005. CNS_INT 31 N006. t13 = RSH ; t11 N007. t14 = OR ; t8,t13 N008. V02(t15); t14 N000. IL_OFFSET INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] N001. V00(t225*) N002. V03 MEM; t225* N000. IL_OFFSET INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] N001. t20 = V03 MEM N002. V20(t227); t20 N003. V20(t228*) N005. CNS_INT -4 N006. t111 = ADD ; t228* N007. V04(t24); t111 BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} ===== N000. IL_OFFSET INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] N001. V04(t25) N002. t26 = IND ; t25 N003. V05(t27); t26 N000. IL_OFFSET INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] N001. V05(t28) N002. t31 = CAST ; t28 N003. V02(t32) N004. CMP ; t31,t32 N005. JCC cond=UNE BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ===== N000. IL_OFFSET INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] N001. V05(t59) N002. CNS_INT 0x8000000 N006. JTEST ; t59 BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ===== N000. IL_OFFSET INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] N001. V05(t65) N002. CNS_INT 0x3F0000 N005. TEST ; t65 N006. JCC cond=UNE BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ===== N000. IL_OFFSET INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] N001. V05(t71) N002. CNS_INT -0x10000 N003. t73 = ADD ; t71 N004. V09(t74); t73 BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ===== N000. IL_OFFSET INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] N001. V05(t85) N002. CNS_INT -0x10000 N003. t87 = AND ; t85 N004. V09(t88); t87 BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ===== N000. IL_OFFSET INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] N001. V04(t78) N002. V09(t76*) N003. V05(t80) N004. t81 = CMPXCHG ; t78,t76*,t80 N005. V05(t82*) N006. CMP ; t81,t82* N007. JCC cond=UNE BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ===== N000. IL_OFFSET INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N001. V05(t35) N002. CNS_INT 0x3FFFFFF N003. t115 = AND ; t35 N004. V06(t116); t115 N000. IL_OFFSET INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N001. V05(t117*) N002. CNS_INT 0xC000000 N003. t122 = AND ; t117* N004. t123 = CNS_INT 0x8000000 N005. CMP ; t122,t123 N006. JCC cond=UEQ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ===== N000. IL_OFFSET INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001. t133 = CNS_INT(h) 0x4208C8 static base addr cell N002. t134 = IND ; t133 N004. t136 = LEA(b+16); t134 N005. t137 = IND ; t136 N006. V13(t138); t137 N000. IL_OFFSET INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001. V13(t140) N002. NULLCHECK; t140 N000. IL_OFFSET INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N001. V13(t139*) N002. CNS_INT 16 N003. t235 = ADD ; t139* N005. V06(t126*) N006. t144 = CAST ; t126* N007. CNS_INT 5 N008. t146 = BFIZ ; t144 N009. t147 = LEA(b+(i*1)+0); t235,t146 N010. t130 = IND ; t147 N011. V07(t45); t130 N000. IL_OFFSET INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] N001. CNS_INT 0 N002. V03 MEM N000. IL_OFFSET INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001. V07(t49) N003. t238 = LEA(b+16); t49 N004. t150 = IND ; t238 N005. V02(t50*) N006. CMP ; t150,t50* N007. JCC cond=UEQ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ===== N000. IL_OFFSET INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001. V07(t153) N003. t240 = LEA(b+24); t153 N004. t158 = IND ; t240 N005. V21(t259); t158 N006. V21(t260) N008. CNS_INT 0 N010. JCMP ; t260 BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} ===== N000. IL_OFFSET INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001. V21(t262*) N002. CNS_INT -1 N003. t167 = ADD ; t262* N004. V07(t162*) N006. t242 = LEA(b+24); t162* N007. STOREIND ; t242,t167 BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} ===== N000. IL_OFFSET INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001. V07(t170) N003. t246 = LEA(b+16); t170 N004. CNS_INT 0 N005. STOREIND ; t246 N000. IL_OFFSET INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001. V07(t249) N002. CNS_INT 20 Fseq[_state] N003. t251 = ADD ; t249 N004. CNS_INT -1 N005. t204 = XADD ; t251 N006. CNS_INT -1 N007. t206 = ADD ; t204 N008. V17(t212); t206 N000. IL_OFFSET INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001. V17(t209*) N002. V19(t211); t209* N000. IL_OFFSET INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001. V19(t216) N002. CNS_INT 128 N003. CMP ; t216 N004. JCC cond=ULT BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} ===== N000. IL_OFFSET INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001. V07(t184*) N000. t322 = PUTARG_REG; t184* N002. V19(t185*) N000. t323 = PUTARG_REG; t185* N003. CALL ; t322,t323 BB13 [0025] [000..001) (throw), preds={BB12} succs={} ===== N000. IL_OFFSET INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N001. CALL BB11 [0010] [000..001) (throw), preds={BB10} succs={} ===== N000. IL_OFFSET INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] N001. t52 = CNS_INT(h) 0x420818 class N000. t319 = PUTARG_REG; t52 N002. t53 = CALL help; t319 N003. V08(t54); t53 N000. IL_OFFSET INL01 @ ??? <- INLRT @ 0x000[E-] N001. V08(t55) N000. t320 = PUTARG_REG; t55 N002. CALL ; t320 N000. IL_OFFSET INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] N001. V08(t57*) N000. t321 = PUTARG_REG; t57* N002. CALL help; t321 BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} ===== N000. IL_OFFSET INLRT @ 0x000[E-] N001. CNS_INT 0 N002. V03 MEM N000. IL_OFFSET INLRT @ 0x006[E-] N001. RETURN BB02 [0014] [000..001) (throw), preds={BB01} succs={} ===== N000. IL_OFFSET INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N001. t222 = CNS_INT(h) '"obj"' N000. t317 = PUTARG_REG; t222 N002. CALL ; t317 buildIntervals second part ======== Arg V00 in reg x0 BB00 regmask=[x0] minReg=1 fixed wt=100.00> NEW BLOCK BB01 DefList: { } N003 (???,???) [000281] ----------- * IL_OFFSET void INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N005 ( 1, 1) [000000] -----+----- * LCL_VAR ref V00 arg0 u:1 NA REG NA $80 DefList: { } N007 ( 1, 2) [000095] -c---+----- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N009 ( 5, 6) [000097] -----+----- * JCMP void REG NA LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> CHECKING LAST USES for BB01, liveout={V00} ============================== use: {V00} def: {} NEW BLOCK BB03 Setting BB01 as the predecessor for determining incoming variable registers of BB03 DefList: { } N013 (???,???) [000283] ----------- * IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N015 ( 2, 8) [000265] H---------- * CNS_INT(h) long 0x420480 UNKNOWN REG NA Interval 15: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] CNS_INT BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N015.t265. CNS_INT } N017 ( 19, 10) [000266] --CXG------ * CALL ind _tls_get_addr long REG NA BB03 regmask=[x0] minReg=1 wt=100.00> BB03 regmask=[x1] minReg=1 wt=100.00> BB03 regmask=[x2] minReg=1 wt=100.00> BB03 regmask=[x2] minReg=1 last fixed wt=100.00> Interval 16: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] BB03 regmask=[x0] minReg=1 wt=100.00> CALL BB03 regmask=[x0] minReg=1 fixed wt=400.00> DefList: { N017.t266. CALL } N019 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 NA REG NA BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N021 ( 3, 2) [000268] ----------- * LCL_VAR long V23 rat1 NA REG NA DefList: { } N023 ( 6, 4) [000269] #---------- * IND ref REG NA LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Interval 17: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] IND BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N023.t269. IND } N025 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 NA REG NA BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N027 ( 3, 2) [000272] ----------- * LCL_VAR ref V22 rat0 NA REG NA DefList: { } N029 ( 1, 2) [000271] -c--------- * CNS_INT long 0 REG NA Contained DefList: { } N031 ( 10, 7) [000274] ----------- * JCMP void REG NA LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> CHECKING LAST USES for BB03, liveout={V00 V22 V23} ============================== use: {} def: {V22 V23} NEW BLOCK BB23 Setting BB03 as the predecessor for determining incoming variable registers of BB23 DefList: { } N035 (???,???) [000285] ----------- * IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N037 ( 3, 2) [000279] ----------- * LCL_VAR ref V22 rat0 NA (last use) REG NA DefList: { } N039 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 NA REG NA LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Assigning related to STORE_LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> CHECKING LAST USES for BB23, liveout={V00 V22} ============================== use: {V22} def: {V22} NEW BLOCK BB22 Setting BB03 as the predecessor for determining incoming variable registers of BB22 firstColdLoc = 43 DefList: { } N043 (???,???) [000284] ----------- * IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N045 ( 3, 2) [000277] ----------- * LCL_VAR long V23 rat1 NA (last use) REG NA DefList: { } N047 (???,???) [000318] ----------- * PUTARG_REG long REG x0 BB22 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB22 regmask=[x0] minReg=1 last fixed wt=400.00> Interval 18: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] BB22 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB22 regmask=[x0] minReg=1 fixed wt=0.00> DefList: { N047.t318. PUTARG_REG } N049 ( 2, 8) [000275] H---------- * CNS_INT(h) long 0x420488 tls REG NA Interval 19: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] CNS_INT BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> DefList: { N047.t318. PUTARG_REG; N049.t275. CNS_INT } N051 ( 22, 13) [000276] --CXG------ * CALL ind ref REG NA BB22 regmask=[x0] minReg=1 wt=0.00> BB22 regmask=[x0] minReg=1 last fixed wt=0.00> BB22 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> Interval 20: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] BB22 regmask=[x0] minReg=1 wt=0.00> CALL BB22 regmask=[x0] minReg=1 fixed wt=0.00> DefList: { N051.t276. CALL } N053 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 NA REG NA BB22 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> Assigning related to STORE_LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> CHECKING LAST USES for BB22, liveout={V00 V22} ============================== use: {V23} def: {V22} NEW BLOCK BB20 Setting BB23 as the predecessor for determining incoming variable registers of BB20 DefList: { } N057 (???,???) [000286] ----------- * IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N059 ( 3, 2) [000263] ----------- * LCL_VAR ref V22 rat0 NA (last use) REG NA DefList: { } N061 ( 5, 5) [000103] -c---+----- * LEA(b+40) byref REG NA Contained DefList: { } N063 ( 6, 4) [000104] n---G+----- * IND int REG NA LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 21: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] IND BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N063.t104. IND } N065 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 NA REG NA $VN.Void BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> DefList: { } N067 (???,???) [000287] ----------- * IL_OFFSET void INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N069 ( 1, 1) [000008] -----+----- * LCL_VAR int V02 tmp1 u:1 NA REG NA DefList: { } N071 ( 1, 1) [000009] -----+----- * LCL_VAR int V02 tmp1 u:1 NA (last use) REG NA DefList: { } N073 ( 1, 2) [000010] -c---+----- * CNS_INT int -1 REG NA $41 Contained DefList: { } N075 ( 3, 4) [000011] -----+----- * ADD int REG NA LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> Interval 22: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] ADD BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N075.t11. ADD } N077 ( 1, 2) [000012] -c---+----- * CNS_INT int 31 REG NA $42 Contained DefList: { N075.t11. ADD } N079 ( 5, 7) [000013] -c---+----- * RSH int REG NA Contained DefList: { N075.t11. ADD } N081 ( 7, 9) [000014] -----+----- * OR int REG NA LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Interval 23: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] OR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N081.t14. OR } N083 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 NA REG NA $VN.Void BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> DefList: { } N085 (???,???) [000288] ----------- * IL_OFFSET void INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N087 ( 1, 1) [000225] -------N--- * LCL_VAR ref V00 arg0 u:1 NA (last use) REG NA $80 DefList: { } N089 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $281 LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N091 (???,???) [000289] ----------- * IL_OFFSET void INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N093 ( 1, 1) [000020] -----+----- * LCL_VAR byref V03 tmp2 NA REG NA $182 Interval 24: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N093.t20. LCL_VAR } N095 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 NA REG NA $VN.Void BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N097 ( 1, 1) [000228] -----+----- * LCL_VAR long V20 tmp19 u:1 NA (last use) REG NA $2c0 DefList: { } N099 ( 1, 2) [000110] -c---+----- * CNS_INT long -4 REG NA $1c1 Contained DefList: { } N101 ( 4, 7) [000111] -A---+----- * ADD long REG NA $2c1 LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Interval 25: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] ADD BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N101.t111. ADD } N103 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 NA REG NA $VN.Void BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1300.00> CHECKING LAST USES for BB20, liveout={V02 V04} ============================== use: {V00 V22} def: {V02 V04 V20} NEW BLOCK BB04 Setting BB20 as the predecessor for determining incoming variable registers of BB04 DefList: { } N107 (???,???) [000290] ----------- * IL_OFFSET void INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N109 ( 1, 1) [000025] -----+----- * LCL_VAR long V04 tmp3 u:1 NA REG NA $2c1 DefList: { } N111 ( 3, 2) [000026] ---XG+----- * IND int REG NA LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1300.00> Interval 26: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] IND BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N111.t26. IND } N113 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 NA REG NA $284 BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> DefList: { } N115 (???,???) [000291] ----------- * IL_OFFSET void INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N117 ( 1, 1) [000028] -----+----- * LCL_VAR int V05 tmp4 u:1 NA REG NA DefList: { } N119 ( 2, 3) [000031] -----+----- * CAST int <- ushort <- int REG NA LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> Interval 27: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] CAST BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N119.t31. CAST } N121 ( 1, 1) [000032] -----+----- * LCL_VAR int V02 tmp1 u:2 NA REG NA DefList: { N119.t31. CAST } N123 ( 4, 5) [000033] -----+-N-U- * CMP void REG NA BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> DefList: { } N125 ( 6, 7) [000034] -----+----- * JCC void cond=UNE REG NA CHECKING LAST USES for BB04, liveout={V02 V04 V05} ============================== use: {V02 V04} def: {V05} NEW BLOCK BB05 Setting BB04 as the predecessor for determining incoming variable registers of BB05 DefList: { } N129 (???,???) [000292] ----------- * IL_OFFSET void INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N131 ( 1, 1) [000059] -----+----- * LCL_VAR int V05 tmp4 u:1 NA REG NA DefList: { } N133 ( 1, 4) [000060] -c---+----- * CNS_INT int 0x8000000 REG NA $46 Contained DefList: { } N135 ( 7, 11) [000064] -----+----- * JTEST void REG NA LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> CHECKING LAST USES for BB05, liveout={V02 V04 V05} ============================== use: {V05} def: {} NEW BLOCK BB06 Setting BB05 as the predecessor for determining incoming variable registers of BB06 DefList: { } N139 (???,???) [000293] ----------- * IL_OFFSET void INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N141 ( 1, 1) [000065] -----+----- * LCL_VAR int V05 tmp4 u:1 NA REG NA DefList: { } N143 ( 1, 2) [000066] -c---+----- * CNS_INT int 0x3F0000 REG NA $47 Contained DefList: { } N145 ( 5, 7) [000069] -----+-N--- * TEST void REG NA LCL_VAR BB06 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> DefList: { } N147 ( 7, 9) [000070] -----+----- * JCC void cond=UNE REG NA CHECKING LAST USES for BB06, liveout={V02 V04 V05} ============================== use: {V05} def: {} NEW BLOCK BB08 Setting BB06 as the predecessor for determining incoming variable registers of BB08 DefList: { } N151 (???,???) [000295] ----------- * IL_OFFSET void INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N153 ( 1, 1) [000071] -----+----- * LCL_VAR int V05 tmp4 u:1 NA REG NA DefList: { } N155 ( 1, 2) [000072] -c---+----- * CNS_INT int -0x10000 REG NA $48 Contained DefList: { } N157 ( 3, 4) [000073] -----+----- * ADD int REG NA LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> Interval 28: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] ADD BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N157.t73. ADD } N159 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 NA REG NA $VN.Void BB08 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB08, liveout={V02 V04 V05 V09} ============================== use: {V05} def: {V09} NEW BLOCK BB07 Setting BB06 as the predecessor for determining incoming variable registers of BB07 DefList: { } N163 (???,???) [000294] ----------- * IL_OFFSET void INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N165 ( 1, 1) [000085] -----+----- * LCL_VAR int V05 tmp4 u:1 NA REG NA DefList: { } N167 ( 1, 2) [000086] -c---+----- * CNS_INT int -0x10000 REG NA $48 Contained DefList: { } N169 ( 3, 4) [000087] -----+----- * AND int REG NA LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> Interval 29: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] AND BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N169.t87. AND } N171 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 NA REG NA $VN.Void BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB07, liveout={V02 V04 V05 V09} ============================== use: {V05} def: {V09} NEW BLOCK BB09 Setting BB07 as the predecessor for determining incoming variable registers of BB09 DefList: { } N175 (???,???) [000296] ----------- * IL_OFFSET void INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N177 ( 1, 1) [000078] -----+-N--- * LCL_VAR long V04 tmp3 u:1 NA REG NA $2c1 DefList: { } N179 ( 1, 1) [000076] -----+----- * LCL_VAR int V09 tmp8 u:3 NA (last use) REG NA $340 DefList: { } N181 ( 1, 1) [000080] -----+----- * LCL_VAR int V05 tmp4 u:1 NA REG NA DefList: { } N183 (255, 8) [000081] -A-XG+----- * CMPXCHG int REG NA $11a Interval 30: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] CMPXCHG BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1300.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> CMPXCHG BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> Interval 31: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] CMPXCHG BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N183.t81. CMPXCHG } N185 ( 1, 1) [000082] -----+----- * LCL_VAR int V05 tmp4 u:1 NA (last use) REG NA DefList: { N183.t81. CMPXCHG } N187 (255, 10) [000083] -A-XG+-N-U- * CMP void REG NA BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> DefList: { } N189 (255, 12) [000084] -A-XG+----- * JCC void cond=UNE REG NA Exposed uses: BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> CHECKING LAST USES for BB09, liveout={V02 V04} ============================== use: {V04 V05 V09} def: {} NEW BLOCK BB10 Setting BB04 as the predecessor for determining incoming variable registers of BB10 DefList: { } N193 (???,???) [000297] ----------- * IL_OFFSET void INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N195 ( 1, 1) [000035] -----+----- * LCL_VAR int V05 tmp4 u:1 NA REG NA DefList: { } N197 ( 1, 4) [000114] -c---+----- * CNS_INT int 0x3FFFFFF REG NA $49 Contained DefList: { } N199 ( 3, 6) [000115] -----+----- * AND int REG NA LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> Interval 32: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] AND BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N199.t115. AND } N201 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 NA REG NA $VN.Void BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> DefList: { } N203 (???,???) [000298] ----------- * IL_OFFSET void INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N205 ( 1, 1) [000117] -----+----- * LCL_VAR int V05 tmp4 u:1 NA (last use) REG NA DefList: { } N207 ( 1, 4) [000121] -c---+----- * CNS_INT int 0xC000000 REG NA $4a Contained DefList: { } N209 ( 3, 6) [000122] -----+----- * AND int REG NA LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> Interval 33: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] AND BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N209.t122. AND } N211 ( 1, 4) [000123] -----+----- * CNS_INT int 0x8000000 REG NA $46 Interval 34: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] CNS_INT BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N209.t122. AND; N211.t123. CNS_INT } N213 ( 5, 11) [000124] -----+-N--- * CMP void REG NA BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> DefList: { } N215 ( 7, 13) [000041] -----+----- * JCC void cond=UEQ REG NA CHECKING LAST USES for BB10, liveout={V02 V06} ============================== use: {V05} def: {V06} NEW BLOCK BB12 Setting BB10 as the predecessor for determining incoming variable registers of BB12 DefList: { } N219 (???,???) [000302] ----------- * IL_OFFSET void INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N221 ( 2, 8) [000133] H----+----- * CNS_INT(h) long 0x4208C8 static base addr cell REG NA $142 Interval 35: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] CNS_INT BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N221.t133. CNS_INT } N223 ( 5, 10) [000134] #----+----- * IND long REG NA $380 BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Interval 36: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N223.t134. IND } N225 ( 7, 13) [000136] -c---+----- * LEA(b+16) long REG NA Contained DefList: { N223.t134. IND } N227 ( 8, 12) [000137] ---XG+----- * IND ref REG NA BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Interval 37: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N227.t137. IND } N229 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 NA REG NA $289 BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> DefList: { } N231 (???,???) [000303] ----------- * IL_OFFSET void INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N233 ( 1, 1) [000140] -----+----- * LCL_VAR ref V13 tmp12 u:2 NA REG NA DefList: { } N235 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte REG NA LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> DefList: { } N237 (???,???) [000304] ----------- * IL_OFFSET void INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N239 ( 1, 1) [000139] -----+----- * LCL_VAR ref V13 tmp12 u:2 NA (last use) REG NA DefList: { } N241 ( 1, 2) [000234] -c---+----- * CNS_INT long 16 REG NA $1c3 Contained DefList: { } N243 ( 2, 5) [000235] -----+-N--- * ADD byref REG NA LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> Interval 38: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] ADD BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N243.t235. ADD } N245 ( 3, 2) [000126] -----+----- * LCL_VAR int V06 tmp5 u:1 NA (last use) REG NA DefList: { N243.t235. ADD } N247 ( 4, 4) [000144] -c---+----- * CAST long <- int REG NA Contained DefList: { N243.t235. ADD } N249 ( 1, 2) [000145] -c---+----- * CNS_INT long 5 REG NA $1c4 Contained DefList: { N243.t235. ADD } N251 ( 6, 7) [000146] -----+----- * BFIZ long REG NA LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Interval 39: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] BFIZ BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N243.t235. ADD; N251.t146. BFIZ } N253 ( 9, 13) [000147] -c---+----- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { N243.t235. ADD; N251.t146. BFIZ } N255 ( 11, 14) [000130] ---XG+----- * IND ref REG NA BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Interval 40: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N255.t130. IND } N257 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 NA REG NA BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=350.00> DefList: { } N259 (???,???) [000305] ----------- * IL_OFFSET void INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N261 ( 1, 2) [000047] -c---+----- * CNS_INT long 0 REG NA $1c2 Contained DefList: { } N263 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void DefList: { } N265 (???,???) [000306] ----------- * IL_OFFSET void INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N267 ( 1, 1) [000049] -----+----- * LCL_VAR ref V07 tmp6 u:2 NA REG NA DefList: { } N269 ( 3, 4) [000238] -c---+----- * LEA(b+16) byref REG NA Contained DefList: { } N271 ( 4, 3) [000150] ---XG+----- * IND int REG NA LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=350.00> Interval 41: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N271.t150. IND } N273 ( 1, 1) [000050] -----+----- * LCL_VAR int V02 tmp1 u:2 NA (last use) REG NA DefList: { N271.t150. IND } N275 ( 6, 5) [000151] ---XG+-N--- * CMP void REG NA BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> DefList: { } N277 ( 8, 7) [000152] ---XG+----- * JCC void cond=UEQ REG NA CHECKING LAST USES for BB12, liveout={V07} ============================== use: {V02 V06} def: {V07 V13} NEW BLOCK BB14 Setting BB12 as the predecessor for determining incoming variable registers of BB14 DefList: { } N281 (???,???) [000308] ----------- * IL_OFFSET void INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N283 ( 1, 1) [000153] ----------- * LCL_VAR ref V07 tmp6 u:2 NA REG NA DefList: { } N285 ( 3, 4) [000240] -c--------- * LEA(b+24) byref REG NA Contained DefList: { } N287 ( 4, 3) [000158] n---GO----- * IND int REG NA LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 last wt=350.00> Interval 42: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] IND BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N287.t158. IND } N289 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 NA REG NA BB14 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> DefList: { } N291 ( 3, 2) [000260] ----------- * LCL_VAR int V21 cse0 u:1 NA REG NA DefList: { } N293 ( 1, 2) [000159] -c--------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N295 ( 15, 13) [000161] -A--GO----- * JCMP void REG NA LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> CHECKING LAST USES for BB14, liveout={V07 V21} ============================== use: {V07} def: {V21} NEW BLOCK BB17 Setting BB14 as the predecessor for determining incoming variable registers of BB17 DefList: { } N299 (???,???) [000314] ----------- * IL_OFFSET void INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N301 ( 3, 2) [000262] ----------- * LCL_VAR int V21 cse0 u:1 NA (last use) REG NA DefList: { } N303 ( 1, 2) [000166] -c--------- * CNS_INT int -1 REG NA $41 Contained DefList: { } N305 ( 5, 5) [000167] ----G------ * ADD int REG NA LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> Interval 43: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] ADD BB17 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N305.t167. ADD } N307 ( 1, 1) [000162] ----------- * LCL_VAR ref V07 tmp6 u:2 NA (last use) REG NA DefList: { N305.t167. ADD } N309 ( 3, 4) [000242] -c--------- * LEA(b+24) byref REG NA Contained DefList: { N305.t167. ADD } N311 ( 10, 9) [000169] nA--GO----- * STOREIND int REG NA LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=350.00> BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> CHECKING LAST USES for BB17, liveout={} ============================== use: {V07 V21} def: {} NEW BLOCK BB15 Setting BB14 as the predecessor for determining incoming variable registers of BB15 DefList: { } N315 (???,???) [000309] ----------- * IL_OFFSET void INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N317 ( 1, 1) [000170] ----------- * LCL_VAR ref V07 tmp6 u:2 NA REG NA DefList: { } N319 ( 3, 4) [000246] -c--------- * LEA(b+16) byref REG NA Contained DefList: { } N321 ( 1, 2) [000171] -c--------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N323 ( 6, 6) [000173] nA--GO----- * STOREIND int REG NA LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=350.00> DefList: { } N325 (???,???) [000310] ----------- * IL_OFFSET void INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N327 ( 1, 1) [000249] -----+----- * LCL_VAR ref V07 tmp6 u:2 NA REG NA DefList: { } N329 ( 1, 2) [000250] -c---+----- * CNS_INT long 20 Fseq[_state] REG NA $1c6 Contained DefList: { } N331 ( 3, 4) [000251] -----+----- * ADD byref REG NA LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=350.00> Interval 44: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] ADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N331.t251. ADD } N333 ( 1, 2) [000203] -c---+----- * CNS_INT int -1 REG NA $41 Contained DefList: { N331.t251. ADD } N335 ( 5, 7) [000204] -A-XG+----- * XADD int REG NA Interval 45: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> Interval 46: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 47: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N335.t204. XADD } N337 ( 1, 2) [000205] -c---+----- * CNS_INT int -1 REG NA $41 Contained DefList: { N335.t204. XADD } N339 ( 7, 10) [000206] -A-XG+----- * ADD int REG NA BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Interval 48: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] ADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N339.t206. ADD } N341 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 NA REG NA BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N343 (???,???) [000311] ----------- * IL_OFFSET void INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N345 ( 1, 1) [000209] -----+----- * LCL_VAR int V17 tmp16 u:1 NA (last use) REG NA $13a DefList: { } N347 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 NA REG NA $VN.Void LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> DefList: { } N349 (???,???) [000312] ----------- * IL_OFFSET void INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N351 ( 1, 1) [000216] -----+----- * LCL_VAR int V19 tmp18 u:1 NA REG NA $13a DefList: { } N353 ( 1, 2) [000217] -c---+----- * CNS_INT int 128 REG NA $4d Contained DefList: { } N355 ( 3, 4) [000218] -----+-N-U- * CMP void REG NA LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> DefList: { } N357 ( 5, 6) [000183] -----+----- * JCC void cond=ULT REG NA CHECKING LAST USES for BB15, liveout={V07 V19} ============================== use: {V07} def: {V17 V19} NEW BLOCK BB16 Setting BB15 as the predecessor for determining incoming variable registers of BB16 DefList: { } N361 (???,???) [000313] ----------- * IL_OFFSET void INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N363 ( 1, 1) [000184] -----+----- * LCL_VAR ref V07 tmp6 u:2 NA (last use) REG NA DefList: { } N365 (???,???) [000322] ----------- * PUTARG_REG ref REG x0 BB16 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB16 regmask=[x0] minReg=1 last fixed wt=350.00> Interval 49: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] BB16 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB16 regmask=[x0] minReg=1 fixed wt=200.00> DefList: { N365.t322. PUTARG_REG } N367 ( 3, 2) [000185] -----+----- * LCL_VAR int V19 tmp18 u:1 NA (last use) REG NA $13a DefList: { N365.t322. PUTARG_REG } N369 (???,???) [000323] ----------- * PUTARG_REG int REG x1 Last use of V19 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB16 regmask=[x1] minReg=1 wt=50.00> LCL_VAR BB16 regmask=[x1] minReg=1 last fixed wt=150.00> Interval 50: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] BB16 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB16 regmask=[x1] minReg=1 fixed wt=200.00> DefList: { N365.t322. PUTARG_REG; N369.t323. PUTARG_REG } N371 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this REG NA $VN.Void BB16 regmask=[x0] minReg=1 wt=50.00> BB16 regmask=[x0] minReg=1 last fixed wt=50.00> BB16 regmask=[x1] minReg=1 wt=50.00> BB16 regmask=[x1] minReg=1 last fixed wt=50.00> CHECKING LAST USES for BB16, liveout={} ============================== use: {V07 V19} def: {} NEW BLOCK BB13 Setting BB12 as the predecessor for determining incoming variable registers of BB13 DefList: { } N375 (???,???) [000307] ----------- * IL_OFFSET void INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N377 ( 14, 2) [000155] --CXG+----- * CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() REG NA $VN.Void CHECKING LAST USES for BB13, liveout={} ============================== use: {} def: {} NEW BLOCK BB11 Setting BB10 as the predecessor for determining incoming variable registers of BB11 DefList: { } N381 (???,???) [000299] ----------- * IL_OFFSET void INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N383 ( 2, 8) [000052] H----+----- * CNS_INT(h) long 0x420818 class REG NA $147 Interval 51: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] CNS_INT BB11 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> DefList: { N383.t52. CNS_INT } N385 (???,???) [000319] ----------- * PUTARG_REG long REG x0 BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> Interval 52: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> DefList: { N385.t319. PUTARG_REG } N387 ( 16, 11) [000053] --C--+----- * CALL help ref CORINFO_HELP_NEWSFAST REG NA $298 BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> Interval 53: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] BB11 regmask=[x0] minReg=1 wt=0.00> CALL BB11 regmask=[x0] minReg=1 fixed wt=0.00> DefList: { N387.t53. CALL } N389 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 NA REG NA $VN.Void BB11 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> Assigning related to STORE_LCL_VAR BB11 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> DefList: { } N391 (???,???) [000300] ----------- * IL_OFFSET void INL01 @ ??? <- INLRT @ 0x000[E-] REG NA DefList: { } N393 ( 3, 2) [000055] -----+----- * LCL_VAR ref V08 tmp7 u:2 NA REG NA $298 DefList: { } N395 (???,???) [000320] ----------- * PUTARG_REG ref REG x0 BB11 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 last fixed wt=0.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 54: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> Assigning related to DefList: { N395.t320. PUTARG_REG } N397 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this REG NA $VN.Void BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> DefList: { } N399 (???,???) [000301] ----------- * IL_OFFSET void INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] REG NA DefList: { } N401 ( 3, 2) [000057] -----+----- * LCL_VAR ref V08 tmp7 u:2 NA (last use) REG NA $298 DefList: { } N403 (???,???) [000321] ----------- * PUTARG_REG ref REG x0 BB11 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 last fixed wt=0.00> Interval 55: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> DefList: { N403.t321. PUTARG_REG } N405 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW REG NA $29a BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> CHECKING LAST USES for BB11, liveout={} ============================== use: {} def: {V08} NEW BLOCK BB18 Setting BB09 as the predecessor for determining incoming variable registers of BB18 DefList: { } N409 (???,???) [000315] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA DefList: { } N411 ( 1, 2) [000092] -c---+----- * CNS_INT byref 0 REG NA $VN.Null Contained DefList: { } N413 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void DefList: { } N415 (???,???) [000316] ----------- * IL_OFFSET void INLRT @ 0x006[E-] REG NA DefList: { } N417 ( 0, 0) [000002] -----+----- * RETURN void REG NA $VN.Void CHECKING LAST USES for BB18, liveout={} ============================== use: {} def: {} NEW BLOCK BB02 Setting BB01 as the predecessor for determining incoming variable registers of BB02 DefList: { } N421 (???,???) [000282] ----------- * IL_OFFSET void INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA DefList: { } N423 ( 2, 8) [000222] H----+----- * CNS_INT(h) ref '"obj"' REG NA $500 Interval 56: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N423.t222. CNS_INT } N425 (???,???) [000317] ----------- * PUTARG_REG ref REG x0 BB02 regmask=[x0] minReg=1 wt=50.00> BB02 regmask=[x0] minReg=1 last fixed wt=50.00> Interval 57: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] BB02 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB02 regmask=[x0] minReg=1 fixed wt=200.00> DefList: { N425.t317. PUTARG_REG } N427 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) REG NA $VN.Void BB02 regmask=[x0] minReg=1 wt=50.00> BB02 regmask=[x0] minReg=1 last fixed wt=50.00> CHECKING LAST USES for BB02, liveout={} ============================== use: {} def: {} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) ref RefPositions {#0@0 #2@9 #48@89} physReg:x0 Preferences=[x19-x28] Aversions=[x0-xip1 lr] Interval 1: (V02) int RefPositions {#40@66 #41@75 #43@81 #47@84 #64@123 #120@275} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 2: (V04) long RefPositions {#55@104 #57@111 #81@183 #88@191} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 3: (V05) int RefPositions {#60@114 #61@119 #66@135 #68@145 #70@157 #75@169 #83@183 #87@187 #90@199 #94@209} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 4: (V06) int RefPositions {#93@202 #110@251} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 5: (V07) ref RefPositions {#116@258 #117@271 #122@287 #130@311 #133@323 #134@331 #151@365} physReg:NA Preferences=[x0] Aversions=[] Interval 6: (V08) ref RefPositions {#177@390 #179@395 #186@403} physReg:NA Preferences=[x19-x28] Aversions=[x0-xip1 lr] Interval 7: (V09) int RefPositions {#73@160 #78@172 #82@183} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 8: (V13) ref RefPositions {#106@230 #107@235 #108@243} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 9: (V17) int RefPositions {#145@342 #146@347} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 10: (V19) int (field) RefPositions {#147@348 #148@355 #155@369} physReg:NA Preferences=[x1] Aversions=[x0] Interval 11: (V20) long RefPositions {#51@96 #52@101} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 12: (V21) int RefPositions {#125@290 #126@295 #128@305} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 13: (V22) ref RefPositions {#17@26 #18@31 #20@39 #21@40 #35@54 #37@63} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 14: (V23) long RefPositions {#13@20 #14@23 #24@47} physReg:NA Preferences=[x0] Aversions=[] Interval 15: long (constant) RefPositions {#4@16 #8@17} physReg:NA Preferences=[x2] Aversions=[] Interval 16: long RefPositions {#11@18 #12@19} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 17: ref RefPositions {#15@24 #16@25} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 18: long RefPositions {#26@48 #29@51} physReg:NA Preferences=[x0] Aversions=[] Interval 19: long (constant) RefPositions {#27@50 #30@51} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 20: ref RefPositions {#33@52 #34@53} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 21: int RefPositions {#38@64 #39@65} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 22: int RefPositions {#42@76 #44@81} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 23: int RefPositions {#45@82 #46@83} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 24: byref RefPositions {#49@94 #50@95} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 25: long RefPositions {#53@102 #54@103} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 26: int RefPositions {#58@112 #59@113} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 27: int RefPositions {#62@120 #63@123} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 28: int RefPositions {#71@158 #72@159} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 29: int RefPositions {#76@170 #77@171} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 30: int (INTERNAL) RefPositions {#80@183 #84@183} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 31: int (interfering uses) RefPositions {#85@184 #86@187} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 32: int RefPositions {#91@200 #92@201} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 33: int RefPositions {#95@210 #97@213} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 34: int (constant) RefPositions {#96@212 #98@213} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 35: long (constant) RefPositions {#100@222 #101@223} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 36: long RefPositions {#102@224 #103@227} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 37: ref RefPositions {#104@228 #105@229} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 38: byref RefPositions {#109@244 #112@255} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 39: long RefPositions {#111@252 #113@255} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 40: ref RefPositions {#114@256 #115@257} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 41: int RefPositions {#118@272 #119@275} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 42: int RefPositions {#123@288 #124@289} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 43: int RefPositions {#129@306 #131@311} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 44: byref RefPositions {#135@332 #138@335} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 45: int (INTERNAL) RefPositions {#136@335 #139@335} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 46: int (INTERNAL) RefPositions {#137@335 #140@335} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 47: int (interfering uses) RefPositions {#141@336 #142@339} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 48: int RefPositions {#143@340 #144@341} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 49: ref RefPositions {#153@366 #159@371} physReg:NA Preferences=[x0] Aversions=[] Interval 50: int RefPositions {#157@370 #161@371} physReg:NA Preferences=[x1] Aversions=[] Interval 51: long (constant) RefPositions {#166@384 #168@385} physReg:NA Preferences=[x0] Aversions=[] Interval 52: long RefPositions {#170@386 #172@387} physReg:NA Preferences=[x0] Aversions=[] Interval 53: ref RefPositions {#175@388 #176@389} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 54: ref (specialPutArg) RefPositions {#181@396 #183@397} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 55: ref RefPositions {#188@404 #190@405} physReg:NA Preferences=[x0] Aversions=[] Interval 56: ref (constant) RefPositions {#194@424 #196@425} physReg:NA Preferences=[x0] Aversions=[] Interval 57: ref RefPositions {#198@426 #200@427} physReg:NA Preferences=[x0] Aversions=[] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> CNS_INT BB03 regmask=[x2] minReg=1 wt=400.00> BB03 regmask=[x0] minReg=1 wt=100.00> BB03 regmask=[x1] minReg=1 wt=100.00> BB03 regmask=[x2] minReg=1 wt=100.00> BB03 regmask=[x2] minReg=1 last fixed wt=100.00> BB03 regmask=[x0] minReg=1 wt=100.00> CALL BB03 regmask=[x0] minReg=1 fixed wt=400.00> BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> IND BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> STORE_LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB22 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB22 regmask=[x0] minReg=1 last fixed wt=400.00> BB22 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB22 regmask=[x0] minReg=1 fixed wt=0.00> CNS_INT BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> BB22 regmask=[x0] minReg=1 wt=0.00> BB22 regmask=[x0] minReg=1 last fixed wt=0.00> BB22 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> BB22 regmask=[x0] minReg=1 wt=0.00> CALL BB22 regmask=[x0] minReg=1 fixed wt=0.00> BB22 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> STORE_LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> IND BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> ADD BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> OR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> ADD BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1300.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=1300.00> IND BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=3700.00> CAST BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> ADD BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB08 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> AND BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> CMPXCHG BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 delay wt=1300.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 delay wt=3700.00> CMPXCHG BB09 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=1600.00> CMPXCHG BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> BB09 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> AND BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> AND BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> CNS_INT BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> CNS_INT BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> ADD BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> BFIZ BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> IND BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB14 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> ADD BB17 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=350.00> BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> ADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB15 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=50.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=200.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=200.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> ADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> BB16 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB16 regmask=[x0] minReg=1 last fixed wt=350.00> BB16 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB16 regmask=[x0] minReg=1 fixed wt=200.00> BB16 regmask=[x1] minReg=1 wt=50.00> LCL_VAR BB16 regmask=[x1] minReg=1 last fixed wt=150.00> BB16 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB16 regmask=[x1] minReg=1 fixed wt=200.00> BB16 regmask=[x0] minReg=1 wt=50.00> BB16 regmask=[x0] minReg=1 last fixed wt=50.00> BB16 regmask=[x1] minReg=1 wt=50.00> BB16 regmask=[x1] minReg=1 last fixed wt=50.00> CNS_INT BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> CALL BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> STORE_LCL_VAR BB11 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 last fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> CNS_INT BB02 regmask=[x0] minReg=1 wt=200.00> BB02 regmask=[x0] minReg=1 wt=50.00> BB02 regmask=[x0] minReg=1 last fixed wt=50.00> BB02 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB02 regmask=[x0] minReg=1 fixed wt=200.00> BB02 regmask=[x0] minReg=1 wt=50.00> BB02 regmask=[x0] minReg=1 last fixed wt=50.00> ------------ REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval) ------------ ----------------- STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=3700.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 delay wt=3700.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> ----------------- STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1300.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=1300.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 delay wt=1300.00> BB09 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> ----------------- STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> ----------------- STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> STORE_LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> STORE_LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=800.00> ----------------- BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> ----------------- STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB22 regmask=[x0] minReg=1 last fixed wt=400.00> ----------------- STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> ----------------- STORE_LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=350.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB16 regmask=[x0] minReg=1 last fixed wt=350.00> ----------------- STORE_LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> ----------------- STORE_LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ----------------- STORE_LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB16 regmask=[x1] minReg=1 last fixed wt=150.00> ----------------- STORE_LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> ----------------- STORE_LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> ----------------- STORE_LCL_VAR BB11 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 fixed wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 last fixed wt=0.00> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V00 BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ===== N003. IL_OFFSET INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N005. V00(L0) N007. CNS_INT null N009. JCMP Use:(#2) BB03 [0015] [???..???) -> BB23(1),BB22(0) (cond), preds={BB01} succs={BB22,BB23} ===== N013. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N015. CNS_INT(h) 0x420480 UNKNOWN Def:(#4) N017. CALL ind _tls_get_addr Use:(#8) Fixed:x2(#7) * Kill: [x0-xip1 lr] Def:(#11) x0 Pref: N019. V23(L14) Use:(#12) * Def:(#13) N021. V23(L14) N023. IND Use:(#14) Def:(#15) Pref: N025. V22(L13) Use:(#16) * Def:(#17) Pref: N027. V22(L13) N029. CNS_INT 0 N031. JCMP Use:(#18) BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} ===== N035. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N037. V22(L13) N039. V22(L13) Use:(#20) * Def:(#21) Pref: BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} ===== N043. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N045. V23(L14) N047. PUTARG_REG Use:(#24) Fixed:x0(#23) * Def:(#26) x0 N049. CNS_INT(h) 0x420488 tls Def:(#27) N051. CALL ind Use:(#29) Fixed:x0(#28) * Use:(#30) * Kill: [x0-xip1 lr] Def:(#33) x0 Pref: N053. V22(L13) Use:(#34) * Def:(#35) Pref: BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} ===== N057. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N059. V22(L13) N061. LEA(b+40) N063. IND Use:(#37) * Def:(#38) Pref: N065. V02(L1) Use:(#39) * Def:(#40) N067. IL_OFFSET INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] N069. V02(L1) N071. V02(L1) N073. CNS_INT -1 N075. ADD Use:(#41) Def:(#42) N077. CNS_INT 31 N079. RSH N081. OR Use:(#43) * Use:(#44) * Def:(#45) Pref: N083. V02(L1) Use:(#46) * Def:(#47) N085. IL_OFFSET INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] N087. V00(L0) N089. V03 MEM Use:(#48) * N091. IL_OFFSET INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] N093. V03 MEM Def:(#49) Pref: N095. V20(L11) Use:(#50) * Def:(#51) N097. V20(L11) N099. CNS_INT -4 N101. ADD Use:(#52) * Def:(#53) Pref: N103. V04(L2) Use:(#54) * Def:(#55) BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} ===== N107. IL_OFFSET INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] N109. V04(L2) N111. IND Use:(#57) Def:(#58) Pref: N113. V05(L3) Use:(#59) * Def:(#60) N115. IL_OFFSET INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] N117. V05(L3) N119. CAST Use:(#61) Def:(#62) N121. V02(L1) N123. CMP Use:(#63) * Use:(#64) N125. JCC cond=UNE BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ===== N129. IL_OFFSET INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] N131. V05(L3) N133. CNS_INT 0x8000000 N135. JTEST Use:(#66) BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ===== N139. IL_OFFSET INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] N141. V05(L3) N143. CNS_INT 0x3F0000 N145. TEST Use:(#68) N147. JCC cond=UNE BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ===== N151. IL_OFFSET INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] N153. V05(L3) N155. CNS_INT -0x10000 N157. ADD Use:(#70) Def:(#71) Pref: N159. V09(L7) Use:(#72) * Def:(#73) BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ===== N163. IL_OFFSET INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] N165. V05(L3) N167. CNS_INT -0x10000 N169. AND Use:(#75) Def:(#76) Pref: N171. V09(L7) Use:(#77) * Def:(#78) BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ===== N175. IL_OFFSET INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] N177. V04(L2) N179. V09(L7) N181. V05(L3) N183. CMPXCHG Def:(#80) Use:(#81) Use:(#82) * Use:(#83) Use:(#84) * Def:(#85) N185. V05(L3) N187. CMP Use:(#86) * Use:(#87) * N189. JCC cond=UNE Exposed use of V04 at #88 BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ===== N193. IL_OFFSET INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N195. V05(L3) N197. CNS_INT 0x3FFFFFF N199. AND Use:(#90) Def:(#91) Pref: N201. V06(L4) Use:(#92) * Def:(#93) N203. IL_OFFSET INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N205. V05(L3) N207. CNS_INT 0xC000000 N209. AND Use:(#94) * Def:(#95) N211. CNS_INT 0x8000000 Def:(#96) N213. CMP Use:(#97) * Use:(#98) * N215. JCC cond=UEQ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ===== N219. IL_OFFSET INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N221. CNS_INT(h) 0x4208C8 static base addr cell Def:(#100) N223. IND Use:(#101) * Def:(#102) N225. LEA(b+16) N227. IND Use:(#103) * Def:(#104) Pref: N229. V13(L8) Use:(#105) * Def:(#106) N231. IL_OFFSET INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N233. V13(L8) N235. NULLCHECK Use:(#107) N237. IL_OFFSET INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N239. V13(L8) N241. CNS_INT 16 N243. ADD Use:(#108) * Def:(#109) N245. V06(L4) N247. CAST N249. CNS_INT 5 N251. BFIZ Use:(#110) * Def:(#111) N253. LEA(b+(i*1)+0) N255. IND Use:(#112) * Use:(#113) * Def:(#114) Pref: N257. V07(L5) Use:(#115) * Def:(#116) N259. IL_OFFSET INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] N261. CNS_INT 0 N263. V03 MEM N265. IL_OFFSET INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N267. V07(L5) N269. LEA(b+16) N271. IND Use:(#117) Def:(#118) N273. V02(L1) N275. CMP Use:(#119) * Use:(#120) * N277. JCC cond=UEQ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ===== N281. IL_OFFSET INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N283. V07(L5) N285. LEA(b+24) N287. IND Use:(#122) Def:(#123) Pref: N289. V21(L12) Use:(#124) * Def:(#125) N291. V21(L12) N293. CNS_INT 0 N295. JCMP Use:(#126) BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} ===== N299. IL_OFFSET INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N301. V21(L12) N303. CNS_INT -1 N305. ADD Use:(#128) * Def:(#129) N307. V07(L5) N309. LEA(b+24) N311. STOREIND Use:(#130) * Use:(#131) * BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} ===== N315. IL_OFFSET INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N317. V07(L5) N319. LEA(b+16) N321. CNS_INT 0 N323. STOREIND Use:(#133) N325. IL_OFFSET INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N327. V07(L5) N329. CNS_INT 20 Fseq[_state] N331. ADD Use:(#134) Def:(#135) N333. CNS_INT -1 N335. XADD Def:(#136) Def:(#137) Use:(#138) * Use:(#139) * Use:(#140) * Def:(#141) N337. CNS_INT -1 N339. ADD Use:(#142) * Def:(#143) Pref: N341. V17(L9) Use:(#144) * Def:(#145) Pref: N343. IL_OFFSET INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N345. V17(L9) N347. V19(L10) Use:(#146) * Def:(#147) N349. IL_OFFSET INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N351. V19(L10) N353. CNS_INT 128 N355. CMP Use:(#148) N357. JCC cond=ULT BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} ===== N361. IL_OFFSET INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N363. V07(L5) N365. PUTARG_REG Use:(#151) Fixed:x0(#150) * Def:(#153) x0 N367. V19(L10) N369. PUTARG_REG Use:(#155) Fixed:x1(#154) * Def:(#157) x1 N371. CALL Use:(#159) Fixed:x0(#158) * Use:(#161) Fixed:x1(#160) * Kill: [x0-xip1 lr] BB13 [0025] [000..001) (throw), preds={BB12} succs={} ===== N375. IL_OFFSET INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N377. CALL Kill: [x0-xip1 lr] BB11 [0010] [000..001) (throw), preds={BB10} succs={} ===== N381. IL_OFFSET INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] N383. CNS_INT(h) 0x420818 class Def:(#166) N385. PUTARG_REG Use:(#168) Fixed:x0(#167) * Def:(#170) x0 N387. CALL help Use:(#172) Fixed:x0(#171) * Kill: [x0-xip1 lr] Def:(#175) x0 Pref: N389. V08(L6) Use:(#176) * Def:(#177) N391. IL_OFFSET INL01 @ ??? <- INLRT @ 0x000[E-] N393. V08(L6) N395. PUTARG_REG Use:(#179) Fixed:x0(#178) Def:(#181) x0 Pref: N397. CALL Use:(#183) Fixed:x0(#182) * Kill: [x0-xip1 lr] N399. IL_OFFSET INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] N401. V08(L6) N403. PUTARG_REG Use:(#186) Fixed:x0(#185) * Def:(#188) x0 N405. CALL help Use:(#190) Fixed:x0(#189) * Kill: [x0-xip1 lr] BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} ===== N409. IL_OFFSET INLRT @ 0x000[E-] N411. CNS_INT 0 N413. V03 MEM N415. IL_OFFSET INLRT @ 0x006[E-] N417. RETURN BB02 [0014] [000..001) (throw), preds={BB01} succs={} ===== N421. IL_OFFSET INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N423. CNS_INT(h) '"obj"' Def:(#194) N425. PUTARG_REG Use:(#196) Fixed:x0(#195) * Def:(#198) x0 N427. CALL Use:(#200) Fixed:x0(#199) * Kill: [x0-xip1 lr] Linear scan intervals after buildIntervals: Interval 0: (V00) ref RefPositions {#0@0 #2@9 #48@89} physReg:x0 Preferences=[x19-x28] Aversions=[x0-xip1 lr] Interval 1: (V02) int RefPositions {#40@66 #41@75 #43@81 #47@84 #64@123 #120@275} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 2: (V04) long RefPositions {#55@104 #57@111 #81@183 #88@191} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 3: (V05) int RefPositions {#60@114 #61@119 #66@135 #68@145 #70@157 #75@169 #83@183 #87@187 #90@199 #94@209} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 4: (V06) int RefPositions {#93@202 #110@251} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 5: (V07) ref RefPositions {#116@258 #117@271 #122@287 #130@311 #133@323 #134@331 #151@365} physReg:NA Preferences=[x0] Aversions=[] Interval 6: (V08) ref RefPositions {#177@390 #179@395 #186@403} physReg:NA Preferences=[x19-x28] Aversions=[x0-xip1 lr] Interval 7: (V09) int RefPositions {#73@160 #78@172 #82@183} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 8: (V13) ref RefPositions {#106@230 #107@235 #108@243} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 9: (V17) int RefPositions {#145@342 #146@347} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 10: (V19) int (field) RefPositions {#147@348 #148@355 #155@369} physReg:NA Preferences=[x1] Aversions=[x0] Interval 11: (V20) long RefPositions {#51@96 #52@101} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 12: (V21) int RefPositions {#125@290 #126@295 #128@305} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 13: (V22) ref RefPositions {#17@26 #18@31 #20@39 #21@40 #35@54 #37@63} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 14: (V23) long RefPositions {#13@20 #14@23 #24@47} physReg:NA Preferences=[x0] Aversions=[] Interval 15: long (constant) RefPositions {#4@16 #8@17} physReg:NA Preferences=[x2] Aversions=[] Interval 16: long RefPositions {#11@18 #12@19} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 17: ref RefPositions {#15@24 #16@25} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 18: long RefPositions {#26@48 #29@51} physReg:NA Preferences=[x0] Aversions=[] Interval 19: long (constant) RefPositions {#27@50 #30@51} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 20: ref RefPositions {#33@52 #34@53} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 21: int RefPositions {#38@64 #39@65} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 22: int RefPositions {#42@76 #44@81} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 23: int RefPositions {#45@82 #46@83} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 24: byref RefPositions {#49@94 #50@95} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 25: long RefPositions {#53@102 #54@103} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 26: int RefPositions {#58@112 #59@113} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 27: int RefPositions {#62@120 #63@123} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 28: int RefPositions {#71@158 #72@159} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 29: int RefPositions {#76@170 #77@171} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 30: int (INTERNAL) RefPositions {#80@183 #84@183} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 31: int (interfering uses) RefPositions {#85@184 #86@187} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 32: int RefPositions {#91@200 #92@201} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 33: int RefPositions {#95@210 #97@213} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 34: int (constant) RefPositions {#96@212 #98@213} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 35: long (constant) RefPositions {#100@222 #101@223} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 36: long RefPositions {#102@224 #103@227} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 37: ref RefPositions {#104@228 #105@229} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 38: byref RefPositions {#109@244 #112@255} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 39: long RefPositions {#111@252 #113@255} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 40: ref RefPositions {#114@256 #115@257} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 41: int RefPositions {#118@272 #119@275} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 42: int RefPositions {#123@288 #124@289} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 43: int RefPositions {#129@306 #131@311} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 44: byref RefPositions {#135@332 #138@335} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 45: int (INTERNAL) RefPositions {#136@335 #139@335} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 46: int (INTERNAL) RefPositions {#137@335 #140@335} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 47: int (interfering uses) RefPositions {#141@336 #142@339} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 48: int RefPositions {#143@340 #144@341} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 49: ref RefPositions {#153@366 #159@371} physReg:NA Preferences=[x0] Aversions=[] Interval 50: int RefPositions {#157@370 #161@371} physReg:NA Preferences=[x1] Aversions=[] Interval 51: long (constant) RefPositions {#166@384 #168@385} physReg:NA Preferences=[x0] Aversions=[] Interval 52: long RefPositions {#170@386 #172@387} physReg:NA Preferences=[x0] Aversions=[] Interval 53: ref RefPositions {#175@388 #176@389} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 54: ref (specialPutArg) RefPositions {#181@396 #183@397} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 55: ref RefPositions {#188@404 #190@405} physReg:NA Preferences=[x0] Aversions=[] Interval 56: ref (constant) RefPositions {#194@424 #196@425} physReg:NA Preferences=[x0] Aversions=[] Interval 57: ref RefPositions {#198@426 #200@427} physReg:NA Preferences=[x0] Aversions=[] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) ref RefPositions {#0@0 #2@9 #48@89} physReg:x0 Preferences=[x19-x28] Aversions=[x0-xip1 lr] Interval 1: (V02) int RefPositions {#40@66 #41@75 #43@81 #47@84 #64@123 #120@275} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 2: (V04) long RefPositions {#55@104 #57@111 #81@183 #88@191} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 3: (V05) int RefPositions {#60@114 #61@119 #66@135 #68@145 #70@157 #75@169 #83@183 #87@187 #90@199 #94@209} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 4: (V06) int RefPositions {#93@202 #110@251} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 5: (V07) ref RefPositions {#116@258 #117@271 #122@287 #130@311 #133@323 #134@331 #151@365} physReg:NA Preferences=[x0] Aversions=[] Interval 6: (V08) ref RefPositions {#177@390 #179@395 #186@403} physReg:NA Preferences=[x19-x28] Aversions=[x0-xip1 lr] Interval 7: (V09) int RefPositions {#73@160 #78@172 #82@183} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 8: (V13) ref RefPositions {#106@230 #107@235 #108@243} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 9: (V17) int RefPositions {#145@342 #146@347} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 10: (V19) int (field) RefPositions {#147@348 #148@355 #155@369} physReg:NA Preferences=[x1] Aversions=[x0] Interval 11: (V20) long RefPositions {#51@96 #52@101} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 12: (V21) int RefPositions {#125@290 #126@295 #128@305} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 13: (V22) ref RefPositions {#17@26 #18@31 #20@39 #21@40 #35@54 #37@63} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 14: (V23) long RefPositions {#13@20 #14@23 #24@47} physReg:NA Preferences=[x0] Aversions=[] Interval 15: long (constant) RefPositions {#4@16 #8@17} physReg:NA Preferences=[x2] Aversions=[] Interval 16: long RefPositions {#11@18 #12@19} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 17: ref RefPositions {#15@24 #16@25} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 18: long RefPositions {#26@48 #29@51} physReg:NA Preferences=[x0] Aversions=[] Interval 19: long (constant) RefPositions {#27@50 #30@51} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 20: ref RefPositions {#33@52 #34@53} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 21: int RefPositions {#38@64 #39@65} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 22: int RefPositions {#42@76 #44@81} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 23: int RefPositions {#45@82 #46@83} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 24: byref RefPositions {#49@94 #50@95} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 25: long RefPositions {#53@102 #54@103} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 26: int RefPositions {#58@112 #59@113} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 27: int RefPositions {#62@120 #63@123} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 28: int RefPositions {#71@158 #72@159} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 29: int RefPositions {#76@170 #77@171} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 30: int (INTERNAL) RefPositions {#80@183 #84@183} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 31: int (interfering uses) RefPositions {#85@184 #86@187} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 32: int RefPositions {#91@200 #92@201} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 33: int RefPositions {#95@210 #97@213} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 34: int (constant) RefPositions {#96@212 #98@213} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 35: long (constant) RefPositions {#100@222 #101@223} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 36: long RefPositions {#102@224 #103@227} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 37: ref RefPositions {#104@228 #105@229} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 38: byref RefPositions {#109@244 #112@255} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 39: long RefPositions {#111@252 #113@255} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 40: ref RefPositions {#114@256 #115@257} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 41: int RefPositions {#118@272 #119@275} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 42: int RefPositions {#123@288 #124@289} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 43: int RefPositions {#129@306 #131@311} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 44: byref RefPositions {#135@332 #138@335} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 45: int (INTERNAL) RefPositions {#136@335 #139@335} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 46: int (INTERNAL) RefPositions {#137@335 #140@335} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 47: int (interfering uses) RefPositions {#141@336 #142@339} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] Interval 48: int RefPositions {#143@340 #144@341} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval Interval 49: ref RefPositions {#153@366 #159@371} physReg:NA Preferences=[x0] Aversions=[] Interval 50: int RefPositions {#157@370 #161@371} physReg:NA Preferences=[x1] Aversions=[] Interval 51: long (constant) RefPositions {#166@384 #168@385} physReg:NA Preferences=[x0] Aversions=[] Interval 52: long RefPositions {#170@386 #172@387} physReg:NA Preferences=[x0] Aversions=[] Interval 53: ref RefPositions {#175@388 #176@389} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 54: ref (specialPutArg) RefPositions {#181@396 #183@397} physReg:NA Preferences=[x0] Aversions=[] RelatedInterval Interval 55: ref RefPositions {#188@404 #190@405} physReg:NA Preferences=[x0] Aversions=[] Interval 56: ref (constant) RefPositions {#194@424 #196@425} physReg:NA Preferences=[x0] Aversions=[] Interval 57: ref RefPositions {#198@426 #200@427} physReg:NA Preferences=[x0] Aversions=[] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> CNS_INT BB03 regmask=[x2] minReg=1 wt=400.00> BB03 regmask=[x0] minReg=1 wt=100.00> BB03 regmask=[x1] minReg=1 wt=100.00> BB03 regmask=[x2] minReg=1 wt=100.00> BB03 regmask=[x2] minReg=1 last fixed wt=100.00> BB03 regmask=[x0] minReg=1 wt=100.00> CALL BB03 regmask=[x0] minReg=1 fixed wt=400.00> BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> IND BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> STORE_LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB22 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB22 regmask=[x0] minReg=1 last fixed wt=400.00> BB22 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB22 regmask=[x0] minReg=1 fixed wt=0.00> CNS_INT BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> BB22 regmask=[x0] minReg=1 wt=0.00> BB22 regmask=[x0] minReg=1 last fixed wt=0.00> BB22 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> BB22 regmask=[x0] minReg=1 wt=0.00> CALL BB22 regmask=[x0] minReg=1 fixed wt=0.00> BB22 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> STORE_LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> IND BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> ADD BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> OR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> ADD BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1300.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=1300.00> IND BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=3700.00> CAST BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> ADD BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB08 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> AND BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> CMPXCHG BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 delay wt=1300.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 delay wt=3700.00> CMPXCHG BB09 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=1600.00> CMPXCHG BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> BB09 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> AND BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> AND BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> CNS_INT BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> CNS_INT BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> ADD BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> BFIZ BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> IND BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> IND BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB14 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> ADD BB17 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=350.00> BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> ADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB15 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=50.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=200.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=200.00> XADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> ADD BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> BB16 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB16 regmask=[x0] minReg=1 last fixed wt=350.00> BB16 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB16 regmask=[x0] minReg=1 fixed wt=200.00> BB16 regmask=[x1] minReg=1 wt=50.00> LCL_VAR BB16 regmask=[x1] minReg=1 last fixed wt=150.00> BB16 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB16 regmask=[x1] minReg=1 fixed wt=200.00> BB16 regmask=[x0] minReg=1 wt=50.00> BB16 regmask=[x0] minReg=1 last fixed wt=50.00> BB16 regmask=[x1] minReg=1 wt=50.00> BB16 regmask=[x1] minReg=1 last fixed wt=50.00> CNS_INT BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> CALL BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> STORE_LCL_VAR BB11 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 last fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> CNS_INT BB02 regmask=[x0] minReg=1 wt=200.00> BB02 regmask=[x0] minReg=1 wt=50.00> BB02 regmask=[x0] minReg=1 last fixed wt=50.00> BB02 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB02 regmask=[x0] minReg=1 fixed wt=200.00> BB02 regmask=[x0] minReg=1 wt=50.00> BB02 regmask=[x0] minReg=1 last fixed wt=50.00> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 (Interval 0) BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> --- V01 --- V02 (Interval 1) STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> --- V03 --- V04 (Interval 2) STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=1300.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=1300.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 delay wt=1300.00> BB09 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V05 (Interval 3) STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=3700.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 delay wt=3700.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=3700.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3700.00> --- V06 (Interval 4) STORE_LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> --- V07 (Interval 5) STORE_LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=350.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=350.00> LCL_VAR BB16 regmask=[x0] minReg=1 last fixed wt=350.00> --- V08 (Interval 6) STORE_LCL_VAR BB11 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 fixed wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 last fixed wt=0.00> --- V09 (Interval 7) STORE_LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=800.00> --- V10 --- V11 --- V12 --- V13 (Interval 8) STORE_LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> --- V14 --- V15 --- V16 --- V17 (Interval 9) STORE_LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> --- V18 --- V19 (Interval 10) STORE_LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB16 regmask=[x1] minReg=1 last fixed wt=150.00> --- V20 (Interval 11) STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> --- V21 (Interval 12) STORE_LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> --- V22 (Interval 13) STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> STORE_LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> STORE_LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V23 (Interval 14) STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB22 regmask=[x0] minReg=1 last fixed wt=400.00> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use, Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register, (b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc, '(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details. The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive. Columns are only printed up to the last modified register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ |V00a| | | | | | | | | | 0.#0 V00 Parm ORDER(A) x19 | | | | | | | | |V00a| | 1.#1 BB1 PredBB0 | | | | | | | | |V00a| | [000097] 9.#2 V00 Use Keep x19 | | | | | | | | |V00a| | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 11.#3 BB3 PredBB1 | | | | | | | | |V00a| | [000265] 16.#4 C15 Def Alloc x2 | | |C15a| | | | | |V00a| | [000266] 17.#5 x0 Fixd Keep x0 | | |C15a| | | | | |V00a| | 17.#6 x1 Fixd Keep x1 | | |C15a| | | | | |V00a| | 17.#7 x2 Fixd Keep x2 | | |C15a| | | | | |V00a| | 17.#8 C15 Use * Keep x2 | | |C15a| | | | | |V00a| | 18.#9 Kill None [x0-xip1 lr] | | | | | | | | |V00a| | 18.#10 x0 Fixd Keep x0 | | | | | | | | |V00a| | 18.#11 I16 Def Alloc x0 |I16a| | | | | | | |V00a| | [000267] 19.#12 I16 Use * Keep x0 |I16a| | | | | | | |V00a| | 20.#13 V23 Def COVRS(A) x0 |V23a| | | | | | | |V00a| | [000269] 23.#14 V23 Use Keep x0 |V23a| | | | | | | |V00a| | 24.#15 I17 Def ORDER(A) x20 |V23a| | | | | | | |V00a|I17a| [000270] 25.#16 I17 Use * Keep x20 |V23a| | | | | | | |V00a|I17a| 26.#17 V22 Def COVRS(A) x20 |V23a| | | | | | | |V00a|V22a| [000274] 31.#18 V22 Use Keep x20 |V23a| | | | | | | |V00a|V22a| --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 33.#19 BB23 PredBB3 |V23i| | | | | | | |V00a|V22a| [000280] 39.#20 V22 Use * Keep x20 |V23i| | | | | | | |V00a|V22i| 40.#21 V22 Def Keep x20 |V23i| | | | | | | |V00a|V22a| --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 41.#22 BB22 PredBB3 |V23a| | | | | | | |V00a|V22i| [000318] 47.#23 x0 Fixd Keep x0 |V23a| | | | | | | |V00a|V22i| 47.#24 V23 Use * Keep x0 |V23a| | | | | | | |V00a|V22i| 48.#25 x0 Fixd Keep x0 | | | | | | | | |V00a|V22i| 48.#26 I18 Def Alloc x0 |I18a| | | | | | | |V00a|V22i| [000275] 50.#27 C19 Def ORDER(A) x1 |I18a|C19a| | | | | | |V00a|V22i| [000276] 51.#28 x0 Fixd Keep x0 |I18a|C19a| | | | | | |V00a|V22i| 51.#29 I18 Use * Keep x0 |I18a|C19a| | | | | | |V00a|V22i| 51.#30 C19 Use * Keep x1 |I18a|C19a| | | | | | |V00a|V22i| 52.#31 Kill None [x0-xip1 lr] | | | | | | | | |V00a|V22i| 52.#32 x0 Fixd Keep x0 | | | | | | | | |V00a|V22i| 52.#33 I20 Def Alloc x0 |I20a| | | | | | | |V00a|V22i| [000278] 53.#34 I20 Use * Keep x0 |I20a| | | | | | | |V00a|V22i| 54.#35 V22 Def Keep x20 | | | | | | | | |V00a|V22a| --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 55.#36 BB20 PredBB23 | | | | | | | | |V00a|V22a| [000104] 63.#37 V22 Use * Keep x20 | | | | | | | | |V00a|V22a| 64.#38 I21 Def BSFIT(A) x0 |I21a| | | | | | | |V00a| | [000007] 65.#39 I21 Use * Keep x0 |I21a| | | | | | | |V00a| | 66.#40 V02 Def COVRS(A) x0 |V02a| | | | | | | |V00a| | [000011] 75.#41 V02 Use Keep x0 |V02a| | | | | | | |V00a| | 76.#42 I22 Def BSFIT(A) x1 |V02a|I22a| | | | | | |V00a| | [000014] 81.#43 V02 Use * Keep x0 |V02i|I22a| | | | | | |V00a| | 81.#44 I22 Use * Keep x1 |V02i|I22a| | | | | | |V00a| | 82.#45 I23 Def RELPR(A) x0 |I23a| | | | | | | |V00a| | [000015] 83.#46 I23 Use * Keep x0 |I23a| | | | | | | |V00a| | Restr x0 |V02i| | | | | | | |V00a| | 84.#47 V02 Def THISA(A) x0 |V02a| | | | | | | |V00a| | [000019] 89.#48 V00 Use * Keep x19 |V02a| | | | | | | |V00a| | [000020] 94.#49 I24 Def BSFIT(A) x1 |V02a|I24a| | | | | | | | | [000227] 95.#50 I24 Use * Keep x1 |V02a|I24a| | | | | | | | | 96.#51 V20 Def COVRS(A) x1 |V02a|V20a| | | | | | | | | [000111] 101.#52 V20 Use * Keep x1 |V02a|V20a| | | | | | | | | 102.#53 I25 Def BSFIT(A) x1 |V02a|I25a| | | | | | | | | [000024] 103.#54 I25 Use * Keep x1 |V02a|I25a| | | | | | | | | 104.#55 V04 Def COVRS(A) x1 |V02a|V04a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 105.#56 BB4 PredBB20 |V02a|V04a| | | | | | | | | [000026] 111.#57 V04 Use Keep x1 |V02a|V04a| | | | | | | | | 112.#58 I26 Def ORDER(A) x2 |V02a|V04a|I26a| | | | | | | | [000027] 113.#59 I26 Use * Keep x2 |V02a|V04a|I26a| | | | | | | | 114.#60 V05 Def COVRS(A) x2 |V02a|V04a|V05a| | | | | | | | [000031] 119.#61 V05 Use Keep x2 |V02a|V04a|V05a| | | | | | | | 120.#62 I27 Def ORDER(A) x3 |V02a|V04a|V05a|I27a| | | | | | | [000033] 123.#63 I27 Use * Keep x3 |V02a|V04a|V05a|I27a| | | | | | | 123.#64 V02 Use Keep x0 |V02a|V04a|V05a|I27a| | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 127.#65 BB5 PredBB4 |V02a|V04a|V05a| | | | | | | | [000064] 135.#66 V05 Use Keep x2 |V02a|V04a|V05a| | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 137.#67 BB6 PredBB5 |V02a|V04a|V05a| | | | | | | | [000069] 145.#68 V05 Use Keep x2 |V02a|V04a|V05a| | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 149.#69 BB8 PredBB6 |V02a|V04a|V05a| | | | | | | | [000073] 157.#70 V05 Use Keep x2 |V02a|V04a|V05a| | | | | | | | 158.#71 I28 Def ORDER(A) x3 |V02a|V04a|V05a|I28a| | | | | | | [000074] 159.#72 I28 Use * Keep x3 |V02a|V04a|V05a|I28a| | | | | | | 160.#73 V09 Def COVRS(A) x3 |V02a|V04a|V05a|V09a| | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 161.#74 BB7 PredBB6 |V02a|V04a|V05a|V09i| | | | | | | [000087] 169.#75 V05 Use Keep x2 |V02a|V04a|V05a|V09i| | | | | | | 170.#76 I29 Def RELPR(A) x3 |V02a|V04a|V05a|I29a| | | | | | | [000088] 171.#77 I29 Use * Keep x3 |V02a|V04a|V05a|I29a| | | | | | | Restr x3 |V02a|V04a|V05a|V09i| | | | | | | 172.#78 V09 Def THISA(A) x3 |V02a|V04a|V05a|V09a| | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 173.#79 BB9 PredBB7 |V02a|V04a|V05a|V09a| | | | | | | [000081] 183.#80 I30 Def ORDER(A) x4 |V02a|V04a|V05a|V09a|I30a| | | | | | 183.#81 V04 Use Keep x1 |V02a|V04a|V05a|V09a|I30a| | | | | | 183.#82 V09 Use *D Keep x3 |V02a|V04a|V05a|V09a|I30a| | | | | | 183.#83 V05 Use Keep x2 |V02a|V04a|V05a|V09a|I30a| | | | | | 183.#84 I30 Use *D Keep x4 |V02a|V04a|V05a|V09a|I30a| | | | | | 184.#85 I31 Def ORDER(A) x5 |V02a|V04a|V05a|V09a|I30a|I31a| | | | | [000083] 187.#86 I31 Use * Keep x5 |V02a|V04a|V05a| | |I31a| | | | | 187.#87 V05 Use * Keep x2 |V02a|V04a|V05i| | |I31a| | | | | [000084] 191.#88 V04 ExpU Keep NA |V02a|V04a|V05i| | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 191.#89 BB10 PredBB4 |V02a| |V05a| | | | | | | | [000115] 199.#90 V05 Use Keep x2 |V02a| |V05a| | | | | | | | 200.#91 I32 Def BSFIT(A) x1 |V02a|I32a|V05a| | | | | | | | [000116] 201.#92 I32 Use * Keep x1 |V02a|I32a|V05a| | | | | | | | 202.#93 V06 Def COVRS(A) x1 |V02a|V06a|V05a| | | | | | | | [000122] 209.#94 V05 Use * Keep x2 |V02a|V06a|V05a| | | | | | | | 210.#95 I33 Def ORDER(A) x2 |V02a|V06a|I33a| | | | | | | | [000123] 212.#96 C34 Def ORDER(A) x3 |V02a|V06a|I33a|C34a| | | | | | | [000124] 213.#97 I33 Use * Keep x2 |V02a|V06a|I33a|C34a| | | | | | | 213.#98 C34 Use * Keep x3 |V02a|V06a|I33a|C34a| | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 217.#99 BB12 PredBB10 |V02a|V06a| | | | | | | | | [000133] 222.#100 C35 Def ORDER(A) x2 |V02a|V06a|C35a| | | | | | | | [000134] 223.#101 C35 Use * Keep x2 |V02a|V06a|C35a| | | | | | | | 224.#102 I36 Def ORDER(A) x2 |V02a|V06a|I36a| | | | | | | | [000137] 227.#103 I36 Use * Keep x2 |V02a|V06a|I36a| | | | | | | | 228.#104 I37 Def ORDER(A) x2 |V02a|V06a|I37a| | | | | | | | [000138] 229.#105 I37 Use * Keep x2 |V02a|V06a|I37a| | | | | | | | 230.#106 V13 Def COVRS(A) x2 |V02a|V06a|V13a| | | | | | | | [000141] 235.#107 V13 Use Keep x2 |V02a|V06a|V13a| | | | | | | | [000235] 243.#108 V13 Use * Keep x2 |V02a|V06a|V13a| | | | | | | | 244.#109 I38 Def ORDER(A) x2 |V02a|V06a|I38a| | | | | | | | [000146] 251.#110 V06 Use * Keep x1 |V02a|V06a|I38a| | | | | | | | 252.#111 I39 Def BSFIT(A) x1 |V02a|I39a|I38a| | | | | | | | [000130] 255.#112 I38 Use * Keep x2 |V02a|I39a|I38a| | | | | | | | 255.#113 I39 Use * Keep x1 |V02a|I39a|I38a| | | | | | | | 256.#114 I40 Def BSFIT(A) x1 |V02a|I40a| | | | | | | | | [000045] 257.#115 I40 Use * Keep x1 |V02a|I40a| | | | | | | | | 258.#116 V07 Def COVRS(A) x1 |V02a|V07a| | | | | | | | | [000150] 271.#117 V07 Use Keep x1 |V02a|V07a| | | | | | | | | 272.#118 I41 Def ORDER(A) x2 |V02a|V07a|I41a| | | | | | | | [000151] 275.#119 I41 Use * Keep x2 |V02a|V07a|I41a| | | | | | | | 275.#120 V02 Use * Keep x0 |V02a|V07a|I41a| | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 279.#121 BB14 PredBB12 | |V07a| | | | | | | | | [000158] 287.#122 V07 Use Keep x1 | |V07a| | | | | | | | | 288.#123 I42 Def BSFIT(A) x0 |I42a|V07a| | | | | | | | | [000259] 289.#124 I42 Use * Keep x0 |I42a|V07a| | | | | | | | | 290.#125 V21 Def COVRS(A) x0 |V21a|V07a| | | | | | | | | [000161] 295.#126 V21 Use Keep x0 |V21a|V07a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 297.#127 BB17 PredBB14 |V21a|V07a| | | | | | | | | [000167] 305.#128 V21 Use * Keep x0 |V21a|V07a| | | | | | | | | 306.#129 I43 Def BSFIT(A) x0 |I43a|V07a| | | | | | | | | [000169] 311.#130 V07 Use * Keep x1 |I43a|V07i| | | | | | | | | 311.#131 I43 Use * Keep x0 |I43a|V07i| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 313.#132 BB15 PredBB14 | |V07a| | | | | | | | | [000173] 323.#133 V07 Use Keep x1 | |V07a| | | | | | | | | [000251] 331.#134 V07 Use Keep x1 | |V07a| | | | | | | | | 332.#135 I44 Def BSFIT(A) x0 |I44a|V07a| | | | | | | | | [000204] 335.#136 I45 Def ORDER(A) x2 |I44a|V07a|I45a| | | | | | | | 335.#137 I46 Def ORDER(A) x3 |I44a|V07a|I45a|I46a| | | | | | | 335.#138 I44 Use *D Keep x0 |I44a|V07a|I45a|I46a| | | | | | | 335.#139 I45 Use *D Keep x2 |I44a|V07a|I45a|I46a| | | | | | | 335.#140 I46 Use *D Keep x3 |I44a|V07a|I45a|I46a| | | | | | | 336.#141 I47 Def ORDER(A) x4 |I44a|V07a|I45a|I46a|I47a| | | | | | [000206] 339.#142 I47 Use * Keep x4 | |V07a| | |I47a| | | | | | 340.#143 I48 Def BSFIT(A) x0 |I48a|V07a| | | | | | | | | [000212] 341.#144 I48 Use * Keep x0 |I48a|V07a| | | | | | | | | 342.#145 V17 Def COVRS(A) x0 |V17a|V07a| | | | | | | | | [000211] 347.#146 V17 Use * Keep x0 |V17a|V07a| | | | | | | | | 348.#147 V19 Def ORDER(A) x2 | |V07a|V19a| | | | | | | | [000218] 355.#148 V19 Use Keep x2 | |V07a|V19a| | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 359.#149 BB16 PredBB15 | |V07a|V19a| | | | | | | | [000322] 365.#150 x0 Fixd Keep x0 | |V07a|V19a| | | | | | | | 365.#151 V07 Use * Copy x0 |V07a|V07a|V19a| | | | | | | | 366.#152 x0 Fixd Keep x0 | | |V19a| | | | | | | | 366.#153 I49 Def Alloc x0 |I49a| |V19a| | | | | | | | [000323] 369.#154 x1 Fixd Keep x1 |I49a| |V19a| | | | | | | | 369.#155 V19 Use * Copy x1 |I49a|V19a|V19a| | | | | | | | 370.#156 x1 Fixd Keep x1 |I49a| | | | | | | | | | 370.#157 I50 Def Alloc x1 |I49a|I50a| | | | | | | | | [000186] 371.#158 x0 Fixd Keep x0 |I49a|I50a| | | | | | | | | 371.#159 I49 Use * Keep x0 |I49a|I50a| | | | | | | | | 371.#160 x1 Fixd Keep x1 |I49a|I50a| | | | | | | | | 371.#161 I50 Use * Keep x1 |I49a|I50a| | | | | | | | | 372.#162 Kill None [x0-xip1 lr] | | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 373.#163 BB13 PredBB12 | | | | | | | | | | | [000155] 378.#164 Kill None [x0-xip1 lr] | | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 379.#165 BB11 PredBB10 | | | | | | | | | | | [000052] 384.#166 C51 Def Alloc x0 |C51a| | | | | | | | | | [000319] 385.#167 x0 Fixd Keep x0 |C51a| | | | | | | | | | 385.#168 C51 Use * Keep x0 |C51a| | | | | | | | | | 386.#169 x0 Fixd Keep x0 | | | | | | | | | | | 386.#170 I52 Def Alloc x0 |I52a| | | | | | | | | | [000053] 387.#171 x0 Fixd Keep x0 |I52a| | | | | | | | | | 387.#172 I52 Use * Keep x0 |I52a| | | | | | | | | | 388.#173 Kill None [x0-xip1 lr] | | | | | | | | | | | 388.#174 x0 Fixd Keep x0 | | | | | | | | | | | 388.#175 I53 Def Alloc x0 |I53a| | | | | | | | | | [000054] 389.#176 I53 Use * Keep x0 |I53a| | | | | | | | | | 390.#177 V08 Def ORDER(A) x19 | | | | | | | | |V08a| | [000320] 395.#178 x0 Fixd Keep x0 | | | | | | | | |V08a| | 395.#179 V08 Use Copy x0 |V08a| | | | | | | |V08a| | 396.#180 x0 Fixd Keep x0 |V08a| | | | | | | |V08a| | 396.#181 I54 Def Alloc x0 |I54a| | | | | | | |V08a| | [000056] 397.#182 x0 Fixd Keep x0 |I54a| | | | | | | |V08a| | 397.#183 I54 Use * Keep x0 |I54a| | | | | | | |V08a| | 398.#184 Kill None [x0-xip1 lr] | | | | | | | | |V08a| | [000321] 403.#185 x0 Fixd Keep x0 | | | | | | | | |V08a| | 403.#186 V08 Use * Copy x0 |V08a| | | | | | | |V08a| | 404.#187 x0 Fixd Keep x0 | | | | | | | | | | | 404.#188 I55 Def Alloc x0 |I55a| | | | | | | | | | [000058] 405.#189 x0 Fixd Keep x0 |I55a| | | | | | | | | | 405.#190 I55 Use * Keep x0 |I55a| | | | | | | | | | 406.#191 Kill None [x0-xip1 lr] | | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 407.#192 BB18 PredBB9 | | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 419.#193 BB2 PredBB1 | | | | | | | | | | | [000222] 424.#194 C56 Def Alloc x0 |C56a| | | | | | | | | | [000317] 425.#195 x0 Fixd Keep x0 |C56a| | | | | | | | | | 425.#196 C56 Use * Keep x0 |C56a| | | | | | | | | | 426.#197 x0 Fixd Keep x0 | | | | | | | | | | | 426.#198 I57 Def Alloc x0 |I57a| | | | | | | | | | [000099] 427.#199 x0 Fixd Keep x0 |I57a| | | | | | | | | | 427.#200 I57 Use * Keep x0 |I57a| | | | | | | | | | 428.#201 Kill None [x0-xip1 lr] | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB00 regmask=[x19] minReg=1 regOptional wt=100.00> LCL_VAR BB01 regmask=[x19] minReg=1 wt=400.00> CNS_INT BB03 regmask=[x2] minReg=1 wt=400.00> BB03 regmask=[x0] minReg=1 wt=100.00> BB03 regmask=[x1] minReg=1 wt=100.00> BB03 regmask=[x2] minReg=1 wt=100.00> BB03 regmask=[x2] minReg=1 last fixed wt=100.00> BB03 regmask=[x0] minReg=1 wt=100.00> CALL BB03 regmask=[x0] minReg=1 fixed wt=400.00> BB03 regmask=[x0] minReg=1 last wt=100.00> STORE_LCL_VAR BB03 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB03 regmask=[x0] minReg=1 wt=400.00> IND BB03 regmask=[x20] minReg=1 wt=400.00> BB03 regmask=[x20] minReg=1 last wt=100.00> STORE_LCL_VAR BB03 regmask=[x20] minReg=1 wt=1000.00> LCL_VAR BB03 regmask=[x20] minReg=1 wt=1000.00> LCL_VAR BB23 regmask=[x20] minReg=1 last wt=1000.00> STORE_LCL_VAR BB23 regmask=[x20] minReg=1 wt=1000.00> BB22 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB22 regmask=[x0] minReg=1 last fixed wt=400.00> BB22 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB22 regmask=[x0] minReg=1 fixed wt=0.00> CNS_INT BB22 regmask=[x1] minReg=1 wt=0.00> BB22 regmask=[x0] minReg=1 wt=0.00> BB22 regmask=[x0] minReg=1 last fixed wt=0.00> BB22 regmask=[x1] minReg=1 last wt=0.00> BB22 regmask=[x0] minReg=1 wt=0.00> CALL BB22 regmask=[x0] minReg=1 fixed wt=0.00> BB22 regmask=[x0] minReg=1 last wt=0.00> STORE_LCL_VAR BB22 regmask=[x20] minReg=1 wt=1000.00> LCL_VAR BB20 regmask=[x20] minReg=1 last wt=1000.00> IND BB20 regmask=[x0] minReg=1 wt=400.00> BB20 regmask=[x0] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x0] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x0] minReg=1 wt=1250.00> ADD BB20 regmask=[x1] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x0] minReg=1 last wt=1250.00> BB20 regmask=[x1] minReg=1 last wt=100.00> OR BB20 regmask=[x0] minReg=1 wt=400.00> BB20 regmask=[x0] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x0] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x19] minReg=1 last wt=400.00> LCL_VAR BB20 regmask=[x1] minReg=1 wt=400.00> BB20 regmask=[x1] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x1] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x1] minReg=1 last wt=400.00> ADD BB20 regmask=[x1] minReg=1 wt=400.00> BB20 regmask=[x1] minReg=1 last wt=100.00> STORE_LCL_VAR BB20 regmask=[x1] minReg=1 wt=1300.00> LCL_VAR BB04 regmask=[x1] minReg=1 wt=1300.00> IND BB04 regmask=[x2] minReg=1 wt=3200.00> BB04 regmask=[x2] minReg=1 last wt=800.00> STORE_LCL_VAR BB04 regmask=[x2] minReg=1 wt=3700.00> LCL_VAR BB04 regmask=[x2] minReg=1 regOptional wt=3700.00> CAST BB04 regmask=[x3] minReg=1 wt=3200.00> BB04 regmask=[x3] minReg=1 last wt=800.00> LCL_VAR BB04 regmask=[x0] minReg=1 wt=1250.00> LCL_VAR BB05 regmask=[x2] minReg=1 wt=3700.00> LCL_VAR BB06 regmask=[x2] minReg=1 wt=3700.00> LCL_VAR BB08 regmask=[x2] minReg=1 wt=3700.00> ADD BB08 regmask=[x3] minReg=1 wt=800.00> BB08 regmask=[x3] minReg=1 last wt=200.00> STORE_LCL_VAR BB08 regmask=[x3] minReg=1 wt=800.00> LCL_VAR BB07 regmask=[x2] minReg=1 wt=3700.00> AND BB07 regmask=[x3] minReg=1 wt=800.00> BB07 regmask=[x3] minReg=1 last wt=200.00> STORE_LCL_VAR BB07 regmask=[x3] minReg=1 wt=800.00> CMPXCHG BB09 regmask=[x4] minReg=1 wt=1600.00> LCL_VAR BB09 regmask=[x1] minReg=1 delay wt=1300.00> LCL_VAR BB09 regmask=[x3] minReg=1 last delay wt=800.00> LCL_VAR BB09 regmask=[x2] minReg=1 delay wt=3700.00> CMPXCHG BB09 regmask=[x4] minReg=1 last delay wt=1600.00> CMPXCHG BB09 regmask=[x5] minReg=1 wt=1600.00> BB09 regmask=[x5] minReg=1 last wt=400.00> LCL_VAR BB09 regmask=[x2] minReg=1 last wt=3700.00> BB09 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB10 regmask=[x2] minReg=1 wt=3700.00> AND BB10 regmask=[x1] minReg=1 wt=200.00> BB10 regmask=[x1] minReg=1 last wt=50.00> STORE_LCL_VAR BB10 regmask=[x1] minReg=1 wt=100.00> LCL_VAR BB10 regmask=[x2] minReg=1 last wt=3700.00> AND BB10 regmask=[x2] minReg=1 wt=200.00> CNS_INT BB10 regmask=[x3] minReg=1 wt=200.00> BB10 regmask=[x2] minReg=1 last wt=50.00> BB10 regmask=[x3] minReg=1 last wt=50.00> CNS_INT BB12 regmask=[x2] minReg=1 wt=200.00> BB12 regmask=[x2] minReg=1 last wt=50.00> IND BB12 regmask=[x2] minReg=1 wt=200.00> BB12 regmask=[x2] minReg=1 last wt=50.00> IND BB12 regmask=[x2] minReg=1 wt=200.00> BB12 regmask=[x2] minReg=1 last wt=50.00> STORE_LCL_VAR BB12 regmask=[x2] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x2] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x2] minReg=1 last wt=300.00> ADD BB12 regmask=[x2] minReg=1 wt=200.00> LCL_VAR BB12 regmask=[x1] minReg=1 last wt=100.00> BFIZ BB12 regmask=[x1] minReg=1 wt=200.00> BB12 regmask=[x2] minReg=1 last wt=50.00> BB12 regmask=[x1] minReg=1 last wt=50.00> IND BB12 regmask=[x1] minReg=1 wt=200.00> BB12 regmask=[x1] minReg=1 last wt=50.00> STORE_LCL_VAR BB12 regmask=[x1] minReg=1 wt=350.00> LCL_VAR BB12 regmask=[x1] minReg=1 wt=350.00> IND BB12 regmask=[x2] minReg=1 wt=200.00> BB12 regmask=[x2] minReg=1 last wt=50.00> LCL_VAR BB12 regmask=[x0] minReg=1 last wt=1250.00> LCL_VAR BB14 regmask=[x1] minReg=1 wt=350.00> IND BB14 regmask=[x0] minReg=1 wt=200.00> BB14 regmask=[x0] minReg=1 last wt=50.00> STORE_LCL_VAR BB14 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB14 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB17 regmask=[x0] minReg=1 last wt=150.00> ADD BB17 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB17 regmask=[x1] minReg=1 last wt=350.00> BB17 regmask=[x0] minReg=1 last wt=50.00> LCL_VAR BB15 regmask=[x1] minReg=1 wt=350.00> LCL_VAR BB15 regmask=[x1] minReg=1 wt=350.00> ADD BB15 regmask=[x0] minReg=1 wt=200.00> XADD BB15 regmask=[x2] minReg=1 wt=200.00> XADD BB15 regmask=[x3] minReg=1 wt=200.00> BB15 regmask=[x0] minReg=1 last delay wt=50.00> XADD BB15 regmask=[x2] minReg=1 last delay wt=200.00> XADD BB15 regmask=[x3] minReg=1 last delay wt=200.00> XADD BB15 regmask=[x4] minReg=1 wt=200.00> BB15 regmask=[x4] minReg=1 last wt=50.00> ADD BB15 regmask=[x0] minReg=1 wt=200.00> BB15 regmask=[x0] minReg=1 last wt=50.00> STORE_LCL_VAR BB15 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB15 regmask=[x0] minReg=1 last wt=200.00> STORE_LCL_VAR BB15 regmask=[x2] minReg=1 wt=150.00> LCL_VAR BB15 regmask=[x2] minReg=1 wt=150.00> BB16 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB16 regmask=[x0] minReg=1 last copy fixed wt=350.00> BB16 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB16 regmask=[x0] minReg=1 fixed wt=200.00> BB16 regmask=[x1] minReg=1 wt=50.00> LCL_VAR BB16 regmask=[x1] minReg=1 last copy fixed wt=150.00> BB16 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB16 regmask=[x1] minReg=1 fixed wt=200.00> BB16 regmask=[x0] minReg=1 wt=50.00> BB16 regmask=[x0] minReg=1 last fixed wt=50.00> BB16 regmask=[x1] minReg=1 wt=50.00> BB16 regmask=[x1] minReg=1 last fixed wt=50.00> CNS_INT BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> CALL BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 last wt=0.00> STORE_LCL_VAR BB11 regmask=[x19] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 copy fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 last copy fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> PUTARG_REG BB11 regmask=[x0] minReg=1 fixed wt=0.00> BB11 regmask=[x0] minReg=1 wt=0.00> BB11 regmask=[x0] minReg=1 last fixed wt=0.00> CNS_INT BB02 regmask=[x0] minReg=1 wt=200.00> BB02 regmask=[x0] minReg=1 wt=50.00> BB02 regmask=[x0] minReg=1 last fixed wt=50.00> BB02 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB02 regmask=[x0] minReg=1 fixed wt=200.00> BB02 regmask=[x0] minReg=1 wt=50.00> BB02 regmask=[x0] minReg=1 last fixed wt=50.00> VAR REFPOSITIONS AFTER ALLOCATION --- V00 (Interval 0) BB00 regmask=[x19] minReg=1 regOptional wt=100.00> LCL_VAR BB01 regmask=[x19] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x19] minReg=1 last wt=400.00> --- V01 --- V02 (Interval 1) STORE_LCL_VAR BB20 regmask=[x0] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x0] minReg=1 wt=1250.00> LCL_VAR BB20 regmask=[x0] minReg=1 last wt=1250.00> STORE_LCL_VAR BB20 regmask=[x0] minReg=1 wt=1250.00> LCL_VAR BB04 regmask=[x0] minReg=1 wt=1250.00> LCL_VAR BB12 regmask=[x0] minReg=1 last wt=1250.00> --- V03 --- V04 (Interval 2) STORE_LCL_VAR BB20 regmask=[x1] minReg=1 wt=1300.00> LCL_VAR BB04 regmask=[x1] minReg=1 wt=1300.00> LCL_VAR BB09 regmask=[x1] minReg=1 delay wt=1300.00> BB09 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V05 (Interval 3) STORE_LCL_VAR BB04 regmask=[x2] minReg=1 wt=3700.00> LCL_VAR BB04 regmask=[x2] minReg=1 regOptional wt=3700.00> LCL_VAR BB05 regmask=[x2] minReg=1 wt=3700.00> LCL_VAR BB06 regmask=[x2] minReg=1 wt=3700.00> LCL_VAR BB08 regmask=[x2] minReg=1 wt=3700.00> LCL_VAR BB07 regmask=[x2] minReg=1 wt=3700.00> LCL_VAR BB09 regmask=[x2] minReg=1 delay wt=3700.00> LCL_VAR BB09 regmask=[x2] minReg=1 last wt=3700.00> LCL_VAR BB10 regmask=[x2] minReg=1 wt=3700.00> LCL_VAR BB10 regmask=[x2] minReg=1 last wt=3700.00> --- V06 (Interval 4) STORE_LCL_VAR BB10 regmask=[x1] minReg=1 wt=100.00> LCL_VAR BB12 regmask=[x1] minReg=1 last wt=100.00> --- V07 (Interval 5) STORE_LCL_VAR BB12 regmask=[x1] minReg=1 wt=350.00> LCL_VAR BB12 regmask=[x1] minReg=1 wt=350.00> LCL_VAR BB14 regmask=[x1] minReg=1 wt=350.00> LCL_VAR BB17 regmask=[x1] minReg=1 last wt=350.00> LCL_VAR BB15 regmask=[x1] minReg=1 wt=350.00> LCL_VAR BB15 regmask=[x1] minReg=1 wt=350.00> LCL_VAR BB16 regmask=[x0] minReg=1 last copy fixed wt=350.00> --- V08 (Interval 6) STORE_LCL_VAR BB11 regmask=[x19] minReg=1 wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 copy fixed wt=0.00> LCL_VAR BB11 regmask=[x0] minReg=1 last copy fixed wt=0.00> --- V09 (Interval 7) STORE_LCL_VAR BB08 regmask=[x3] minReg=1 wt=800.00> STORE_LCL_VAR BB07 regmask=[x3] minReg=1 wt=800.00> LCL_VAR BB09 regmask=[x3] minReg=1 last delay wt=800.00> --- V10 --- V11 --- V12 --- V13 (Interval 8) STORE_LCL_VAR BB12 regmask=[x2] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x2] minReg=1 wt=300.00> LCL_VAR BB12 regmask=[x2] minReg=1 last wt=300.00> --- V14 --- V15 --- V16 --- V17 (Interval 9) STORE_LCL_VAR BB15 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB15 regmask=[x0] minReg=1 last wt=200.00> --- V18 --- V19 (Interval 10) STORE_LCL_VAR BB15 regmask=[x2] minReg=1 wt=150.00> LCL_VAR BB15 regmask=[x2] minReg=1 wt=150.00> LCL_VAR BB16 regmask=[x1] minReg=1 last copy fixed wt=150.00> --- V20 (Interval 11) STORE_LCL_VAR BB20 regmask=[x1] minReg=1 wt=400.00> LCL_VAR BB20 regmask=[x1] minReg=1 last wt=400.00> --- V21 (Interval 12) STORE_LCL_VAR BB14 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB14 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB17 regmask=[x0] minReg=1 last wt=150.00> --- V22 (Interval 13) STORE_LCL_VAR BB03 regmask=[x20] minReg=1 wt=1000.00> LCL_VAR BB03 regmask=[x20] minReg=1 wt=1000.00> LCL_VAR BB23 regmask=[x20] minReg=1 last wt=1000.00> STORE_LCL_VAR BB23 regmask=[x20] minReg=1 wt=1000.00> STORE_LCL_VAR BB22 regmask=[x20] minReg=1 wt=1000.00> LCL_VAR BB20 regmask=[x20] minReg=1 last wt=1000.00> --- V23 (Interval 14) STORE_LCL_VAR BB03 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB03 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB22 regmask=[x0] minReg=1 last fixed wt=400.00> Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V02 V04 V05 V06 V07 V09 V19 V21 V22 V23} Has Critical Edges Prior to Resolution BB01 use: {V00} def: {} in: {V00} out: {V00} Var=Reg beg of BB01: V00=x19 Var=Reg end of BB01: V00=x19 BB02 use: {} def: {} in: {} out: {} Var=Reg beg of BB02: none Var=Reg end of BB02: none BB03 use: {} def: {V22 V23} in: {V00} out: {V00 V22 V23} Var=Reg beg of BB03: V00=x19 Var=Reg end of BB03: V22=x20 V00=x19 V23=x0 BB22 use: {V23} def: {V22} in: {V00 V23} out: {V00 V22} Var=Reg beg of BB22: V00=x19 V23=x0 Var=Reg end of BB22: V22=x20 V00=x19 BB23 use: {V22} def: {V22} in: {V00 V22} out: {V00 V22} Var=Reg beg of BB23: V22=x20 V00=x19 Var=Reg end of BB23: V22=x20 V00=x19 BB20 use: {V00 V22} def: {V02 V04 V20} in: {V00 V22} out: {V02 V04} Var=Reg beg of BB20: V22=x20 V00=x19 Var=Reg end of BB20: V04=x1 V02=x0 BB04 use: {V02 V04} def: {V05} in: {V02 V04} out: {V02 V04 V05} Var=Reg beg of BB04: V04=x1 V02=x0 Var=Reg end of BB04: V05=x2 V04=x1 V02=x0 BB05 use: {V05} def: {} in: {V02 V04 V05} out: {V02 V04 V05} Var=Reg beg of BB05: V05=x2 V04=x1 V02=x0 Var=Reg end of BB05: V05=x2 V04=x1 V02=x0 BB06 use: {V05} def: {} in: {V02 V04 V05} out: {V02 V04 V05} Var=Reg beg of BB06: V05=x2 V04=x1 V02=x0 Var=Reg end of BB06: V05=x2 V04=x1 V02=x0 BB07 use: {V05} def: {V09} in: {V02 V04 V05} out: {V02 V04 V05 V09} Var=Reg beg of BB07: V05=x2 V04=x1 V02=x0 Var=Reg end of BB07: V05=x2 V04=x1 V02=x0 V09=x3 BB08 use: {V05} def: {V09} in: {V02 V04 V05} out: {V02 V04 V05 V09} Var=Reg beg of BB08: V05=x2 V04=x1 V02=x0 Var=Reg end of BB08: V05=x2 V04=x1 V02=x0 V09=x3 BB09 use: {V04 V05 V09} def: {} in: {V02 V04 V05 V09} out: {V02 V04} Var=Reg beg of BB09: V05=x2 V04=x1 V02=x0 V09=x3 Var=Reg end of BB09: V04=x1 V02=x0 BB10 use: {V05} def: {V06} in: {V02 V05} out: {V02 V06} Var=Reg beg of BB10: V05=x2 V02=x0 Var=Reg end of BB10: V02=x0 V06=x1 BB11 use: {} def: {V08} in: {} out: {} Var=Reg beg of BB11: none Var=Reg end of BB11: none BB12 use: {V02 V06} def: {V07 V13} in: {V02 V06} out: {V07} Var=Reg beg of BB12: V02=x0 V06=x1 Var=Reg end of BB12: V07=x1 BB13 use: {} def: {} in: {} out: {} Var=Reg beg of BB13: none Var=Reg end of BB13: none BB14 use: {V07} def: {V21} in: {V07} out: {V07 V21} Var=Reg beg of BB14: V07=x1 Var=Reg end of BB14: V07=x1 V21=x0 BB15 use: {V07} def: {V17 V19} in: {V07} out: {V07 V19} Var=Reg beg of BB15: V07=x1 Var=Reg end of BB15: V07=x1 V19=x2 BB16 use: {V07 V19} def: {} in: {V07 V19} out: {} Var=Reg beg of BB16: V07=x1 V19=x2 Var=Reg end of BB16: none BB17 use: {V07 V21} def: {} in: {V07 V21} out: {} Var=Reg beg of BB17: V07=x1 V21=x0 Var=Reg end of BB17: none BB18 use: {} def: {} in: {} out: {} Var=Reg beg of BB18: none Var=Reg end of BB18: none RESOLVING EDGES Set V00 argument initial register to x19 Trees after linear scan register allocator (LSRA) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i LIR BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i LIR hascall nullcheck BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i LIR BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i LIR nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} N003 (???,???) [000281] ----------- IL_OFFSET void INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR ref V00 arg0 u:1 x19 REG x19 $80 N007 ( 1, 2) [000095] -c---+----- t95 = CNS_INT ref null REG NA $VN.Null /--* t0 ref +--* t95 ref N009 ( 5, 6) [000097] -----+----- * JCMP void REG NA ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} N421 (???,???) [000282] ----------- IL_OFFSET void INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA N423 ( 2, 8) [000222] H----+----- t222 = CNS_INT(h) ref '"obj"' REG x0 $500 /--* t222 ref N425 (???,???) [000317] ----------- t317 = * PUTARG_REG ref REG x0 /--* t317 ref arg0 in x0 N427 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) REG NA $VN.Void ------------ BB03 [0015] [???..???) -> BB23(1),BB22(0) (cond), preds={BB01} succs={BB22,BB23} N013 (???,???) [000283] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N015 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN REG x2 /--* t265 long calli tgt N017 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long REG x0 /--* t266 long N019 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 x0 REG x0 N021 ( 3, 2) [000268] ----------- t268 = LCL_VAR long V23 rat1 x0 REG x0 /--* t268 long N023 ( 6, 4) [000269] #---------- t269 = * IND ref REG x20 /--* t269 ref N025 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 N027 ( 3, 2) [000272] ----------- t272 = LCL_VAR ref V22 rat0 x20 REG x20 N029 ( 1, 2) [000271] -c--------- t271 = CNS_INT long 0 REG NA /--* t272 ref +--* t271 long N031 ( 10, 7) [000274] ----------- * JCMP void REG NA ------------ BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} N043 (???,???) [000284] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N045 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 x0 (last use) REG x0 /--* t277 long N047 (???,???) [000318] ----------- t318 = * PUTARG_REG long REG x0 N049 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls REG x1 /--* t318 long arg0 in x0 +--* t275 long calli tgt N051 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref REG x0 /--* t276 ref N053 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 x20 REG x20 ------------ BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} N035 (???,???) [000285] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N037 ( 3, 2) [000279] ----------- t279 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t279 ref N039 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 ------------ BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} N057 (???,???) [000286] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N059 ( 3, 2) [000263] ----------- t263 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t263 ref N061 ( 5, 5) [000103] -c---+----- t103 = * LEA(b+40) byref REG NA /--* t103 byref N063 ( 6, 4) [000104] n---G+----- t104 = * IND int REG x0 /--* t104 int N065 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 x0 REG x0 $VN.Void N067 (???,???) [000287] ----------- IL_OFFSET void INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] REG NA N069 ( 1, 1) [000008] -----+----- t8 = LCL_VAR int V02 tmp1 u:1 x0 (last use) REG x0 N071 ( 1, 1) [000009] -----+----- t9 = LCL_VAR int V02 tmp1 u:1 x0 REG x0 N073 ( 1, 2) [000010] -c---+----- t10 = CNS_INT int -1 REG NA $41 /--* t9 int +--* t10 int N075 ( 3, 4) [000011] -----+----- t11 = * ADD int REG x1 N077 ( 1, 2) [000012] -c---+----- t12 = CNS_INT int 31 REG NA $42 /--* t11 int +--* t12 int N079 ( 5, 7) [000013] -c---+----- t13 = * RSH int REG NA /--* t8 int +--* t13 int N081 ( 7, 9) [000014] -----+----- t14 = * OR int REG x0 /--* t14 int N083 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 x0 REG x0 $VN.Void N085 (???,???) [000288] ----------- IL_OFFSET void INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] REG NA N087 ( 1, 1) [000225] -------N--- t225 = LCL_VAR ref V00 arg0 u:1 x19 (last use) REG x19 $80 /--* t225 ref N089 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $281 N091 (???,???) [000289] ----------- IL_OFFSET void INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] REG NA N093 ( 1, 1) [000020] -----+----- t20 = LCL_VAR byref V03 tmp2 x1 REG x1 $182 /--* t20 byref N095 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 x1 REG x1 $VN.Void N097 ( 1, 1) [000228] -----+----- t228 = LCL_VAR long V20 tmp19 u:1 x1 (last use) REG x1 $2c0 N099 ( 1, 2) [000110] -c---+----- t110 = CNS_INT long -4 REG NA $1c1 /--* t228 long +--* t110 long N101 ( 4, 7) [000111] -A---+----- t111 = * ADD long REG x1 $2c1 /--* t111 long N103 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 x1 REG x1 $VN.Void ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} N107 (???,???) [000290] ----------- IL_OFFSET void INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] REG NA N109 ( 1, 1) [000025] -----+----- t25 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 /--* t25 long N111 ( 3, 2) [000026] ---XG+----- t26 = * IND int REG x2 /--* t26 int N113 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 x2 REG x2 $284 N115 (???,???) [000291] ----------- IL_OFFSET void INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] REG NA N117 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t28 int N119 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int REG x3 N121 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 x0 REG x0 /--* t31 int +--* t32 int N123 ( 4, 5) [000033] -----+-N-U- * CMP void REG NA N125 ( 6, 7) [000034] -----+----- JCC void cond=UNE REG NA ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} N129 (???,???) [000292] ----------- IL_OFFSET void INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] REG NA N131 ( 1, 1) [000059] -----+----- t59 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N133 ( 1, 4) [000060] -c---+----- t60 = CNS_INT int 0x8000000 REG NA $46 /--* t59 int +--* t60 int N135 ( 7, 11) [000064] -----+----- * JTEST void REG NA ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} N139 (???,???) [000293] ----------- IL_OFFSET void INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] REG NA N141 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N143 ( 1, 2) [000066] -c---+----- t66 = CNS_INT int 0x3F0000 REG NA $47 /--* t65 int +--* t66 int N145 ( 5, 7) [000069] -----+-N--- * TEST void REG NA N147 ( 7, 9) [000070] -----+----- JCC void cond=UNE REG NA ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} N163 (???,???) [000294] ----------- IL_OFFSET void INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] REG NA N165 ( 1, 1) [000085] -----+----- t85 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N167 ( 1, 2) [000086] -c---+----- t86 = CNS_INT int -0x10000 REG NA $48 /--* t85 int +--* t86 int N169 ( 3, 4) [000087] -----+----- t87 = * AND int REG x3 /--* t87 int N171 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 x3 REG x3 $VN.Void ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} N151 (???,???) [000295] ----------- IL_OFFSET void INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] REG NA N153 ( 1, 1) [000071] -----+----- t71 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N155 ( 1, 2) [000072] -c---+----- t72 = CNS_INT int -0x10000 REG NA $48 /--* t71 int +--* t72 int N157 ( 3, 4) [000073] -----+----- t73 = * ADD int REG x3 /--* t73 int N159 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 x3 REG x3 $VN.Void ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} N175 (???,???) [000296] ----------- IL_OFFSET void INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] REG NA N177 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 N179 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 x3 (last use) REG x3 $340 N181 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t78 long +--* t76 int +--* t80 int N183 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int REG x5 $11a N185 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 /--* t81 int +--* t82 int N187 (255, 10) [000083] -A-XG+-N-U- * CMP void REG NA N189 (255, 12) [000084] -A-XG+----- JCC void cond=UNE REG NA ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} N193 (???,???) [000297] ----------- IL_OFFSET void INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA N195 ( 1, 1) [000035] -----+----- t35 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N197 ( 1, 4) [000114] -c---+----- t114 = CNS_INT int 0x3FFFFFF REG NA $49 /--* t35 int +--* t114 int N199 ( 3, 6) [000115] -----+----- t115 = * AND int REG x1 /--* t115 int N201 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 x1 REG x1 $VN.Void N203 (???,???) [000298] ----------- IL_OFFSET void INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA N205 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 N207 ( 1, 4) [000121] -c---+----- t121 = CNS_INT int 0xC000000 REG NA $4a /--* t117 int +--* t121 int N209 ( 3, 6) [000122] -----+----- t122 = * AND int REG x2 N211 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 REG x3 $46 /--* t122 int +--* t123 int N213 ( 5, 11) [000124] -----+-N--- * CMP void REG NA N215 ( 7, 13) [000041] -----+----- JCC void cond=UEQ REG NA ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} N381 (???,???) [000299] ----------- IL_OFFSET void INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] REG NA N383 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class REG x0 $147 /--* t52 long N385 (???,???) [000319] ----------- t319 = * PUTARG_REG long REG x0 /--* t319 long arg0 in x0 N387 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST REG x0 $298 /--* t53 ref N389 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 x19 REG x19 $VN.Void N391 (???,???) [000300] ----------- IL_OFFSET void INL01 @ ??? <- INLRT @ 0x000[E-] REG NA N393 ( 3, 2) [000055] -----+----- t55 = LCL_VAR ref V08 tmp7 u:2 x19 REG x19 $298 /--* t55 ref N395 (???,???) [000320] ----------- t320 = * PUTARG_REG ref REG x0 /--* t320 ref this in x0 N397 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this REG NA $VN.Void N399 (???,???) [000301] ----------- IL_OFFSET void INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] REG NA N401 ( 3, 2) [000057] -----+----- t57 = LCL_VAR ref V08 tmp7 u:2 x19 (last use) REG x19 $298 /--* t57 ref N403 (???,???) [000321] ----------- t321 = * PUTARG_REG ref REG x0 /--* t321 ref arg0 in x0 N405 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW REG NA $29a ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} N219 (???,???) [000302] ----------- IL_OFFSET void INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N221 ( 2, 8) [000133] H----+----- t133 = CNS_INT(h) long 0x4208C8 static base addr cell REG x2 $142 /--* t133 long N223 ( 5, 10) [000134] #----+----- t134 = * IND long REG x2 $380 /--* t134 long N225 ( 7, 13) [000136] -c---+----- t136 = * LEA(b+16) long REG NA /--* t136 long N227 ( 8, 12) [000137] ---XG+----- t137 = * IND ref REG x2 /--* t137 ref N229 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 x2 REG x2 $289 N231 (???,???) [000303] ----------- IL_OFFSET void INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N233 ( 1, 1) [000140] -----+----- t140 = LCL_VAR ref V13 tmp12 u:2 x2 REG x2 /--* t140 ref N235 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte REG NA N237 (???,???) [000304] ----------- IL_OFFSET void INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N239 ( 1, 1) [000139] -----+----- t139 = LCL_VAR ref V13 tmp12 u:2 x2 (last use) REG x2 N241 ( 1, 2) [000234] -c---+----- t234 = CNS_INT long 16 REG NA $1c3 /--* t139 ref +--* t234 long N243 ( 2, 5) [000235] -----+-N--- t235 = * ADD byref REG x2 N245 ( 3, 2) [000126] -----+----- t126 = LCL_VAR int V06 tmp5 u:1 x1 (last use) REG x1 /--* t126 int N247 ( 4, 4) [000144] -c---+----- t144 = * CAST long <- int REG NA N249 ( 1, 2) [000145] -c---+----- t145 = CNS_INT long 5 REG NA $1c4 /--* t144 long +--* t145 long N251 ( 6, 7) [000146] -----+----- t146 = * BFIZ long REG x1 /--* t235 byref +--* t146 long N253 ( 9, 13) [000147] -c---+----- t147 = * LEA(b+(i*1)+0) byref REG NA /--* t147 byref N255 ( 11, 14) [000130] ---XG+----- t130 = * IND ref REG x1 /--* t130 ref N257 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 x1 REG x1 N259 (???,???) [000305] ----------- IL_OFFSET void INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] REG NA N261 ( 1, 2) [000047] -c---+----- t47 = CNS_INT long 0 REG NA $1c2 /--* t47 long N263 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void N265 (???,???) [000306] ----------- IL_OFFSET void INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N267 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t49 ref N269 ( 3, 4) [000238] -c---+----- t238 = * LEA(b+16) byref REG NA /--* t238 byref N271 ( 4, 3) [000150] ---XG+----- t150 = * IND int REG x2 N273 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 x0 (last use) REG x0 /--* t150 int +--* t50 int N275 ( 6, 5) [000151] ---XG+-N--- * CMP void REG NA N277 ( 8, 7) [000152] ---XG+----- JCC void cond=UEQ REG NA ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} N375 (???,???) [000307] ----------- IL_OFFSET void INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N377 ( 14, 2) [000155] --CXG+----- CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() REG NA $VN.Void ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} N281 (???,???) [000308] ----------- IL_OFFSET void INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N283 ( 1, 1) [000153] ----------- t153 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t153 ref N285 ( 3, 4) [000240] -c--------- t240 = * LEA(b+24) byref REG NA /--* t240 byref N287 ( 4, 3) [000158] n---GO----- t158 = * IND int REG x0 /--* t158 int N289 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 x0 REG x0 N291 ( 3, 2) [000260] ----------- t260 = LCL_VAR int V21 cse0 u:1 x0 REG x0 N293 ( 1, 2) [000159] -c--------- t159 = CNS_INT int 0 REG NA $40 /--* t260 int +--* t159 int N295 ( 15, 13) [000161] -A--GO----- * JCMP void REG NA ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} N315 (???,???) [000309] ----------- IL_OFFSET void INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N317 ( 1, 1) [000170] ----------- t170 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t170 ref N319 ( 3, 4) [000246] -c--------- t246 = * LEA(b+16) byref REG NA N321 ( 1, 2) [000171] -c--------- t171 = CNS_INT int 0 REG NA $40 /--* t246 byref +--* t171 int N323 ( 6, 6) [000173] nA--GO----- * STOREIND int REG NA N325 (???,???) [000310] ----------- IL_OFFSET void INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N327 ( 1, 1) [000249] -----+----- t249 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 N329 ( 1, 2) [000250] -c---+----- t250 = CNS_INT long 20 Fseq[_state] REG NA $1c6 /--* t249 ref +--* t250 long N331 ( 3, 4) [000251] -----+----- t251 = * ADD byref REG x0 N333 ( 1, 2) [000203] -c---+----- t203 = CNS_INT int -1 REG NA $41 /--* t251 byref +--* t203 int N335 ( 5, 7) [000204] -A-XG+----- t204 = * XADD int REG x4 N337 ( 1, 2) [000205] -c---+----- t205 = CNS_INT int -1 REG NA $41 /--* t204 int +--* t205 int N339 ( 7, 10) [000206] -A-XG+----- t206 = * ADD int REG x0 /--* t206 int N341 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 x0 REG x0 N343 (???,???) [000311] ----------- IL_OFFSET void INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N345 ( 1, 1) [000209] -----+----- t209 = LCL_VAR int V17 tmp16 u:1 x0 (last use) REG x0 $13a /--* t209 int N347 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 x2 REG x2 $VN.Void N349 (???,???) [000312] ----------- IL_OFFSET void INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N351 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 x2 REG x2 $13a N353 ( 1, 2) [000217] -c---+----- t217 = CNS_INT int 128 REG NA $4d /--* t216 int +--* t217 int N355 ( 3, 4) [000218] -----+-N-U- * CMP void REG NA N357 ( 5, 6) [000183] -----+----- JCC void cond=ULT REG NA ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} N361 (???,???) [000313] ----------- IL_OFFSET void INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N363 ( 1, 1) [000184] -----+----- t184 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t184 ref N365 (???,???) [000322] ----------- t322 = * PUTARG_REG ref REG x0 N367 ( 3, 2) [000185] -----+----- t185 = LCL_VAR int V19 tmp18 u:1 x2 (last use) REG x2 $13a /--* t185 int N369 (???,???) [000323] ----------- t323 = * PUTARG_REG int REG x1 /--* t322 ref this in x0 +--* t323 int arg1 in x1 N371 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this REG NA $VN.Void ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} N299 (???,???) [000314] ----------- IL_OFFSET void INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N301 ( 3, 2) [000262] ----------- t262 = LCL_VAR int V21 cse0 u:1 x0 (last use) REG x0 N303 ( 1, 2) [000166] -c--------- t166 = CNS_INT int -1 REG NA $41 /--* t262 int +--* t166 int N305 ( 5, 5) [000167] ----G------ t167 = * ADD int REG x0 N307 ( 1, 1) [000162] ----------- t162 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t162 ref N309 ( 3, 4) [000242] -c--------- t242 = * LEA(b+24) byref REG NA /--* t242 byref +--* t167 int N311 ( 10, 9) [000169] nA--GO----- * STOREIND int REG NA ------------ BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} N409 (???,???) [000315] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N411 ( 1, 2) [000092] -c---+----- t92 = CNS_INT byref 0 REG NA $VN.Null /--* t92 byref N413 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void N415 (???,???) [000316] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA N417 ( 0, 0) [000002] -----+----- RETURN void REG NA $VN.Void ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 0.#0 V00 Parm Alloc x19 | | | | | | | | |V00a| | 1.#1 BB1 PredBB0 | | | | | | | | |V00a| | [000097] 9.#2 V00 Use Keep x19 | | | | | | | | |V00a| | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 11.#3 BB3 PredBB1 | | | | | | | | |V00a| | [000265] 16.#4 C15 Def Alloc x2 | | |C15a| | | | | |V00a| | [000266] 17.#5 x0 Fixd Keep x0 | | |C15a| | | | | |V00a| | 17.#6 x1 Fixd Keep x1 | | |C15a| | | | | |V00a| | 17.#7 x2 Fixd Keep x2 | | |C15a| | | | | |V00a| | 17.#8 C15 Use * Keep x2 | | |C15i| | | | | |V00a| | 18.#9 Kill None [x0-xip1 lr] | | | | | | | | |V00a| | 18.#10 x0 Fixd Keep x0 | | | | | | | | |V00a| | 18.#11 I16 Def Alloc x0 |I16a| | | | | | | |V00a| | [000267] 19.#12 I16 Use * Keep x0 |I16i| | | | | | | |V00a| | 20.#13 V23 Def Alloc x0 |V23a| | | | | | | |V00a| | [000269] 23.#14 V23 Use Keep x0 |V23a| | | | | | | |V00a| | 24.#15 I17 Def Alloc x20 |V23a| | | | | | | |V00a|I17a| [000270] 25.#16 I17 Use * Keep x20 |V23a| | | | | | | |V00a|I17i| 26.#17 V22 Def Alloc x20 |V23a| | | | | | | |V00a|V22a| [000274] 31.#18 V22 Use Keep x20 |V23a| | | | | | | |V00a|V22a| --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 33.#19 BB23 PredBB3 | | | | | | | | |V00a|V22a| [000280] 39.#20 V22 Use * Keep x20 | | | | | | | | |V00a|V22i| 40.#21 V22 Def Alloc x20 | | | | | | | | |V00a|V22a| --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 41.#22 BB22 PredBB3 |V23a| | | | | | | |V00a| | [000318] 47.#23 x0 Fixd Keep x0 |V23a| | | | | | | |V00a| | 47.#24 V23 Use * Keep x0 |V23i| | | | | | | |V00a| | 48.#25 x0 Fixd Keep x0 | | | | | | | | |V00a| | 48.#26 I18 Def Alloc x0 |I18a| | | | | | | |V00a| | [000275] 50.#27 C19 Def Alloc x1 |I18a|C19a| | | | | | |V00a| | [000276] 51.#28 x0 Fixd Keep x0 |I18a|C19a| | | | | | |V00a| | 51.#29 I18 Use * Keep x0 |I18i|C19a| | | | | | |V00a| | 51.#30 C19 Use * Keep x1 | |C19i| | | | | | |V00a| | 52.#31 Kill None [x0-xip1 lr] | | | | | | | | |V00a| | 52.#32 x0 Fixd Keep x0 | | | | | | | | |V00a| | 52.#33 I20 Def Alloc x0 |I20a| | | | | | | |V00a| | [000278] 53.#34 I20 Use * Keep x0 |I20i| | | | | | | |V00a| | 54.#35 V22 Def Alloc x20 | | | | | | | | |V00a|V22a| --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 55.#36 BB20 PredBB23 | | | | | | | | |V00a|V22a| [000104] 63.#37 V22 Use * Keep x20 | | | | | | | | |V00a|V22i| 64.#38 I21 Def Alloc x0 |I21a| | | | | | | |V00a| | [000007] 65.#39 I21 Use * Keep x0 |I21i| | | | | | | |V00a| | 66.#40 V02 Def Alloc x0 |V02a| | | | | | | |V00a| | [000011] 75.#41 V02 Use Keep x0 |V02a| | | | | | | |V00a| | 76.#42 I22 Def Alloc x1 |V02a|I22a| | | | | | |V00a| | [000014] 81.#43 V02 Use * Keep x0 |V02i|I22a| | | | | | |V00a| | 81.#44 I22 Use * Keep x1 | |I22i| | | | | | |V00a| | 82.#45 I23 Def Alloc x0 |I23a| | | | | | | |V00a| | [000015] 83.#46 I23 Use * Keep x0 |I23i| | | | | | | |V00a| | 84.#47 V02 Def Alloc x0 |V02a| | | | | | | |V00a| | [000019] 89.#48 V00 Use * Keep x19 |V02a| | | | | | | |V00i| | [000020] 94.#49 I24 Def Alloc x1 |V02a|I24a| | | | | | | | | [000227] 95.#50 I24 Use * Keep x1 |V02a|I24i| | | | | | | | | 96.#51 V20 Def Alloc x1 |V02a|V20a| | | | | | | | | [000111] 101.#52 V20 Use * Keep x1 |V02a|V20i| | | | | | | | | 102.#53 I25 Def Alloc x1 |V02a|I25a| | | | | | | | | [000024] 103.#54 I25 Use * Keep x1 |V02a|I25i| | | | | | | | | 104.#55 V04 Def Alloc x1 |V02a|V04a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 105.#56 BB4 PredBB20 |V02a|V04a| | | | | | | | | [000026] 111.#57 V04 Use Keep x1 |V02a|V04a| | | | | | | | | 112.#58 I26 Def Alloc x2 |V02a|V04a|I26a| | | | | | | | [000027] 113.#59 I26 Use * Keep x2 |V02a|V04a|I26i| | | | | | | | 114.#60 V05 Def Alloc x2 |V02a|V04a|V05a| | | | | | | | [000031] 119.#61 V05 Use Keep x2 |V02a|V04a|V05a| | | | | | | | 120.#62 I27 Def Alloc x3 |V02a|V04a|V05a|I27a| | | | | | | [000033] 123.#63 I27 Use * Keep x3 |V02a|V04a|V05a|I27i| | | | | | | 123.#64 V02 Use Keep x0 |V02a|V04a|V05a| | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 127.#65 BB5 PredBB4 |V02a|V04a|V05a| | | | | | | | [000064] 135.#66 V05 Use Keep x2 |V02a|V04a|V05a| | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 137.#67 BB6 PredBB5 |V02a|V04a|V05a| | | | | | | | [000069] 145.#68 V05 Use Keep x2 |V02a|V04a|V05a| | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 149.#69 BB8 PredBB6 |V02a|V04a|V05a| | | | | | | | [000073] 157.#70 V05 Use Keep x2 |V02a|V04a|V05a| | | | | | | | 158.#71 I28 Def Alloc x3 |V02a|V04a|V05a|I28a| | | | | | | [000074] 159.#72 I28 Use * Keep x3 |V02a|V04a|V05a|I28i| | | | | | | 160.#73 V09 Def Alloc x3 |V02a|V04a|V05a|V09a| | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 161.#74 BB7 PredBB6 |V02a|V04a|V05a| | | | | | | | [000087] 169.#75 V05 Use Keep x2 |V02a|V04a|V05a| | | | | | | | 170.#76 I29 Def Alloc x3 |V02a|V04a|V05a|I29a| | | | | | | [000088] 171.#77 I29 Use * Keep x3 |V02a|V04a|V05a|I29i| | | | | | | 172.#78 V09 Def Alloc x3 |V02a|V04a|V05a|V09a| | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 173.#79 BB9 PredBB7 |V02a|V04a|V05a|V09a| | | | | | | [000081] 183.#80 I30 Def Alloc x4 |V02a|V04a|V05a|V09a|I30a| | | | | | 183.#81 V04 Use Keep x1 |V02a|V04a|V05a|V09a|I30a| | | | | | 183.#82 V09 Use *D Keep x3 |V02a|V04a|V05a|V09i|I30a| | | | | | 183.#83 V05 Use Keep x2 |V02a|V04a|V05a| |I30a| | | | | | 183.#84 I30 Use *D Keep x4 |V02a|V04a|V05a| |I30i| | | | | | 184.#85 I31 Def Alloc x5 |V02a|V04a|V05a| | |I31a| | | | | [000083] 187.#86 I31 Use * Keep x5 |V02a|V04a|V05a| | |I31i| | | | | 187.#87 V05 Use * Keep x2 |V02a|V04a|V05i| | | | | | | | [000084] 191.#88 V04 ExpU |V02a|V04a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 191.#89 BB10 PredBB4 |V02a| |V05a| | | | | | | | [000115] 199.#90 V05 Use Keep x2 |V02a| |V05a| | | | | | | | 200.#91 I32 Def Alloc x1 |V02a|I32a|V05a| | | | | | | | [000116] 201.#92 I32 Use * Keep x1 |V02a|I32i|V05a| | | | | | | | 202.#93 V06 Def Alloc x1 |V02a|V06a|V05a| | | | | | | | [000122] 209.#94 V05 Use * Keep x2 |V02a|V06a|V05i| | | | | | | | 210.#95 I33 Def Alloc x2 |V02a|V06a|I33a| | | | | | | | [000123] 212.#96 C34 Def Alloc x3 |V02a|V06a|I33a|C34a| | | | | | | [000124] 213.#97 I33 Use * Keep x2 |V02a|V06a|I33i|C34a| | | | | | | 213.#98 C34 Use * Keep x3 |V02a|V06a| |C34i| | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 217.#99 BB12 PredBB10 |V02a|V06a| | | | | | | | | [000133] 222.#100 C35 Def Alloc x2 |V02a|V06a|C35a| | | | | | | | [000134] 223.#101 C35 Use * Keep x2 |V02a|V06a|C35i| | | | | | | | 224.#102 I36 Def Alloc x2 |V02a|V06a|I36a| | | | | | | | [000137] 227.#103 I36 Use * Keep x2 |V02a|V06a|I36i| | | | | | | | 228.#104 I37 Def Alloc x2 |V02a|V06a|I37a| | | | | | | | [000138] 229.#105 I37 Use * Keep x2 |V02a|V06a|I37i| | | | | | | | 230.#106 V13 Def Alloc x2 |V02a|V06a|V13a| | | | | | | | [000141] 235.#107 V13 Use Keep x2 |V02a|V06a|V13a| | | | | | | | [000235] 243.#108 V13 Use * Keep x2 |V02a|V06a|V13i| | | | | | | | 244.#109 I38 Def Alloc x2 |V02a|V06a|I38a| | | | | | | | [000146] 251.#110 V06 Use * Keep x1 |V02a|V06i|I38a| | | | | | | | 252.#111 I39 Def Alloc x1 |V02a|I39a|I38a| | | | | | | | [000130] 255.#112 I38 Use * Keep x2 |V02a|I39a|I38i| | | | | | | | 255.#113 I39 Use * Keep x1 |V02a|I39i| | | | | | | | | 256.#114 I40 Def Alloc x1 |V02a|I40a| | | | | | | | | [000045] 257.#115 I40 Use * Keep x1 |V02a|I40i| | | | | | | | | 258.#116 V07 Def Alloc x1 |V02a|V07a| | | | | | | | | [000150] 271.#117 V07 Use Keep x1 |V02a|V07a| | | | | | | | | 272.#118 I41 Def Alloc x2 |V02a|V07a|I41a| | | | | | | | [000151] 275.#119 I41 Use * Keep x2 |V02a|V07a|I41i| | | | | | | | 275.#120 V02 Use * Keep x0 |V02i|V07a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 279.#121 BB14 PredBB12 | |V07a| | | | | | | | | [000158] 287.#122 V07 Use Keep x1 | |V07a| | | | | | | | | 288.#123 I42 Def Alloc x0 |I42a|V07a| | | | | | | | | [000259] 289.#124 I42 Use * Keep x0 |I42i|V07a| | | | | | | | | 290.#125 V21 Def Alloc x0 |V21a|V07a| | | | | | | | | [000161] 295.#126 V21 Use Keep x0 |V21a|V07a| | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 297.#127 BB17 PredBB14 |V21a|V07a| | | | | | | | | [000167] 305.#128 V21 Use * Keep x0 |V21i|V07a| | | | | | | | | 306.#129 I43 Def Alloc x0 |I43a|V07a| | | | | | | | | [000169] 311.#130 V07 Use * Keep x1 |I43a|V07i| | | | | | | | | 311.#131 I43 Use * Keep x0 |I43i| | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 313.#132 BB15 PredBB14 | |V07a| | | | | | | | | [000173] 323.#133 V07 Use Keep x1 | |V07a| | | | | | | | | [000251] 331.#134 V07 Use Keep x1 | |V07a| | | | | | | | | 332.#135 I44 Def Alloc x0 |I44a|V07a| | | | | | | | | [000204] 335.#136 I45 Def Alloc x2 |I44a|V07a|I45a| | | | | | | | 335.#137 I46 Def Alloc x3 |I44a|V07a|I45a|I46a| | | | | | | 335.#138 I44 Use *D Keep x0 |I44i|V07a|I45a|I46a| | | | | | | 335.#139 I45 Use *D Keep x2 | |V07a|I45i|I46a| | | | | | | 335.#140 I46 Use *D Keep x3 | |V07a| |I46i| | | | | | | 336.#141 I47 Def Alloc x4 | |V07a| | |I47a| | | | | | [000206] 339.#142 I47 Use * Keep x4 | |V07a| | |I47i| | | | | | 340.#143 I48 Def Alloc x0 |I48a|V07a| | | | | | | | | [000212] 341.#144 I48 Use * Keep x0 |I48i|V07a| | | | | | | | | 342.#145 V17 Def Alloc x0 |V17a|V07a| | | | | | | | | [000211] 347.#146 V17 Use * Keep x0 |V17i|V07a| | | | | | | | | 348.#147 V19 Def Alloc x2 | |V07a|V19a| | | | | | | | [000218] 355.#148 V19 Use Keep x2 | |V07a|V19a| | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 359.#149 BB16 PredBB15 | |V07a|V19a| | | | | | | | [000322] 365.#150 x0 Fixd Keep x0 | |V07a|V19a| | | | | | | | 365.#151 V07 Use * Copy x0 |V07i|V07i|V19a| | | | | | | | 366.#152 x0 Fixd Keep x0 | | |V19a| | | | | | | | 366.#153 I49 Def Alloc x0 |I49a| |V19a| | | | | | | | [000323] 369.#154 x1 Fixd Keep x1 |I49a| |V19a| | | | | | | | 369.#155 V19 Use * Copy x1 |I49a|V19i|V19i| | | | | | | | 370.#156 x1 Fixd Keep x1 |I49a| | | | | | | | | | 370.#157 I50 Def Alloc x1 |I49a|I50a| | | | | | | | | [000186] 371.#158 x0 Fixd Keep x0 |I49a|I50a| | | | | | | | | 371.#159 I49 Use * Keep x0 |I49i|I50a| | | | | | | | | 371.#160 x1 Fixd Keep x1 | |I50a| | | | | | | | | 371.#161 I50 Use * Keep x1 | |I50i| | | | | | | | | 372.#162 Kill None [x0-xip1 lr] | | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 373.#163 BB13 PredBB12 | | | | | | | | | | | [000155] 378.#164 Kill None [x0-xip1 lr] | | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 379.#165 BB11 PredBB10 | | | | | | | | | | | [000052] 384.#166 C51 Def Alloc x0 |C51a| | | | | | | | | | [000319] 385.#167 x0 Fixd Keep x0 |C51a| | | | | | | | | | 385.#168 C51 Use * Keep x0 |C51i| | | | | | | | | | 386.#169 x0 Fixd Keep x0 | | | | | | | | | | | 386.#170 I52 Def Alloc x0 |I52a| | | | | | | | | | [000053] 387.#171 x0 Fixd Keep x0 |I52a| | | | | | | | | | 387.#172 I52 Use * Keep x0 |I52i| | | | | | | | | | 388.#173 Kill None [x0-xip1 lr] | | | | | | | | | | | 388.#174 x0 Fixd Keep x0 | | | | | | | | | | | 388.#175 I53 Def Alloc x0 |I53a| | | | | | | | | | [000054] 389.#176 I53 Use * Keep x0 |I53i| | | | | | | | | | 390.#177 V08 Def Alloc x19 | | | | | | | | |V08a| | [000320] 395.#178 x0 Fixd Keep x0 | | | | | | | | |V08a| | 395.#179 V08 Use Copy x0 |V08a| | | | | | | |V08a| | 396.#180 x0 Fixd Keep x0 | | | | | | | | |V08a| | 396.#181 I54 Def Alloc x0 |I54a| | | | | | | |V08a| | [000056] 397.#182 x0 Fixd Keep x0 |I54a| | | | | | | |V08a| | 397.#183 I54 Use * Keep x0 |I54i| | | | | | | |V08a| | 398.#184 Kill None [x0-xip1 lr] | | | | | | | | |V08a| | [000321] 403.#185 x0 Fixd Keep x0 | | | | | | | | |V08a| | 403.#186 V08 Use * Copy x0 |V08i| | | | | | | |V08i| | 404.#187 x0 Fixd Keep x0 | | | | | | | | | | | 404.#188 I55 Def Alloc x0 |I55a| | | | | | | | | | [000058] 405.#189 x0 Fixd Keep x0 |I55a| | | | | | | | | | 405.#190 I55 Use * Keep x0 |I55i| | | | | | | | | | 406.#191 Kill None [x0-xip1 lr] | | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 407.#192 BB18 PredBB9 | | | | | | | | | | | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 419.#193 BB2 PredBB1 | | | | | | | | | | | [000222] 424.#194 C56 Def Alloc x0 |C56a| | | | | | | | | | [000317] 425.#195 x0 Fixd Keep x0 |C56a| | | | | | | | | | 425.#196 C56 Use * Keep x0 |C56i| | | | | | | | | | 426.#197 x0 Fixd Keep x0 | | | | | | | | | | | 426.#198 I57 Def Alloc x0 |I57a| | | | | | | | | | [000099] 427.#199 x0 Fixd Keep x0 |I57a| | | | | | | | | | 427.#200 I57 Use * Keep x0 |I57i| | | | | | | | | | 428.#201 Kill None [x0-xip1 lr] | | | | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Register selection order: ABCDEFGHIJKLMNOPQ Total Tracked Vars: 15 Total Reg Cand Vars: 15 Total number of Intervals: 57 Total number of RefPositions: 201 Total Number of spill temps created: 0 .......... BB00 [ 100.00]: REG_ORDER = 1 BB03 [ 100.00]: COVERS = 2, REG_ORDER = 1 BB22 [ 0.00]: REG_ORDER = 1 BB20 [ 100.00]: COVERS = 3, RELATED_PREFERENCE = 1, BEST_FIT = 4 BB04 [ 800.00]: COVERS = 1, REG_ORDER = 2 BB07 [ 200.00]: RELATED_PREFERENCE = 1 BB08 [ 200.00]: COVERS = 1, REG_ORDER = 1 BB09 [ 400.00]: REG_ORDER = 2 BB10 [ 50.00]: COVERS = 1, BEST_FIT = 1, REG_ORDER = 2 BB11 [ 0.00]: REG_ORDER = 1 BB12 [ 50.00]: COVERS = 2, BEST_FIT = 2, REG_ORDER = 5 BB14 [ 50.00]: COVERS = 1, BEST_FIT = 1 BB15 [ 50.00]: COVERS = 1, BEST_FIT = 2, REG_ORDER = 4 BB17 [ 50.00]: BEST_FIT = 1 .......... Total SpillCount : 0 Weighted: 0.000000 Total CopyReg : 0 Weighted: 0.000000 Total ResolutionMovs : 0 Weighted: 0.000000 Total SplitEdges : 0 Weighted: 0.000000 .......... Total COVERS [# 4] : 12 Weighted: 1750.000000 Total RELATED_PREFERENCE [# 7] : 2 Weighted: 300.000000 Total BEST_FIT [#11] : 11 Weighted: 750.000000 Total REG_ORDER [#13] : 20 Weighted: 3350.000000 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V00(x0=>x19) BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} ===== N003. IL_OFFSET INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N005. V00(x19) N007. CNS_INT null N009. JCMP ; x19 Var=Reg end of BB01: V00=x19 BB03 [0015] [???..???) -> BB23(1),BB22(0) (cond), preds={BB01} succs={BB22,BB23} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB03: V00=x19 N013. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N015. x2 = CNS_INT(h) 0x420480 UNKNOWN N017. x0 = CALL ind _tls_get_addr; x2 * N019. V23(x0); x0 N021. V23(x0) N023. x20 = IND ; x0 * N025. V22(x20); x20 N027. V22(x20) N029. CNS_INT 0 N031. JCMP ; x20 Var=Reg end of BB03: V22=x20 V00=x19 V23=x0 BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB23: V22=x20 V00=x19 N035. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N037. V22(x20*) * N039. V22(x20); x20* Var=Reg end of BB23: V22=x20 V00=x19 BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB22: V00=x19 V23=x0 N043. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N045. V23(x0*) N047. x0 = PUTARG_REG; x0* N049. x1 = CNS_INT(h) 0x420488 tls N051. x0 = CALL ind ; x0,x1 * N053. V22(x20); x0 Var=Reg end of BB22: V22=x20 V00=x19 BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} ===== Predecessor for variable locations: BB23 Var=Reg beg of BB20: V22=x20 V00=x19 N057. IL_OFFSET INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] N059. V22(x20*) N061. STK = LEA(b+40); x20* N063. x0 = IND ; STK * N065. V02(x0); x0 N067. IL_OFFSET INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] N069. V02(x0*) N071. V02(x0) N073. CNS_INT -1 N075. x1 = ADD ; x0 N077. CNS_INT 31 N079. STK = RSH ; x1 N081. x0 = OR ; x0*,STK * N083. V02(x0); x0 N085. IL_OFFSET INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] N087. V00(x19*) N089. V03 MEM; x19* N091. IL_OFFSET INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] N093. x1 = V03 MEM * N095. V20(x1); x1 N097. V20(x1*) N099. CNS_INT -4 N101. x1 = ADD ; x1* * N103. V04(x1); x1 Var=Reg end of BB20: V04=x1 V02=x0 BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} ===== Predecessor for variable locations: BB20 Var=Reg beg of BB04: V04=x1 V02=x0 N107. IL_OFFSET INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] N109. V04(x1) N111. x2 = IND ; x1 * N113. V05(x2); x2 N115. IL_OFFSET INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] N117. V05(x2) N119. x3 = CAST ; x2 N121. V02(x0) N123. CMP ; x3,x0 N125. JCC cond=UNE Var=Reg end of BB04: V05=x2 V04=x1 V02=x0 BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB05: V05=x2 V04=x1 V02=x0 N129. IL_OFFSET INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] N131. V05(x2) N133. CNS_INT 0x8000000 N135. JTEST ; x2 Var=Reg end of BB05: V05=x2 V04=x1 V02=x0 BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} ===== Predecessor for variable locations: BB05 Var=Reg beg of BB06: V05=x2 V04=x1 V02=x0 N139. IL_OFFSET INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] N141. V05(x2) N143. CNS_INT 0x3F0000 N145. TEST ; x2 N147. JCC cond=UNE Var=Reg end of BB06: V05=x2 V04=x1 V02=x0 BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB08: V05=x2 V04=x1 V02=x0 N151. IL_OFFSET INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] N153. V05(x2) N155. CNS_INT -0x10000 N157. x3 = ADD ; x2 * N159. V09(x3); x3 Var=Reg end of BB08: V05=x2 V04=x1 V02=x0 V09=x3 BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB07: V05=x2 V04=x1 V02=x0 N163. IL_OFFSET INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] N165. V05(x2) N167. CNS_INT -0x10000 N169. x3 = AND ; x2 * N171. V09(x3); x3 Var=Reg end of BB07: V05=x2 V04=x1 V02=x0 V09=x3 BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB09: V05=x2 V04=x1 V02=x0 V09=x3 N175. IL_OFFSET INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] N177. V04(x1) N179. V09(x3*) N181. V05(x2) N183. x5 = CMPXCHG ; x1,x3*,x2 N185. V05(x2*) N187. CMP ; x5,x2* N189. JCC cond=UNE Var=Reg end of BB09: V04=x1 V02=x0 BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB10: V05=x2 V02=x0 N193. IL_OFFSET INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N195. V05(x2) N197. CNS_INT 0x3FFFFFF N199. x1 = AND ; x2 * N201. V06(x1); x1 N203. IL_OFFSET INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] N205. V05(x2*) N207. CNS_INT 0xC000000 N209. x2 = AND ; x2* N211. x3 = CNS_INT 0x8000000 N213. CMP ; x2,x3 N215. JCC cond=UEQ Var=Reg end of BB10: V02=x0 V06=x1 BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} ===== Predecessor for variable locations: BB10 Var=Reg beg of BB12: V02=x0 V06=x1 N219. IL_OFFSET INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N221. x2 = CNS_INT(h) 0x4208C8 static base addr cell N223. x2 = IND ; x2 N225. STK = LEA(b+16); x2 N227. x2 = IND ; STK * N229. V13(x2); x2 N231. IL_OFFSET INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N233. V13(x2) N235. NULLCHECK; x2 N237. IL_OFFSET INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] N239. V13(x2*) N241. CNS_INT 16 N243. x2 = ADD ; x2* N245. V06(x1*) N247. STK = CAST ; x1* N249. CNS_INT 5 N251. x1 = BFIZ ; STK N253. STK = LEA(b+(i*1)+0); x2,x1 N255. x1 = IND ; STK * N257. V07(x1); x1 N259. IL_OFFSET INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] N261. CNS_INT 0 N263. V03 MEM N265. IL_OFFSET INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N267. V07(x1) N269. STK = LEA(b+16); x1 N271. x2 = IND ; STK N273. V02(x0*) N275. CMP ; x2,x0* N277. JCC cond=UEQ Var=Reg end of BB12: V07=x1 BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} ===== Predecessor for variable locations: BB12 Var=Reg beg of BB14: V07=x1 N281. IL_OFFSET INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N283. V07(x1) N285. STK = LEA(b+24); x1 N287. x0 = IND ; STK * N289. V21(x0); x0 N291. V21(x0) N293. CNS_INT 0 N295. JCMP ; x0 Var=Reg end of BB14: V07=x1 V21=x0 BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} ===== Predecessor for variable locations: BB14 Var=Reg beg of BB17: V07=x1 V21=x0 N299. IL_OFFSET INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N301. V21(x0*) N303. CNS_INT -1 N305. x0 = ADD ; x0* N307. V07(x1*) N309. STK = LEA(b+24); x1* N311. STOREIND ; STK,x0 Var=Reg end of BB17: none BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} ===== Predecessor for variable locations: BB14 Var=Reg beg of BB15: V07=x1 N315. IL_OFFSET INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N317. V07(x1) N319. STK = LEA(b+16); x1 N321. CNS_INT 0 N323. STOREIND ; STK N325. IL_OFFSET INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N327. V07(x1) N329. CNS_INT 20 Fseq[_state] N331. x0 = ADD ; x1 N333. CNS_INT -1 N335. x4 = XADD ; x0 N337. CNS_INT -1 N339. x0 = ADD ; x4 * N341. V17(x0); x0 N343. IL_OFFSET INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N345. V17(x0*) * N347. V19(x2); x0* N349. IL_OFFSET INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N351. V19(x2) N353. CNS_INT 128 N355. CMP ; x2 N357. JCC cond=ULT Var=Reg end of BB15: V07=x1 V19=x2 BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} ===== Predecessor for variable locations: BB15 Var=Reg beg of BB16: V07=x1 V19=x2 N361. IL_OFFSET INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N363. V07(x1*) N365. x0 = PUTARG_REG; x1* N367. V19(x2*) N369. x1 = PUTARG_REG; x2* N371. CALL ; x0,x1 Var=Reg end of BB16: none BB13 [0025] [000..001) (throw), preds={BB12} succs={} ===== Predecessor for variable locations: BB12 Var=Reg beg of BB13: none N375. IL_OFFSET INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] N377. CALL Var=Reg end of BB13: none BB11 [0010] [000..001) (throw), preds={BB10} succs={} ===== Predecessor for variable locations: BB10 Var=Reg beg of BB11: none N381. IL_OFFSET INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] N383. x0 = CNS_INT(h) 0x420818 class N385. x0 = PUTARG_REG; x0 N387. x0 = CALL help; x0 * N389. V08(x19); x0 N391. IL_OFFSET INL01 @ ??? <- INLRT @ 0x000[E-] N393. V08(x19) N395. x0 = PUTARG_REG; x19 N397. CALL ; x0 N399. IL_OFFSET INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] N401. V08(x19*) N403. x0 = PUTARG_REG; x19* N405. CALL help; x0 Var=Reg end of BB11: none BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} ===== Predecessor for variable locations: BB09 Var=Reg beg of BB18: none N409. IL_OFFSET INLRT @ 0x000[E-] N411. CNS_INT 0 N413. V03 MEM N415. IL_OFFSET INLRT @ 0x006[E-] N417. RETURN Var=Reg end of BB18: none BB02 [0014] [000..001) (throw), preds={BB01} succs={} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB02: none N421. IL_OFFSET INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] N423. x0 = CNS_INT(h) '"obj"' N425. x0 = PUTARG_REG; x0 N427. CALL ; x0 Var=Reg end of BB02: none *************** Finishing PHASE Linear scan register alloc Trees after Linear scan register alloc --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i LIR BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i LIR hascall nullcheck BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i LIR BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i LIR nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} N003 (???,???) [000281] ----------- IL_OFFSET void INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR ref V00 arg0 u:1 x19 REG x19 $80 N007 ( 1, 2) [000095] -c---+----- t95 = CNS_INT ref null REG NA $VN.Null /--* t0 ref +--* t95 ref N009 ( 5, 6) [000097] -----+----- * JCMP void REG NA ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} N421 (???,???) [000282] ----------- IL_OFFSET void INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA N423 ( 2, 8) [000222] H----+----- t222 = CNS_INT(h) ref '"obj"' REG x0 $500 /--* t222 ref N425 (???,???) [000317] ----------- t317 = * PUTARG_REG ref REG x0 /--* t317 ref arg0 in x0 N427 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) REG NA $VN.Void ------------ BB03 [0015] [???..???) -> BB23(1),BB22(0) (cond), preds={BB01} succs={BB22,BB23} N013 (???,???) [000283] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N015 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN REG x2 /--* t265 long calli tgt N017 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long REG x0 /--* t266 long N019 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 x0 REG x0 N021 ( 3, 2) [000268] ----------- t268 = LCL_VAR long V23 rat1 x0 REG x0 /--* t268 long N023 ( 6, 4) [000269] #---------- t269 = * IND ref REG x20 /--* t269 ref N025 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 N027 ( 3, 2) [000272] ----------- t272 = LCL_VAR ref V22 rat0 x20 REG x20 N029 ( 1, 2) [000271] -c--------- t271 = CNS_INT long 0 REG NA /--* t272 ref +--* t271 long N031 ( 10, 7) [000274] ----------- * JCMP void REG NA ------------ BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} N043 (???,???) [000284] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N045 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 x0 (last use) REG x0 /--* t277 long N047 (???,???) [000318] ----------- t318 = * PUTARG_REG long REG x0 N049 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls REG x1 /--* t318 long arg0 in x0 +--* t275 long calli tgt N051 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref REG x0 /--* t276 ref N053 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 x20 REG x20 ------------ BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} N035 (???,???) [000285] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N037 ( 3, 2) [000279] ----------- t279 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t279 ref N039 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 ------------ BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} N057 (???,???) [000286] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N059 ( 3, 2) [000263] ----------- t263 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t263 ref N061 ( 5, 5) [000103] -c---+----- t103 = * LEA(b+40) byref REG NA /--* t103 byref N063 ( 6, 4) [000104] n---G+----- t104 = * IND int REG x0 /--* t104 int N065 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 x0 REG x0 $VN.Void N067 (???,???) [000287] ----------- IL_OFFSET void INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] REG NA N069 ( 1, 1) [000008] -----+----- t8 = LCL_VAR int V02 tmp1 u:1 x0 (last use) REG x0 N071 ( 1, 1) [000009] -----+----- t9 = LCL_VAR int V02 tmp1 u:1 x0 REG x0 N073 ( 1, 2) [000010] -c---+----- t10 = CNS_INT int -1 REG NA $41 /--* t9 int +--* t10 int N075 ( 3, 4) [000011] -----+----- t11 = * ADD int REG x1 N077 ( 1, 2) [000012] -c---+----- t12 = CNS_INT int 31 REG NA $42 /--* t11 int +--* t12 int N079 ( 5, 7) [000013] -c---+----- t13 = * RSH int REG NA /--* t8 int +--* t13 int N081 ( 7, 9) [000014] -----+----- t14 = * OR int REG x0 /--* t14 int N083 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 x0 REG x0 $VN.Void N085 (???,???) [000288] ----------- IL_OFFSET void INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] REG NA N087 ( 1, 1) [000225] -------N--- t225 = LCL_VAR ref V00 arg0 u:1 x19 (last use) REG x19 $80 /--* t225 ref N089 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $281 N091 (???,???) [000289] ----------- IL_OFFSET void INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] REG NA N093 ( 1, 1) [000020] -----+----- t20 = LCL_VAR byref V03 tmp2 x1 REG x1 $182 /--* t20 byref N095 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 x1 REG x1 $VN.Void N097 ( 1, 1) [000228] -----+----- t228 = LCL_VAR long V20 tmp19 u:1 x1 (last use) REG x1 $2c0 N099 ( 1, 2) [000110] -c---+----- t110 = CNS_INT long -4 REG NA $1c1 /--* t228 long +--* t110 long N101 ( 4, 7) [000111] -A---+----- t111 = * ADD long REG x1 $2c1 /--* t111 long N103 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 x1 REG x1 $VN.Void ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} N107 (???,???) [000290] ----------- IL_OFFSET void INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] REG NA N109 ( 1, 1) [000025] -----+----- t25 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 /--* t25 long N111 ( 3, 2) [000026] ---XG+----- t26 = * IND int REG x2 /--* t26 int N113 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 x2 REG x2 $284 N115 (???,???) [000291] ----------- IL_OFFSET void INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] REG NA N117 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t28 int N119 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int REG x3 N121 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 x0 REG x0 /--* t31 int +--* t32 int N123 ( 4, 5) [000033] -----+-N-U- * CMP void REG NA N125 ( 6, 7) [000034] -----+----- JCC void cond=UNE REG NA ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} N129 (???,???) [000292] ----------- IL_OFFSET void INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] REG NA N131 ( 1, 1) [000059] -----+----- t59 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N133 ( 1, 4) [000060] -c---+----- t60 = CNS_INT int 0x8000000 REG NA $46 /--* t59 int +--* t60 int N135 ( 7, 11) [000064] -----+----- * JTEST void REG NA ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} N139 (???,???) [000293] ----------- IL_OFFSET void INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] REG NA N141 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N143 ( 1, 2) [000066] -c---+----- t66 = CNS_INT int 0x3F0000 REG NA $47 /--* t65 int +--* t66 int N145 ( 5, 7) [000069] -----+-N--- * TEST void REG NA N147 ( 7, 9) [000070] -----+----- JCC void cond=UNE REG NA ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} N163 (???,???) [000294] ----------- IL_OFFSET void INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] REG NA N165 ( 1, 1) [000085] -----+----- t85 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N167 ( 1, 2) [000086] -c---+----- t86 = CNS_INT int -0x10000 REG NA $48 /--* t85 int +--* t86 int N169 ( 3, 4) [000087] -----+----- t87 = * AND int REG x3 /--* t87 int N171 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 x3 REG x3 $VN.Void ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} N151 (???,???) [000295] ----------- IL_OFFSET void INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] REG NA N153 ( 1, 1) [000071] -----+----- t71 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N155 ( 1, 2) [000072] -c---+----- t72 = CNS_INT int -0x10000 REG NA $48 /--* t71 int +--* t72 int N157 ( 3, 4) [000073] -----+----- t73 = * ADD int REG x3 /--* t73 int N159 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 x3 REG x3 $VN.Void ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} N175 (???,???) [000296] ----------- IL_OFFSET void INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] REG NA N177 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 N179 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 x3 (last use) REG x3 $340 N181 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t78 long +--* t76 int +--* t80 int N183 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int REG x5 $11a N185 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 /--* t81 int +--* t82 int N187 (255, 10) [000083] -A-XG+-N-U- * CMP void REG NA N189 (255, 12) [000084] -A-XG+----- JCC void cond=UNE REG NA ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} N193 (???,???) [000297] ----------- IL_OFFSET void INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA N195 ( 1, 1) [000035] -----+----- t35 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N197 ( 1, 4) [000114] -c---+----- t114 = CNS_INT int 0x3FFFFFF REG NA $49 /--* t35 int +--* t114 int N199 ( 3, 6) [000115] -----+----- t115 = * AND int REG x1 /--* t115 int N201 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 x1 REG x1 $VN.Void N203 (???,???) [000298] ----------- IL_OFFSET void INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA N205 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 N207 ( 1, 4) [000121] -c---+----- t121 = CNS_INT int 0xC000000 REG NA $4a /--* t117 int +--* t121 int N209 ( 3, 6) [000122] -----+----- t122 = * AND int REG x2 N211 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 REG x3 $46 /--* t122 int +--* t123 int N213 ( 5, 11) [000124] -----+-N--- * CMP void REG NA N215 ( 7, 13) [000041] -----+----- JCC void cond=UEQ REG NA ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} N381 (???,???) [000299] ----------- IL_OFFSET void INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] REG NA N383 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class REG x0 $147 /--* t52 long N385 (???,???) [000319] ----------- t319 = * PUTARG_REG long REG x0 /--* t319 long arg0 in x0 N387 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST REG x0 $298 /--* t53 ref N389 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 x19 REG x19 $VN.Void N391 (???,???) [000300] ----------- IL_OFFSET void INL01 @ ??? <- INLRT @ 0x000[E-] REG NA N393 ( 3, 2) [000055] -----+----- t55 = LCL_VAR ref V08 tmp7 u:2 x19 REG x19 $298 /--* t55 ref N395 (???,???) [000320] ----------- t320 = * PUTARG_REG ref REG x0 /--* t320 ref this in x0 N397 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this REG NA $VN.Void N399 (???,???) [000301] ----------- IL_OFFSET void INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] REG NA N401 ( 3, 2) [000057] -----+----- t57 = LCL_VAR ref V08 tmp7 u:2 x19 (last use) REG x19 $298 /--* t57 ref N403 (???,???) [000321] ----------- t321 = * PUTARG_REG ref REG x0 /--* t321 ref arg0 in x0 N405 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW REG NA $29a ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} N219 (???,???) [000302] ----------- IL_OFFSET void INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N221 ( 2, 8) [000133] H----+----- t133 = CNS_INT(h) long 0x4208C8 static base addr cell REG x2 $142 /--* t133 long N223 ( 5, 10) [000134] #----+----- t134 = * IND long REG x2 $380 /--* t134 long N225 ( 7, 13) [000136] -c---+----- t136 = * LEA(b+16) long REG NA /--* t136 long N227 ( 8, 12) [000137] ---XG+----- t137 = * IND ref REG x2 /--* t137 ref N229 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 x2 REG x2 $289 N231 (???,???) [000303] ----------- IL_OFFSET void INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N233 ( 1, 1) [000140] -----+----- t140 = LCL_VAR ref V13 tmp12 u:2 x2 REG x2 /--* t140 ref N235 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte REG NA N237 (???,???) [000304] ----------- IL_OFFSET void INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N239 ( 1, 1) [000139] -----+----- t139 = LCL_VAR ref V13 tmp12 u:2 x2 (last use) REG x2 N241 ( 1, 2) [000234] -c---+----- t234 = CNS_INT long 16 REG NA $1c3 /--* t139 ref +--* t234 long N243 ( 2, 5) [000235] -----+-N--- t235 = * ADD byref REG x2 N245 ( 3, 2) [000126] -----+----- t126 = LCL_VAR int V06 tmp5 u:1 x1 (last use) REG x1 /--* t126 int N247 ( 4, 4) [000144] -c---+----- t144 = * CAST long <- int REG NA N249 ( 1, 2) [000145] -c---+----- t145 = CNS_INT long 5 REG NA $1c4 /--* t144 long +--* t145 long N251 ( 6, 7) [000146] -----+----- t146 = * BFIZ long REG x1 /--* t235 byref +--* t146 long N253 ( 9, 13) [000147] -c---+----- t147 = * LEA(b+(i*1)+0) byref REG NA /--* t147 byref N255 ( 11, 14) [000130] ---XG+----- t130 = * IND ref REG x1 /--* t130 ref N257 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 x1 REG x1 N259 (???,???) [000305] ----------- IL_OFFSET void INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] REG NA N261 ( 1, 2) [000047] -c---+----- t47 = CNS_INT long 0 REG NA $1c2 /--* t47 long N263 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void N265 (???,???) [000306] ----------- IL_OFFSET void INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N267 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t49 ref N269 ( 3, 4) [000238] -c---+----- t238 = * LEA(b+16) byref REG NA /--* t238 byref N271 ( 4, 3) [000150] ---XG+----- t150 = * IND int REG x2 N273 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 x0 (last use) REG x0 /--* t150 int +--* t50 int N275 ( 6, 5) [000151] ---XG+-N--- * CMP void REG NA N277 ( 8, 7) [000152] ---XG+----- JCC void cond=UEQ REG NA ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} N375 (???,???) [000307] ----------- IL_OFFSET void INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N377 ( 14, 2) [000155] --CXG+----- CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() REG NA $VN.Void ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} N281 (???,???) [000308] ----------- IL_OFFSET void INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N283 ( 1, 1) [000153] ----------- t153 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t153 ref N285 ( 3, 4) [000240] -c--------- t240 = * LEA(b+24) byref REG NA /--* t240 byref N287 ( 4, 3) [000158] n---GO----- t158 = * IND int REG x0 /--* t158 int N289 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 x0 REG x0 N291 ( 3, 2) [000260] ----------- t260 = LCL_VAR int V21 cse0 u:1 x0 REG x0 N293 ( 1, 2) [000159] -c--------- t159 = CNS_INT int 0 REG NA $40 /--* t260 int +--* t159 int N295 ( 15, 13) [000161] -A--GO----- * JCMP void REG NA ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} N315 (???,???) [000309] ----------- IL_OFFSET void INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N317 ( 1, 1) [000170] ----------- t170 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t170 ref N319 ( 3, 4) [000246] -c--------- t246 = * LEA(b+16) byref REG NA N321 ( 1, 2) [000171] -c--------- t171 = CNS_INT int 0 REG NA $40 /--* t246 byref +--* t171 int N323 ( 6, 6) [000173] nA--GO----- * STOREIND int REG NA N325 (???,???) [000310] ----------- IL_OFFSET void INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N327 ( 1, 1) [000249] -----+----- t249 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 N329 ( 1, 2) [000250] -c---+----- t250 = CNS_INT long 20 Fseq[_state] REG NA $1c6 /--* t249 ref +--* t250 long N331 ( 3, 4) [000251] -----+----- t251 = * ADD byref REG x0 N333 ( 1, 2) [000203] -c---+----- t203 = CNS_INT int -1 REG NA $41 /--* t251 byref +--* t203 int N335 ( 5, 7) [000204] -A-XG+----- t204 = * XADD int REG x4 N337 ( 1, 2) [000205] -c---+----- t205 = CNS_INT int -1 REG NA $41 /--* t204 int +--* t205 int N339 ( 7, 10) [000206] -A-XG+----- t206 = * ADD int REG x0 /--* t206 int N341 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 x0 REG x0 N343 (???,???) [000311] ----------- IL_OFFSET void INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N345 ( 1, 1) [000209] -----+----- t209 = LCL_VAR int V17 tmp16 u:1 x0 (last use) REG x0 $13a /--* t209 int N347 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 x2 REG x2 $VN.Void N349 (???,???) [000312] ----------- IL_OFFSET void INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N351 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 x2 REG x2 $13a N353 ( 1, 2) [000217] -c---+----- t217 = CNS_INT int 128 REG NA $4d /--* t216 int +--* t217 int N355 ( 3, 4) [000218] -----+-N-U- * CMP void REG NA N357 ( 5, 6) [000183] -----+----- JCC void cond=ULT REG NA ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} N361 (???,???) [000313] ----------- IL_OFFSET void INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N363 ( 1, 1) [000184] -----+----- t184 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t184 ref N365 (???,???) [000322] ----------- t322 = * PUTARG_REG ref REG x0 N367 ( 3, 2) [000185] -----+----- t185 = LCL_VAR int V19 tmp18 u:1 x2 (last use) REG x2 $13a /--* t185 int N369 (???,???) [000323] ----------- t323 = * PUTARG_REG int REG x1 /--* t322 ref this in x0 +--* t323 int arg1 in x1 N371 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this REG NA $VN.Void ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} N299 (???,???) [000314] ----------- IL_OFFSET void INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N301 ( 3, 2) [000262] ----------- t262 = LCL_VAR int V21 cse0 u:1 x0 (last use) REG x0 N303 ( 1, 2) [000166] -c--------- t166 = CNS_INT int -1 REG NA $41 /--* t262 int +--* t166 int N305 ( 5, 5) [000167] ----G------ t167 = * ADD int REG x0 N307 ( 1, 1) [000162] ----------- t162 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t162 ref N309 ( 3, 4) [000242] -c--------- t242 = * LEA(b+24) byref REG NA /--* t242 byref +--* t167 int N311 ( 10, 9) [000169] nA--GO----- * STOREIND int REG NA ------------ BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} N409 (???,???) [000315] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N411 ( 1, 2) [000092] -c---+----- t92 = CNS_INT byref 0 REG NA $VN.Null /--* t92 byref N413 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void N415 (???,???) [000316] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA N417 ( 0, 0) [000002] -----+----- RETURN void REG NA $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Optimize layout *************** In fgDoReversePostOrderLayout() Initial BasicBlocks --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i LIR BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i LIR hascall nullcheck BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i LIR BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i LIR nullcheck BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** In fgMoveHotJumps() Initial BasicBlocks --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i LIR BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i LIR hascall nullcheck BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i LIR BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i LIR nullcheck BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i LIR BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** In fgMoveColdBlocks() Initial BasicBlocks --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i LIR BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i LIR hascall nullcheck BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i LIR BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i LIR nullcheck BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i LIR BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** In fgSearchImprovedLayout() Initial BasicBlocks --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i LIR BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i LIR hascall nullcheck BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i LIR BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i LIR nullcheck BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i LIR BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj --------------------------------------------------------------------------------------------------------------------------------------------------------------------- Initial layout cost: 1625.000000 Running greedy 3-opt pass. No changes made. *************** Finishing PHASE Optimize layout Trees after Optimize layout --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB03(0.5),BB02(0.5) ( cond ) i LIR BB03 [0015] 1 BB01 1 [???..???)-> BB23(1),BB22(0) ( cond ) i LIR hascall nullcheck BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB12(1),BB11(0) ( cond ) i LIR BB12 [0011] 1 BB10 0.50 [000..001)-> BB14(0.5),BB13(0.5) ( cond ) i LIR nullcheck BB14 [0026] 1 BB12 0.50 [000..001)-> BB17(0.5),BB15(0.5) ( cond ) i LIR BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} N003 (???,???) [000281] ----------- IL_OFFSET void INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR ref V00 arg0 u:1 x19 REG x19 $80 N007 ( 1, 2) [000095] -c---+----- t95 = CNS_INT ref null REG NA $VN.Null /--* t0 ref +--* t95 ref N009 ( 5, 6) [000097] -----+----- * JCMP void REG NA ------------ BB03 [0015] [???..???) -> BB23(1),BB22(0) (cond), preds={BB01} succs={BB22,BB23} N013 (???,???) [000283] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N015 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN REG x2 /--* t265 long calli tgt N017 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long REG x0 /--* t266 long N019 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 x0 REG x0 N021 ( 3, 2) [000268] ----------- t268 = LCL_VAR long V23 rat1 x0 REG x0 /--* t268 long N023 ( 6, 4) [000269] #---------- t269 = * IND ref REG x20 /--* t269 ref N025 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 N027 ( 3, 2) [000272] ----------- t272 = LCL_VAR ref V22 rat0 x20 REG x20 N029 ( 1, 2) [000271] -c--------- t271 = CNS_INT long 0 REG NA /--* t272 ref +--* t271 long N031 ( 10, 7) [000274] ----------- * JCMP void REG NA ------------ BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} N035 (???,???) [000285] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N037 ( 3, 2) [000279] ----------- t279 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t279 ref N039 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 ------------ BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} N057 (???,???) [000286] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N059 ( 3, 2) [000263] ----------- t263 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t263 ref N061 ( 5, 5) [000103] -c---+----- t103 = * LEA(b+40) byref REG NA /--* t103 byref N063 ( 6, 4) [000104] n---G+----- t104 = * IND int REG x0 /--* t104 int N065 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 x0 REG x0 $VN.Void N067 (???,???) [000287] ----------- IL_OFFSET void INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] REG NA N069 ( 1, 1) [000008] -----+----- t8 = LCL_VAR int V02 tmp1 u:1 x0 (last use) REG x0 N071 ( 1, 1) [000009] -----+----- t9 = LCL_VAR int V02 tmp1 u:1 x0 REG x0 N073 ( 1, 2) [000010] -c---+----- t10 = CNS_INT int -1 REG NA $41 /--* t9 int +--* t10 int N075 ( 3, 4) [000011] -----+----- t11 = * ADD int REG x1 N077 ( 1, 2) [000012] -c---+----- t12 = CNS_INT int 31 REG NA $42 /--* t11 int +--* t12 int N079 ( 5, 7) [000013] -c---+----- t13 = * RSH int REG NA /--* t8 int +--* t13 int N081 ( 7, 9) [000014] -----+----- t14 = * OR int REG x0 /--* t14 int N083 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 x0 REG x0 $VN.Void N085 (???,???) [000288] ----------- IL_OFFSET void INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] REG NA N087 ( 1, 1) [000225] -------N--- t225 = LCL_VAR ref V00 arg0 u:1 x19 (last use) REG x19 $80 /--* t225 ref N089 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $281 N091 (???,???) [000289] ----------- IL_OFFSET void INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] REG NA N093 ( 1, 1) [000020] -----+----- t20 = LCL_VAR byref V03 tmp2 x1 REG x1 $182 /--* t20 byref N095 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 x1 REG x1 $VN.Void N097 ( 1, 1) [000228] -----+----- t228 = LCL_VAR long V20 tmp19 u:1 x1 (last use) REG x1 $2c0 N099 ( 1, 2) [000110] -c---+----- t110 = CNS_INT long -4 REG NA $1c1 /--* t228 long +--* t110 long N101 ( 4, 7) [000111] -A---+----- t111 = * ADD long REG x1 $2c1 /--* t111 long N103 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 x1 REG x1 $VN.Void ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} N107 (???,???) [000290] ----------- IL_OFFSET void INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] REG NA N109 ( 1, 1) [000025] -----+----- t25 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 /--* t25 long N111 ( 3, 2) [000026] ---XG+----- t26 = * IND int REG x2 /--* t26 int N113 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 x2 REG x2 $284 N115 (???,???) [000291] ----------- IL_OFFSET void INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] REG NA N117 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t28 int N119 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int REG x3 N121 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 x0 REG x0 /--* t31 int +--* t32 int N123 ( 4, 5) [000033] -----+-N-U- * CMP void REG NA N125 ( 6, 7) [000034] -----+----- JCC void cond=UNE REG NA ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} N129 (???,???) [000292] ----------- IL_OFFSET void INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] REG NA N131 ( 1, 1) [000059] -----+----- t59 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N133 ( 1, 4) [000060] -c---+----- t60 = CNS_INT int 0x8000000 REG NA $46 /--* t59 int +--* t60 int N135 ( 7, 11) [000064] -----+----- * JTEST void REG NA ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} N139 (???,???) [000293] ----------- IL_OFFSET void INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] REG NA N141 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N143 ( 1, 2) [000066] -c---+----- t66 = CNS_INT int 0x3F0000 REG NA $47 /--* t65 int +--* t66 int N145 ( 5, 7) [000069] -----+-N--- * TEST void REG NA N147 ( 7, 9) [000070] -----+----- JCC void cond=UNE REG NA ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} N163 (???,???) [000294] ----------- IL_OFFSET void INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] REG NA N165 ( 1, 1) [000085] -----+----- t85 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N167 ( 1, 2) [000086] -c---+----- t86 = CNS_INT int -0x10000 REG NA $48 /--* t85 int +--* t86 int N169 ( 3, 4) [000087] -----+----- t87 = * AND int REG x3 /--* t87 int N171 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 x3 REG x3 $VN.Void ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} N151 (???,???) [000295] ----------- IL_OFFSET void INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] REG NA N153 ( 1, 1) [000071] -----+----- t71 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N155 ( 1, 2) [000072] -c---+----- t72 = CNS_INT int -0x10000 REG NA $48 /--* t71 int +--* t72 int N157 ( 3, 4) [000073] -----+----- t73 = * ADD int REG x3 /--* t73 int N159 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 x3 REG x3 $VN.Void ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} N175 (???,???) [000296] ----------- IL_OFFSET void INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] REG NA N177 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 N179 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 x3 (last use) REG x3 $340 N181 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t78 long +--* t76 int +--* t80 int N183 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int REG x5 $11a N185 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 /--* t81 int +--* t82 int N187 (255, 10) [000083] -A-XG+-N-U- * CMP void REG NA N189 (255, 12) [000084] -A-XG+----- JCC void cond=UNE REG NA ------------ BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} N409 (???,???) [000315] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N411 ( 1, 2) [000092] -c---+----- t92 = CNS_INT byref 0 REG NA $VN.Null /--* t92 byref N413 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void N415 (???,???) [000316] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA N417 ( 0, 0) [000002] -----+----- RETURN void REG NA $VN.Void ------------ BB10 [0009] [000..001) -> BB12(1),BB11(0) (cond), preds={BB04,BB05} succs={BB11,BB12} N193 (???,???) [000297] ----------- IL_OFFSET void INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA N195 ( 1, 1) [000035] -----+----- t35 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N197 ( 1, 4) [000114] -c---+----- t114 = CNS_INT int 0x3FFFFFF REG NA $49 /--* t35 int +--* t114 int N199 ( 3, 6) [000115] -----+----- t115 = * AND int REG x1 /--* t115 int N201 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 x1 REG x1 $VN.Void N203 (???,???) [000298] ----------- IL_OFFSET void INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA N205 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 N207 ( 1, 4) [000121] -c---+----- t121 = CNS_INT int 0xC000000 REG NA $4a /--* t117 int +--* t121 int N209 ( 3, 6) [000122] -----+----- t122 = * AND int REG x2 N211 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 REG x3 $46 /--* t122 int +--* t123 int N213 ( 5, 11) [000124] -----+-N--- * CMP void REG NA N215 ( 7, 13) [000041] -----+----- JCC void cond=UEQ REG NA ------------ BB12 [0011] [000..001) -> BB14(0.5),BB13(0.5) (cond), preds={BB10} succs={BB13,BB14} N219 (???,???) [000302] ----------- IL_OFFSET void INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N221 ( 2, 8) [000133] H----+----- t133 = CNS_INT(h) long 0x4208C8 static base addr cell REG x2 $142 /--* t133 long N223 ( 5, 10) [000134] #----+----- t134 = * IND long REG x2 $380 /--* t134 long N225 ( 7, 13) [000136] -c---+----- t136 = * LEA(b+16) long REG NA /--* t136 long N227 ( 8, 12) [000137] ---XG+----- t137 = * IND ref REG x2 /--* t137 ref N229 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 x2 REG x2 $289 N231 (???,???) [000303] ----------- IL_OFFSET void INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N233 ( 1, 1) [000140] -----+----- t140 = LCL_VAR ref V13 tmp12 u:2 x2 REG x2 /--* t140 ref N235 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte REG NA N237 (???,???) [000304] ----------- IL_OFFSET void INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N239 ( 1, 1) [000139] -----+----- t139 = LCL_VAR ref V13 tmp12 u:2 x2 (last use) REG x2 N241 ( 1, 2) [000234] -c---+----- t234 = CNS_INT long 16 REG NA $1c3 /--* t139 ref +--* t234 long N243 ( 2, 5) [000235] -----+-N--- t235 = * ADD byref REG x2 N245 ( 3, 2) [000126] -----+----- t126 = LCL_VAR int V06 tmp5 u:1 x1 (last use) REG x1 /--* t126 int N247 ( 4, 4) [000144] -c---+----- t144 = * CAST long <- int REG NA N249 ( 1, 2) [000145] -c---+----- t145 = CNS_INT long 5 REG NA $1c4 /--* t144 long +--* t145 long N251 ( 6, 7) [000146] -----+----- t146 = * BFIZ long REG x1 /--* t235 byref +--* t146 long N253 ( 9, 13) [000147] -c---+----- t147 = * LEA(b+(i*1)+0) byref REG NA /--* t147 byref N255 ( 11, 14) [000130] ---XG+----- t130 = * IND ref REG x1 /--* t130 ref N257 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 x1 REG x1 N259 (???,???) [000305] ----------- IL_OFFSET void INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] REG NA N261 ( 1, 2) [000047] -c---+----- t47 = CNS_INT long 0 REG NA $1c2 /--* t47 long N263 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void N265 (???,???) [000306] ----------- IL_OFFSET void INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N267 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t49 ref N269 ( 3, 4) [000238] -c---+----- t238 = * LEA(b+16) byref REG NA /--* t238 byref N271 ( 4, 3) [000150] ---XG+----- t150 = * IND int REG x2 N273 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 x0 (last use) REG x0 /--* t150 int +--* t50 int N275 ( 6, 5) [000151] ---XG+-N--- * CMP void REG NA N277 ( 8, 7) [000152] ---XG+----- JCC void cond=UEQ REG NA ------------ BB14 [0026] [000..001) -> BB17(0.5),BB15(0.5) (cond), preds={BB12} succs={BB15,BB17} N281 (???,???) [000308] ----------- IL_OFFSET void INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N283 ( 1, 1) [000153] ----------- t153 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t153 ref N285 ( 3, 4) [000240] -c--------- t240 = * LEA(b+24) byref REG NA /--* t240 byref N287 ( 4, 3) [000158] n---GO----- t158 = * IND int REG x0 /--* t158 int N289 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 x0 REG x0 N291 ( 3, 2) [000260] ----------- t260 = LCL_VAR int V21 cse0 u:1 x0 REG x0 N293 ( 1, 2) [000159] -c--------- t159 = CNS_INT int 0 REG NA $40 /--* t260 int +--* t159 int N295 ( 15, 13) [000161] -A--GO----- * JCMP void REG NA ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} N299 (???,???) [000314] ----------- IL_OFFSET void INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N301 ( 3, 2) [000262] ----------- t262 = LCL_VAR int V21 cse0 u:1 x0 (last use) REG x0 N303 ( 1, 2) [000166] -c--------- t166 = CNS_INT int -1 REG NA $41 /--* t262 int +--* t166 int N305 ( 5, 5) [000167] ----G------ t167 = * ADD int REG x0 N307 ( 1, 1) [000162] ----------- t162 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t162 ref N309 ( 3, 4) [000242] -c--------- t242 = * LEA(b+24) byref REG NA /--* t242 byref +--* t167 int N311 ( 10, 9) [000169] nA--GO----- * STOREIND int REG NA ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} N315 (???,???) [000309] ----------- IL_OFFSET void INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N317 ( 1, 1) [000170] ----------- t170 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t170 ref N319 ( 3, 4) [000246] -c--------- t246 = * LEA(b+16) byref REG NA N321 ( 1, 2) [000171] -c--------- t171 = CNS_INT int 0 REG NA $40 /--* t246 byref +--* t171 int N323 ( 6, 6) [000173] nA--GO----- * STOREIND int REG NA N325 (???,???) [000310] ----------- IL_OFFSET void INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N327 ( 1, 1) [000249] -----+----- t249 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 N329 ( 1, 2) [000250] -c---+----- t250 = CNS_INT long 20 Fseq[_state] REG NA $1c6 /--* t249 ref +--* t250 long N331 ( 3, 4) [000251] -----+----- t251 = * ADD byref REG x0 N333 ( 1, 2) [000203] -c---+----- t203 = CNS_INT int -1 REG NA $41 /--* t251 byref +--* t203 int N335 ( 5, 7) [000204] -A-XG+----- t204 = * XADD int REG x4 N337 ( 1, 2) [000205] -c---+----- t205 = CNS_INT int -1 REG NA $41 /--* t204 int +--* t205 int N339 ( 7, 10) [000206] -A-XG+----- t206 = * ADD int REG x0 /--* t206 int N341 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 x0 REG x0 N343 (???,???) [000311] ----------- IL_OFFSET void INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N345 ( 1, 1) [000209] -----+----- t209 = LCL_VAR int V17 tmp16 u:1 x0 (last use) REG x0 $13a /--* t209 int N347 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 x2 REG x2 $VN.Void N349 (???,???) [000312] ----------- IL_OFFSET void INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N351 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 x2 REG x2 $13a N353 ( 1, 2) [000217] -c---+----- t217 = CNS_INT int 128 REG NA $4d /--* t216 int +--* t217 int N355 ( 3, 4) [000218] -----+-N-U- * CMP void REG NA N357 ( 5, 6) [000183] -----+----- JCC void cond=ULT REG NA ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} N361 (???,???) [000313] ----------- IL_OFFSET void INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N363 ( 1, 1) [000184] -----+----- t184 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t184 ref N365 (???,???) [000322] ----------- t322 = * PUTARG_REG ref REG x0 N367 ( 3, 2) [000185] -----+----- t185 = LCL_VAR int V19 tmp18 u:1 x2 (last use) REG x2 $13a /--* t185 int N369 (???,???) [000323] ----------- t323 = * PUTARG_REG int REG x1 /--* t322 ref this in x0 +--* t323 int arg1 in x1 N371 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this REG NA $VN.Void ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} N375 (???,???) [000307] ----------- IL_OFFSET void INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N377 ( 14, 2) [000155] --CXG+----- CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() REG NA $VN.Void ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} N421 (???,???) [000282] ----------- IL_OFFSET void INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA N423 ( 2, 8) [000222] H----+----- t222 = CNS_INT(h) ref '"obj"' REG x0 $500 /--* t222 ref N425 (???,???) [000317] ----------- t317 = * PUTARG_REG ref REG x0 /--* t317 ref arg0 in x0 N427 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) REG NA $VN.Void ------------ BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} N043 (???,???) [000284] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N045 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 x0 (last use) REG x0 /--* t277 long N047 (???,???) [000318] ----------- t318 = * PUTARG_REG long REG x0 N049 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls REG x1 /--* t318 long arg0 in x0 +--* t275 long calli tgt N051 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref REG x0 /--* t276 ref N053 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 x20 REG x20 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} N381 (???,???) [000299] ----------- IL_OFFSET void INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] REG NA N383 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class REG x0 $147 /--* t52 long N385 (???,???) [000319] ----------- t319 = * PUTARG_REG long REG x0 /--* t319 long arg0 in x0 N387 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST REG x0 $298 /--* t53 ref N389 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 x19 REG x19 $VN.Void N391 (???,???) [000300] ----------- IL_OFFSET void INL01 @ ??? <- INLRT @ 0x000[E-] REG NA N393 ( 3, 2) [000055] -----+----- t55 = LCL_VAR ref V08 tmp7 u:2 x19 REG x19 $298 /--* t55 ref N395 (???,???) [000320] ----------- t320 = * PUTARG_REG ref REG x0 /--* t320 ref this in x0 N397 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this REG NA $VN.Void N399 (???,???) [000301] ----------- IL_OFFSET void INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] REG NA N401 ( 3, 2) [000057] -----+----- t57 = LCL_VAR ref V08 tmp7 u:2 x19 (last use) REG x19 $298 /--* t57 ref N403 (???,???) [000321] ----------- t321 = * PUTARG_REG ref REG x0 /--* t321 ref arg0 in x0 N405 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW REG NA $29a ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Optimize post-layout *************** Finishing PHASE Optimize post-layout Trees after Optimize post-layout --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB02(0.5),BB03(0.5) ( cond ) i LIR BB03 [0015] 1 BB01 1 [???..???)-> BB22(0),BB23(1) ( cond ) i LIR hascall nullcheck BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB11(0),BB12(1) ( cond ) i LIR BB12 [0011] 1 BB10 0.50 [000..001)-> BB13(0.5),BB14(0.5) ( cond ) i LIR nullcheck BB14 [0026] 1 BB12 0.50 [000..001)-> BB15(0.5),BB17(0.5) ( cond ) i LIR BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB02(0.5),BB03(0.5) (cond), preds={} succs={BB03,BB02} N003 (???,???) [000281] ----------- IL_OFFSET void INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR ref V00 arg0 u:1 x19 REG x19 $80 N007 ( 1, 2) [000095] -c---+----- t95 = CNS_INT ref null REG NA $VN.Null /--* t0 ref +--* t95 ref N009 ( 5, 6) [000097] -----+----- * JCMP void REG NA ------------ BB03 [0015] [???..???) -> BB22(0),BB23(1) (cond), preds={BB01} succs={BB23,BB22} N013 (???,???) [000283] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N015 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN REG x2 /--* t265 long calli tgt N017 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long REG x0 /--* t266 long N019 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 x0 REG x0 N021 ( 3, 2) [000268] ----------- t268 = LCL_VAR long V23 rat1 x0 REG x0 /--* t268 long N023 ( 6, 4) [000269] #---------- t269 = * IND ref REG x20 /--* t269 ref N025 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 N027 ( 3, 2) [000272] ----------- t272 = LCL_VAR ref V22 rat0 x20 REG x20 N029 ( 1, 2) [000271] -c--------- t271 = CNS_INT long 0 REG NA /--* t272 ref +--* t271 long N031 ( 10, 7) [000274] ----------- * JCMP void REG NA ------------ BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} N035 (???,???) [000285] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N037 ( 3, 2) [000279] ----------- t279 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t279 ref N039 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 ------------ BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} N057 (???,???) [000286] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N059 ( 3, 2) [000263] ----------- t263 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t263 ref N061 ( 5, 5) [000103] -c---+----- t103 = * LEA(b+40) byref REG NA /--* t103 byref N063 ( 6, 4) [000104] n---G+----- t104 = * IND int REG x0 /--* t104 int N065 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 x0 REG x0 $VN.Void N067 (???,???) [000287] ----------- IL_OFFSET void INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] REG NA N069 ( 1, 1) [000008] -----+----- t8 = LCL_VAR int V02 tmp1 u:1 x0 (last use) REG x0 N071 ( 1, 1) [000009] -----+----- t9 = LCL_VAR int V02 tmp1 u:1 x0 REG x0 N073 ( 1, 2) [000010] -c---+----- t10 = CNS_INT int -1 REG NA $41 /--* t9 int +--* t10 int N075 ( 3, 4) [000011] -----+----- t11 = * ADD int REG x1 N077 ( 1, 2) [000012] -c---+----- t12 = CNS_INT int 31 REG NA $42 /--* t11 int +--* t12 int N079 ( 5, 7) [000013] -c---+----- t13 = * RSH int REG NA /--* t8 int +--* t13 int N081 ( 7, 9) [000014] -----+----- t14 = * OR int REG x0 /--* t14 int N083 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 x0 REG x0 $VN.Void N085 (???,???) [000288] ----------- IL_OFFSET void INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] REG NA N087 ( 1, 1) [000225] -------N--- t225 = LCL_VAR ref V00 arg0 u:1 x19 (last use) REG x19 $80 /--* t225 ref N089 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $281 N091 (???,???) [000289] ----------- IL_OFFSET void INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] REG NA N093 ( 1, 1) [000020] -----+----- t20 = LCL_VAR byref V03 tmp2 x1 REG x1 $182 /--* t20 byref N095 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 x1 REG x1 $VN.Void N097 ( 1, 1) [000228] -----+----- t228 = LCL_VAR long V20 tmp19 u:1 x1 (last use) REG x1 $2c0 N099 ( 1, 2) [000110] -c---+----- t110 = CNS_INT long -4 REG NA $1c1 /--* t228 long +--* t110 long N101 ( 4, 7) [000111] -A---+----- t111 = * ADD long REG x1 $2c1 /--* t111 long N103 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 x1 REG x1 $VN.Void ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} N107 (???,???) [000290] ----------- IL_OFFSET void INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] REG NA N109 ( 1, 1) [000025] -----+----- t25 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 /--* t25 long N111 ( 3, 2) [000026] ---XG+----- t26 = * IND int REG x2 /--* t26 int N113 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 x2 REG x2 $284 N115 (???,???) [000291] ----------- IL_OFFSET void INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] REG NA N117 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t28 int N119 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int REG x3 N121 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 x0 REG x0 /--* t31 int +--* t32 int N123 ( 4, 5) [000033] -----+-N-U- * CMP void REG NA N125 ( 6, 7) [000034] -----+----- JCC void cond=UNE REG NA ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} N129 (???,???) [000292] ----------- IL_OFFSET void INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] REG NA N131 ( 1, 1) [000059] -----+----- t59 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N133 ( 1, 4) [000060] -c---+----- t60 = CNS_INT int 0x8000000 REG NA $46 /--* t59 int +--* t60 int N135 ( 7, 11) [000064] -----+----- * JTEST void REG NA ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} N139 (???,???) [000293] ----------- IL_OFFSET void INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] REG NA N141 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N143 ( 1, 2) [000066] -c---+----- t66 = CNS_INT int 0x3F0000 REG NA $47 /--* t65 int +--* t66 int N145 ( 5, 7) [000069] -----+-N--- * TEST void REG NA N147 ( 7, 9) [000070] -----+----- JCC void cond=UNE REG NA ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} N163 (???,???) [000294] ----------- IL_OFFSET void INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] REG NA N165 ( 1, 1) [000085] -----+----- t85 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N167 ( 1, 2) [000086] -c---+----- t86 = CNS_INT int -0x10000 REG NA $48 /--* t85 int +--* t86 int N169 ( 3, 4) [000087] -----+----- t87 = * AND int REG x3 /--* t87 int N171 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 x3 REG x3 $VN.Void ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} N151 (???,???) [000295] ----------- IL_OFFSET void INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] REG NA N153 ( 1, 1) [000071] -----+----- t71 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N155 ( 1, 2) [000072] -c---+----- t72 = CNS_INT int -0x10000 REG NA $48 /--* t71 int +--* t72 int N157 ( 3, 4) [000073] -----+----- t73 = * ADD int REG x3 /--* t73 int N159 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 x3 REG x3 $VN.Void ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} N175 (???,???) [000296] ----------- IL_OFFSET void INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] REG NA N177 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 N179 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 x3 (last use) REG x3 $340 N181 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t78 long +--* t76 int +--* t80 int N183 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int REG x5 $11a N185 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 /--* t81 int +--* t82 int N187 (255, 10) [000083] -A-XG+-N-U- * CMP void REG NA N189 (255, 12) [000084] -A-XG+----- JCC void cond=UNE REG NA ------------ BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} N409 (???,???) [000315] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N411 ( 1, 2) [000092] -c---+----- t92 = CNS_INT byref 0 REG NA $VN.Null /--* t92 byref N413 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void N415 (???,???) [000316] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA N417 ( 0, 0) [000002] -----+----- RETURN void REG NA $VN.Void ------------ BB10 [0009] [000..001) -> BB11(0),BB12(1) (cond), preds={BB04,BB05} succs={BB12,BB11} N193 (???,???) [000297] ----------- IL_OFFSET void INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA N195 ( 1, 1) [000035] -----+----- t35 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N197 ( 1, 4) [000114] -c---+----- t114 = CNS_INT int 0x3FFFFFF REG NA $49 /--* t35 int +--* t114 int N199 ( 3, 6) [000115] -----+----- t115 = * AND int REG x1 /--* t115 int N201 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 x1 REG x1 $VN.Void N203 (???,???) [000298] ----------- IL_OFFSET void INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA N205 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 N207 ( 1, 4) [000121] -c---+----- t121 = CNS_INT int 0xC000000 REG NA $4a /--* t117 int +--* t121 int N209 ( 3, 6) [000122] -----+----- t122 = * AND int REG x2 N211 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 REG x3 $46 /--* t122 int +--* t123 int N213 ( 5, 11) [000124] -----+-N--- * CMP void REG NA N215 ( 7, 13) [000041] -----+----- JCC void cond=UNE REG NA ------------ BB12 [0011] [000..001) -> BB13(0.5),BB14(0.5) (cond), preds={BB10} succs={BB14,BB13} N219 (???,???) [000302] ----------- IL_OFFSET void INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N221 ( 2, 8) [000133] H----+----- t133 = CNS_INT(h) long 0x4208C8 static base addr cell REG x2 $142 /--* t133 long N223 ( 5, 10) [000134] #----+----- t134 = * IND long REG x2 $380 /--* t134 long N225 ( 7, 13) [000136] -c---+----- t136 = * LEA(b+16) long REG NA /--* t136 long N227 ( 8, 12) [000137] ---XG+----- t137 = * IND ref REG x2 /--* t137 ref N229 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 x2 REG x2 $289 N231 (???,???) [000303] ----------- IL_OFFSET void INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N233 ( 1, 1) [000140] -----+----- t140 = LCL_VAR ref V13 tmp12 u:2 x2 REG x2 /--* t140 ref N235 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte REG NA N237 (???,???) [000304] ----------- IL_OFFSET void INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N239 ( 1, 1) [000139] -----+----- t139 = LCL_VAR ref V13 tmp12 u:2 x2 (last use) REG x2 N241 ( 1, 2) [000234] -c---+----- t234 = CNS_INT long 16 REG NA $1c3 /--* t139 ref +--* t234 long N243 ( 2, 5) [000235] -----+-N--- t235 = * ADD byref REG x2 N245 ( 3, 2) [000126] -----+----- t126 = LCL_VAR int V06 tmp5 u:1 x1 (last use) REG x1 /--* t126 int N247 ( 4, 4) [000144] -c---+----- t144 = * CAST long <- int REG NA N249 ( 1, 2) [000145] -c---+----- t145 = CNS_INT long 5 REG NA $1c4 /--* t144 long +--* t145 long N251 ( 6, 7) [000146] -----+----- t146 = * BFIZ long REG x1 /--* t235 byref +--* t146 long N253 ( 9, 13) [000147] -c---+----- t147 = * LEA(b+(i*1)+0) byref REG NA /--* t147 byref N255 ( 11, 14) [000130] ---XG+----- t130 = * IND ref REG x1 /--* t130 ref N257 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 x1 REG x1 N259 (???,???) [000305] ----------- IL_OFFSET void INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] REG NA N261 ( 1, 2) [000047] -c---+----- t47 = CNS_INT long 0 REG NA $1c2 /--* t47 long N263 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void N265 (???,???) [000306] ----------- IL_OFFSET void INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N267 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t49 ref N269 ( 3, 4) [000238] -c---+----- t238 = * LEA(b+16) byref REG NA /--* t238 byref N271 ( 4, 3) [000150] ---XG+----- t150 = * IND int REG x2 N273 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 x0 (last use) REG x0 /--* t150 int +--* t50 int N275 ( 6, 5) [000151] ---XG+-N--- * CMP void REG NA N277 ( 8, 7) [000152] ---XG+----- JCC void cond=UNE REG NA ------------ BB14 [0026] [000..001) -> BB15(0.5),BB17(0.5) (cond), preds={BB12} succs={BB17,BB15} N281 (???,???) [000308] ----------- IL_OFFSET void INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N283 ( 1, 1) [000153] ----------- t153 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t153 ref N285 ( 3, 4) [000240] -c--------- t240 = * LEA(b+24) byref REG NA /--* t240 byref N287 ( 4, 3) [000158] n---GO----- t158 = * IND int REG x0 /--* t158 int N289 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 x0 REG x0 N291 ( 3, 2) [000260] ----------- t260 = LCL_VAR int V21 cse0 u:1 x0 REG x0 N293 ( 1, 2) [000159] -c--------- t159 = CNS_INT int 0 REG NA $40 /--* t260 int +--* t159 int N295 ( 15, 13) [000161] -A--GO----- * JCMP void REG NA ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} N299 (???,???) [000314] ----------- IL_OFFSET void INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N301 ( 3, 2) [000262] ----------- t262 = LCL_VAR int V21 cse0 u:1 x0 (last use) REG x0 N303 ( 1, 2) [000166] -c--------- t166 = CNS_INT int -1 REG NA $41 /--* t262 int +--* t166 int N305 ( 5, 5) [000167] ----G------ t167 = * ADD int REG x0 N307 ( 1, 1) [000162] ----------- t162 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t162 ref N309 ( 3, 4) [000242] -c--------- t242 = * LEA(b+24) byref REG NA /--* t242 byref +--* t167 int N311 ( 10, 9) [000169] nA--GO----- * STOREIND int REG NA ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} N315 (???,???) [000309] ----------- IL_OFFSET void INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N317 ( 1, 1) [000170] ----------- t170 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t170 ref N319 ( 3, 4) [000246] -c--------- t246 = * LEA(b+16) byref REG NA N321 ( 1, 2) [000171] -c--------- t171 = CNS_INT int 0 REG NA $40 /--* t246 byref +--* t171 int N323 ( 6, 6) [000173] nA--GO----- * STOREIND int REG NA N325 (???,???) [000310] ----------- IL_OFFSET void INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N327 ( 1, 1) [000249] -----+----- t249 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 N329 ( 1, 2) [000250] -c---+----- t250 = CNS_INT long 20 Fseq[_state] REG NA $1c6 /--* t249 ref +--* t250 long N331 ( 3, 4) [000251] -----+----- t251 = * ADD byref REG x0 N333 ( 1, 2) [000203] -c---+----- t203 = CNS_INT int -1 REG NA $41 /--* t251 byref +--* t203 int N335 ( 5, 7) [000204] -A-XG+----- t204 = * XADD int REG x4 N337 ( 1, 2) [000205] -c---+----- t205 = CNS_INT int -1 REG NA $41 /--* t204 int +--* t205 int N339 ( 7, 10) [000206] -A-XG+----- t206 = * ADD int REG x0 /--* t206 int N341 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 x0 REG x0 N343 (???,???) [000311] ----------- IL_OFFSET void INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N345 ( 1, 1) [000209] -----+----- t209 = LCL_VAR int V17 tmp16 u:1 x0 (last use) REG x0 $13a /--* t209 int N347 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 x2 REG x2 $VN.Void N349 (???,???) [000312] ----------- IL_OFFSET void INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N351 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 x2 REG x2 $13a N353 ( 1, 2) [000217] -c---+----- t217 = CNS_INT int 128 REG NA $4d /--* t216 int +--* t217 int N355 ( 3, 4) [000218] -----+-N-U- * CMP void REG NA N357 ( 5, 6) [000183] -----+----- JCC void cond=ULT REG NA ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} N361 (???,???) [000313] ----------- IL_OFFSET void INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N363 ( 1, 1) [000184] -----+----- t184 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t184 ref N365 (???,???) [000322] ----------- t322 = * PUTARG_REG ref REG x0 N367 ( 3, 2) [000185] -----+----- t185 = LCL_VAR int V19 tmp18 u:1 x2 (last use) REG x2 $13a /--* t185 int N369 (???,???) [000323] ----------- t323 = * PUTARG_REG int REG x1 /--* t322 ref this in x0 +--* t323 int arg1 in x1 N371 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this REG NA $VN.Void ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} N375 (???,???) [000307] ----------- IL_OFFSET void INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N377 ( 14, 2) [000155] --CXG+----- CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() REG NA $VN.Void ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} N421 (???,???) [000282] ----------- IL_OFFSET void INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA N423 ( 2, 8) [000222] H----+----- t222 = CNS_INT(h) ref '"obj"' REG x0 $500 /--* t222 ref N425 (???,???) [000317] ----------- t317 = * PUTARG_REG ref REG x0 /--* t317 ref arg0 in x0 N427 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) REG NA $VN.Void ------------ BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} N043 (???,???) [000284] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N045 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 x0 (last use) REG x0 /--* t277 long N047 (???,???) [000318] ----------- t318 = * PUTARG_REG long REG x0 N049 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls REG x1 /--* t318 long arg0 in x0 +--* t275 long calli tgt N051 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref REG x0 /--* t276 ref N053 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 x20 REG x20 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} N381 (???,???) [000299] ----------- IL_OFFSET void INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] REG NA N383 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class REG x0 $147 /--* t52 long N385 (???,???) [000319] ----------- t319 = * PUTARG_REG long REG x0 /--* t319 long arg0 in x0 N387 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST REG x0 $298 /--* t53 ref N389 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 x19 REG x19 $VN.Void N391 (???,???) [000300] ----------- IL_OFFSET void INL01 @ ??? <- INLRT @ 0x000[E-] REG NA N393 ( 3, 2) [000055] -----+----- t55 = LCL_VAR ref V08 tmp7 u:2 x19 REG x19 $298 /--* t55 ref N395 (???,???) [000320] ----------- t320 = * PUTARG_REG ref REG x0 /--* t320 ref this in x0 N397 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this REG NA $VN.Void N399 (???,???) [000301] ----------- IL_OFFSET void INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] REG NA N401 ( 3, 2) [000057] -----+----- t57 = LCL_VAR ref V08 tmp7 u:2 x19 (last use) REG x19 $298 /--* t57 ref N403 (???,???) [000321] ----------- t321 = * PUTARG_REG ref REG x0 /--* t321 ref arg0 in x0 N405 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW REG NA $29a ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** Starting PHASE Determine first cold block No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block [no changes] *************** Starting PHASE Place 'align' instructions *************** In placeLoopAlignInstructions() Identifying loops in DFS tree with following reverse post order: RPO -> BB [pre, post] 00 -> BB01[0, 20] 01 -> BB02[20, 19] 02 -> BB03[1, 18] 03 -> BB22[19, 17] 04 -> BB23[2, 16] 05 -> BB20[3, 15] 06 -> BB04[4, 14] 07 -> BB05[5, 13] 08 -> BB10[11, 12] 09 -> BB11[18, 11] 10 -> BB12[12, 10] 11 -> BB13[17, 9] 12 -> BB14[13, 8] 13 -> BB15[15, 7] 14 -> BB16[16, 6] 15 -> BB17[14, 5] 16 -> BB06[6, 4] 17 -> BB08[10, 3] 18 -> BB07[7, 2] 19 -> BB09[8, 1] 20 -> BB18[9, 0] BB09 -> BB04 is a backedge BB04 is the header of a DFS loop with 1 back edges Loop has 6 blocks BB04 -> BB10 is an exit edge BB05 -> BB10 is an exit edge BB09 -> BB18 is an exit edge BB20 -> BB04 is an entry edge Added loop L00 with header BB04 Found 1 loops *************** Natural loop graph L00 header: BB04 Members (6): [BB04..BB09] Entry: BB20 -> BB04 Exit: BB04 -> BB10; BB05 -> BB10; BB09 -> BB18 Back: BB09 -> BB04 Aligning L00 that starts at BB04, weight=800 >= 300. Marking BB20 before the loop with BBF_HAS_ALIGN for loop at BB04 BB17, bbWeight=50 ends with unconditional 'jmp' BB22, bbWeight=0 ends with unconditional 'jmp' Found 1 candidates for loop alignment *************** Finishing PHASE Place 'align' instructions Trees after Place 'align' instructions --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB02(0.5),BB03(0.5) ( cond ) i LIR BB03 [0015] 1 BB01 1 [???..???)-> BB22(0),BB23(1) ( cond ) i LIR hascall nullcheck BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck has-align BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target align BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB11(0),BB12(1) ( cond ) i LIR BB12 [0011] 1 BB10 0.50 [000..001)-> BB13(0.5),BB14(0.5) ( cond ) i LIR nullcheck BB14 [0026] 1 BB12 0.50 [000..001)-> BB15(0.5),BB17(0.5) ( cond ) i LIR BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj --------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [0000] [000..006) -> BB02(0.5),BB03(0.5) (cond), preds={} succs={BB03,BB02} N003 (???,???) [000281] ----------- IL_OFFSET void INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR ref V00 arg0 u:1 x19 REG x19 $80 N007 ( 1, 2) [000095] -c---+----- t95 = CNS_INT ref null REG NA $VN.Null /--* t0 ref +--* t95 ref N009 ( 5, 6) [000097] -----+----- * JCMP void REG NA ------------ BB03 [0015] [???..???) -> BB22(0),BB23(1) (cond), preds={BB01} succs={BB23,BB22} N013 (???,???) [000283] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N015 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN REG x2 /--* t265 long calli tgt N017 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long REG x0 /--* t266 long N019 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 x0 REG x0 N021 ( 3, 2) [000268] ----------- t268 = LCL_VAR long V23 rat1 x0 REG x0 /--* t268 long N023 ( 6, 4) [000269] #---------- t269 = * IND ref REG x20 /--* t269 ref N025 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 N027 ( 3, 2) [000272] ----------- t272 = LCL_VAR ref V22 rat0 x20 REG x20 N029 ( 1, 2) [000271] -c--------- t271 = CNS_INT long 0 REG NA /--* t272 ref +--* t271 long N031 ( 10, 7) [000274] ----------- * JCMP void REG NA ------------ BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} N035 (???,???) [000285] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N037 ( 3, 2) [000279] ----------- t279 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t279 ref N039 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 ------------ BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} N057 (???,???) [000286] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N059 ( 3, 2) [000263] ----------- t263 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t263 ref N061 ( 5, 5) [000103] -c---+----- t103 = * LEA(b+40) byref REG NA /--* t103 byref N063 ( 6, 4) [000104] n---G+----- t104 = * IND int REG x0 /--* t104 int N065 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 x0 REG x0 $VN.Void N067 (???,???) [000287] ----------- IL_OFFSET void INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] REG NA N069 ( 1, 1) [000008] -----+----- t8 = LCL_VAR int V02 tmp1 u:1 x0 (last use) REG x0 N071 ( 1, 1) [000009] -----+----- t9 = LCL_VAR int V02 tmp1 u:1 x0 REG x0 N073 ( 1, 2) [000010] -c---+----- t10 = CNS_INT int -1 REG NA $41 /--* t9 int +--* t10 int N075 ( 3, 4) [000011] -----+----- t11 = * ADD int REG x1 N077 ( 1, 2) [000012] -c---+----- t12 = CNS_INT int 31 REG NA $42 /--* t11 int +--* t12 int N079 ( 5, 7) [000013] -c---+----- t13 = * RSH int REG NA /--* t8 int +--* t13 int N081 ( 7, 9) [000014] -----+----- t14 = * OR int REG x0 /--* t14 int N083 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 x0 REG x0 $VN.Void N085 (???,???) [000288] ----------- IL_OFFSET void INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] REG NA N087 ( 1, 1) [000225] -------N--- t225 = LCL_VAR ref V00 arg0 u:1 x19 (last use) REG x19 $80 /--* t225 ref N089 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $281 N091 (???,???) [000289] ----------- IL_OFFSET void INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] REG NA N093 ( 1, 1) [000020] -----+----- t20 = LCL_VAR byref V03 tmp2 x1 REG x1 $182 /--* t20 byref N095 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 x1 REG x1 $VN.Void N097 ( 1, 1) [000228] -----+----- t228 = LCL_VAR long V20 tmp19 u:1 x1 (last use) REG x1 $2c0 N099 ( 1, 2) [000110] -c---+----- t110 = CNS_INT long -4 REG NA $1c1 /--* t228 long +--* t110 long N101 ( 4, 7) [000111] -A---+----- t111 = * ADD long REG x1 $2c1 /--* t111 long N103 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 x1 REG x1 $VN.Void ------------ BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} N107 (???,???) [000290] ----------- IL_OFFSET void INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] REG NA N109 ( 1, 1) [000025] -----+----- t25 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 /--* t25 long N111 ( 3, 2) [000026] ---XG+----- t26 = * IND int REG x2 /--* t26 int N113 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 x2 REG x2 $284 N115 (???,???) [000291] ----------- IL_OFFSET void INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] REG NA N117 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t28 int N119 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int REG x3 N121 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 x0 REG x0 /--* t31 int +--* t32 int N123 ( 4, 5) [000033] -----+-N-U- * CMP void REG NA N125 ( 6, 7) [000034] -----+----- JCC void cond=UNE REG NA ------------ BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} N129 (???,???) [000292] ----------- IL_OFFSET void INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] REG NA N131 ( 1, 1) [000059] -----+----- t59 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N133 ( 1, 4) [000060] -c---+----- t60 = CNS_INT int 0x8000000 REG NA $46 /--* t59 int +--* t60 int N135 ( 7, 11) [000064] -----+----- * JTEST void REG NA ------------ BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} N139 (???,???) [000293] ----------- IL_OFFSET void INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] REG NA N141 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N143 ( 1, 2) [000066] -c---+----- t66 = CNS_INT int 0x3F0000 REG NA $47 /--* t65 int +--* t66 int N145 ( 5, 7) [000069] -----+-N--- * TEST void REG NA N147 ( 7, 9) [000070] -----+----- JCC void cond=UNE REG NA ------------ BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} N163 (???,???) [000294] ----------- IL_OFFSET void INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] REG NA N165 ( 1, 1) [000085] -----+----- t85 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N167 ( 1, 2) [000086] -c---+----- t86 = CNS_INT int -0x10000 REG NA $48 /--* t85 int +--* t86 int N169 ( 3, 4) [000087] -----+----- t87 = * AND int REG x3 /--* t87 int N171 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 x3 REG x3 $VN.Void ------------ BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} N151 (???,???) [000295] ----------- IL_OFFSET void INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] REG NA N153 ( 1, 1) [000071] -----+----- t71 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N155 ( 1, 2) [000072] -c---+----- t72 = CNS_INT int -0x10000 REG NA $48 /--* t71 int +--* t72 int N157 ( 3, 4) [000073] -----+----- t73 = * ADD int REG x3 /--* t73 int N159 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 x3 REG x3 $VN.Void ------------ BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} N175 (???,???) [000296] ----------- IL_OFFSET void INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] REG NA N177 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 N179 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 x3 (last use) REG x3 $340 N181 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t78 long +--* t76 int +--* t80 int N183 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int REG x5 $11a N185 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 /--* t81 int +--* t82 int N187 (255, 10) [000083] -A-XG+-N-U- * CMP void REG NA N189 (255, 12) [000084] -A-XG+----- JCC void cond=UNE REG NA ------------ BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} N409 (???,???) [000315] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N411 ( 1, 2) [000092] -c---+----- t92 = CNS_INT byref 0 REG NA $VN.Null /--* t92 byref N413 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void N415 (???,???) [000316] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA N417 ( 0, 0) [000002] -----+----- RETURN void REG NA $VN.Void ------------ BB10 [0009] [000..001) -> BB11(0),BB12(1) (cond), preds={BB04,BB05} succs={BB12,BB11} N193 (???,???) [000297] ----------- IL_OFFSET void INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA N195 ( 1, 1) [000035] -----+----- t35 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 N197 ( 1, 4) [000114] -c---+----- t114 = CNS_INT int 0x3FFFFFF REG NA $49 /--* t35 int +--* t114 int N199 ( 3, 6) [000115] -----+----- t115 = * AND int REG x1 /--* t115 int N201 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 x1 REG x1 $VN.Void N203 (???,???) [000298] ----------- IL_OFFSET void INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA N205 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 N207 ( 1, 4) [000121] -c---+----- t121 = CNS_INT int 0xC000000 REG NA $4a /--* t117 int +--* t121 int N209 ( 3, 6) [000122] -----+----- t122 = * AND int REG x2 N211 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 REG x3 $46 /--* t122 int +--* t123 int N213 ( 5, 11) [000124] -----+-N--- * CMP void REG NA N215 ( 7, 13) [000041] -----+----- JCC void cond=UNE REG NA ------------ BB12 [0011] [000..001) -> BB13(0.5),BB14(0.5) (cond), preds={BB10} succs={BB14,BB13} N219 (???,???) [000302] ----------- IL_OFFSET void INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N221 ( 2, 8) [000133] H----+----- t133 = CNS_INT(h) long 0x4208C8 static base addr cell REG x2 $142 /--* t133 long N223 ( 5, 10) [000134] #----+----- t134 = * IND long REG x2 $380 /--* t134 long N225 ( 7, 13) [000136] -c---+----- t136 = * LEA(b+16) long REG NA /--* t136 long N227 ( 8, 12) [000137] ---XG+----- t137 = * IND ref REG x2 /--* t137 ref N229 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 x2 REG x2 $289 N231 (???,???) [000303] ----------- IL_OFFSET void INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N233 ( 1, 1) [000140] -----+----- t140 = LCL_VAR ref V13 tmp12 u:2 x2 REG x2 /--* t140 ref N235 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte REG NA N237 (???,???) [000304] ----------- IL_OFFSET void INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA N239 ( 1, 1) [000139] -----+----- t139 = LCL_VAR ref V13 tmp12 u:2 x2 (last use) REG x2 N241 ( 1, 2) [000234] -c---+----- t234 = CNS_INT long 16 REG NA $1c3 /--* t139 ref +--* t234 long N243 ( 2, 5) [000235] -----+-N--- t235 = * ADD byref REG x2 N245 ( 3, 2) [000126] -----+----- t126 = LCL_VAR int V06 tmp5 u:1 x1 (last use) REG x1 /--* t126 int N247 ( 4, 4) [000144] -c---+----- t144 = * CAST long <- int REG NA N249 ( 1, 2) [000145] -c---+----- t145 = CNS_INT long 5 REG NA $1c4 /--* t144 long +--* t145 long N251 ( 6, 7) [000146] -----+----- t146 = * BFIZ long REG x1 /--* t235 byref +--* t146 long N253 ( 9, 13) [000147] -c---+----- t147 = * LEA(b+(i*1)+0) byref REG NA /--* t147 byref N255 ( 11, 14) [000130] ---XG+----- t130 = * IND ref REG x1 /--* t130 ref N257 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 x1 REG x1 N259 (???,???) [000305] ----------- IL_OFFSET void INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] REG NA N261 ( 1, 2) [000047] -c---+----- t47 = CNS_INT long 0 REG NA $1c2 /--* t47 long N263 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void N265 (???,???) [000306] ----------- IL_OFFSET void INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N267 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t49 ref N269 ( 3, 4) [000238] -c---+----- t238 = * LEA(b+16) byref REG NA /--* t238 byref N271 ( 4, 3) [000150] ---XG+----- t150 = * IND int REG x2 N273 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 x0 (last use) REG x0 /--* t150 int +--* t50 int N275 ( 6, 5) [000151] ---XG+-N--- * CMP void REG NA N277 ( 8, 7) [000152] ---XG+----- JCC void cond=UNE REG NA ------------ BB14 [0026] [000..001) -> BB15(0.5),BB17(0.5) (cond), preds={BB12} succs={BB17,BB15} N281 (???,???) [000308] ----------- IL_OFFSET void INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N283 ( 1, 1) [000153] ----------- t153 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t153 ref N285 ( 3, 4) [000240] -c--------- t240 = * LEA(b+24) byref REG NA /--* t240 byref N287 ( 4, 3) [000158] n---GO----- t158 = * IND int REG x0 /--* t158 int N289 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 x0 REG x0 N291 ( 3, 2) [000260] ----------- t260 = LCL_VAR int V21 cse0 u:1 x0 REG x0 N293 ( 1, 2) [000159] -c--------- t159 = CNS_INT int 0 REG NA $40 /--* t260 int +--* t159 int N295 ( 15, 13) [000161] -A--GO----- * JCMP void REG NA ------------ BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} N299 (???,???) [000314] ----------- IL_OFFSET void INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N301 ( 3, 2) [000262] ----------- t262 = LCL_VAR int V21 cse0 u:1 x0 (last use) REG x0 N303 ( 1, 2) [000166] -c--------- t166 = CNS_INT int -1 REG NA $41 /--* t262 int +--* t166 int N305 ( 5, 5) [000167] ----G------ t167 = * ADD int REG x0 N307 ( 1, 1) [000162] ----------- t162 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t162 ref N309 ( 3, 4) [000242] -c--------- t242 = * LEA(b+24) byref REG NA /--* t242 byref +--* t167 int N311 ( 10, 9) [000169] nA--GO----- * STOREIND int REG NA ------------ BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} N315 (???,???) [000309] ----------- IL_OFFSET void INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N317 ( 1, 1) [000170] ----------- t170 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t170 ref N319 ( 3, 4) [000246] -c--------- t246 = * LEA(b+16) byref REG NA N321 ( 1, 2) [000171] -c--------- t171 = CNS_INT int 0 REG NA $40 /--* t246 byref +--* t171 int N323 ( 6, 6) [000173] nA--GO----- * STOREIND int REG NA N325 (???,???) [000310] ----------- IL_OFFSET void INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N327 ( 1, 1) [000249] -----+----- t249 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 N329 ( 1, 2) [000250] -c---+----- t250 = CNS_INT long 20 Fseq[_state] REG NA $1c6 /--* t249 ref +--* t250 long N331 ( 3, 4) [000251] -----+----- t251 = * ADD byref REG x0 N333 ( 1, 2) [000203] -c---+----- t203 = CNS_INT int -1 REG NA $41 /--* t251 byref +--* t203 int N335 ( 5, 7) [000204] -A-XG+----- t204 = * XADD int REG x4 N337 ( 1, 2) [000205] -c---+----- t205 = CNS_INT int -1 REG NA $41 /--* t204 int +--* t205 int N339 ( 7, 10) [000206] -A-XG+----- t206 = * ADD int REG x0 /--* t206 int N341 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 x0 REG x0 N343 (???,???) [000311] ----------- IL_OFFSET void INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N345 ( 1, 1) [000209] -----+----- t209 = LCL_VAR int V17 tmp16 u:1 x0 (last use) REG x0 $13a /--* t209 int N347 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 x2 REG x2 $VN.Void N349 (???,???) [000312] ----------- IL_OFFSET void INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N351 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 x2 REG x2 $13a N353 ( 1, 2) [000217] -c---+----- t217 = CNS_INT int 128 REG NA $4d /--* t216 int +--* t217 int N355 ( 3, 4) [000218] -----+-N-U- * CMP void REG NA N357 ( 5, 6) [000183] -----+----- JCC void cond=ULT REG NA ------------ BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} N361 (???,???) [000313] ----------- IL_OFFSET void INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N363 ( 1, 1) [000184] -----+----- t184 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t184 ref N365 (???,???) [000322] ----------- t322 = * PUTARG_REG ref REG x0 N367 ( 3, 2) [000185] -----+----- t185 = LCL_VAR int V19 tmp18 u:1 x2 (last use) REG x2 $13a /--* t185 int N369 (???,???) [000323] ----------- t323 = * PUTARG_REG int REG x1 /--* t322 ref this in x0 +--* t323 int arg1 in x1 N371 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this REG NA $VN.Void ------------ BB13 [0025] [000..001) (throw), preds={BB12} succs={} N375 (???,???) [000307] ----------- IL_OFFSET void INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA N377 ( 14, 2) [000155] --CXG+----- CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() REG NA $VN.Void ------------ BB02 [0014] [000..001) (throw), preds={BB01} succs={} N421 (???,???) [000282] ----------- IL_OFFSET void INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA N423 ( 2, 8) [000222] H----+----- t222 = CNS_INT(h) ref '"obj"' REG x0 $500 /--* t222 ref N425 (???,???) [000317] ----------- t317 = * PUTARG_REG ref REG x0 /--* t317 ref arg0 in x0 N427 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) REG NA $VN.Void ------------ BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} N043 (???,???) [000284] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA N045 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 x0 (last use) REG x0 /--* t277 long N047 (???,???) [000318] ----------- t318 = * PUTARG_REG long REG x0 N049 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls REG x1 /--* t318 long arg0 in x0 +--* t275 long calli tgt N051 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref REG x0 /--* t276 ref N053 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 x20 REG x20 ------------ BB11 [0010] [000..001) (throw), preds={BB10} succs={} N381 (???,???) [000299] ----------- IL_OFFSET void INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] REG NA N383 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class REG x0 $147 /--* t52 long N385 (???,???) [000319] ----------- t319 = * PUTARG_REG long REG x0 /--* t319 long arg0 in x0 N387 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST REG x0 $298 /--* t53 ref N389 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 x19 REG x19 $VN.Void N391 (???,???) [000300] ----------- IL_OFFSET void INL01 @ ??? <- INLRT @ 0x000[E-] REG NA N393 ( 3, 2) [000055] -----+----- t55 = LCL_VAR ref V08 tmp7 u:2 x19 REG x19 $298 /--* t55 ref N395 (???,???) [000320] ----------- t320 = * PUTARG_REG ref REG x0 /--* t320 ref this in x0 N397 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this REG NA $VN.Void N399 (???,???) [000301] ----------- IL_OFFSET void INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] REG NA N401 ( 3, 2) [000057] -----+----- t57 = LCL_VAR ref V08 tmp7 u:2 x19 (last use) REG x19 $298 /--* t57 ref N403 (???,???) [000321] ----------- t321 = * PUTARG_REG ref REG x0 /--* t321 ref arg0 in x0 N405 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW REG NA $29a ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [deferred prior check failed -- skipping this check] *************** In genGenerateCode() --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB02(0.5),BB03(0.5) ( cond ) i LIR BB03 [0015] 1 BB01 1 [???..???)-> BB22(0),BB23(1) ( cond ) i LIR hascall nullcheck BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR hascall nullcheck has-align BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead bwd bwd-target align BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR bwd bwd-src BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR nullcheck BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB11(0),BB12(1) ( cond ) i LIR BB12 [0011] 1 BB10 0.50 [000..001)-> BB13(0.5),BB14(0.5) ( cond ) i LIR nullcheck BB14 [0026] 1 BB12 0.50 [000..001)-> BB15(0.5),BB17(0.5) ( cond ) i LIR BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR hascall gcsafe BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR hascall gcsafe BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare hascall gcsafe newobj --------------------------------------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V00(x19) must init V03 because it has a GC ref Modified regs: [x0-xip1 x19-x20 lr] Callee-saved registers pushed: 4 [x19-x20 fp lr] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V03 tmp2, size=8, stkOffs=-0x28 Setting genSaveFpLrWithAllCalleeSavedRegisters to false --- delta bump 48 for FP frame, 16 inside frame for FP/LR relocation --- virtual stack offset to actual stack offset delta is 48 -- V01 was 0, now 48 -- V03 was -40, now 24 ; Final local variable assignments ; ; V00 arg0 [V00,T05] ( 4, 4 ) ref -> x19 class-hnd single-def ;# V01 OutArgs [V01 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V02 tmp1 [V02,T02] ( 6, 12.50) int -> x0 "Inline stloc first use temp" ; V03 tmp2 [V03 ] ( 4, 3.50) byref -> [fp+0x18] must-init pinned "Inline stloc first use temp" ; V04 tmp3 [V04,T01] ( 3, 13 ) long -> x1 "Inline stloc first use temp" ; V05 tmp4 [V05,T00] ( 10, 37 ) int -> x2 "Inline stloc first use temp" ; V06 tmp5 [V06,T13] ( 2, 1 ) int -> x1 ld-addr-op "Inline ldloca(s) first use temp" ; V07 tmp6 [V07,T08] ( 7, 3.50) ref -> x1 class-hnd exact single-def "Inline stloc first use temp" ; V08 tmp7 [V08,T14] ( 3, 0 ) ref -> x19 class-hnd exact single-def "NewObj constructor temp" ; V09 tmp8 [V09,T04] ( 3, 8 ) int -> x3 ;* V10 tmp9 [V10 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V11 tmp10 [V11 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V12 tmp11 [V12 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ; V13 tmp12 [V13,T09] ( 3, 3 ) ref -> x2 single-def "MemoryMarshal.GetArrayDataReference array" ;* V14 tmp13 [V14 ] ( 0, 0 ) struct ( 8) zero-ref ld-addr-op "Inline stloc first use temp" ;* V15 tmp14 [V15 ] ( 0, 0 ) struct ( 8) zero-ref ld-addr-op "NewObj constructor temp" ;* V16 tmp15 [V16 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V17 tmp16 [V17,T10] ( 2, 2 ) int -> x0 "Inlining Arg" ;* V18 tmp17 [V18 ] ( 0, 0 ) int -> zero-ref "field V14._state (fldOffset=0x0)" P-INDEP ; V19 tmp18 [V19,T11] ( 3, 1.50) int -> x2 "field V15._state (fldOffset=0x0)" P-INDEP ; V20 tmp19 [V20,T07] ( 2, 4 ) long -> x1 "Cast away GC" ; V21 cse0 [V21,T12] ( 3, 1.50) int -> x0 "CSE #01: moderate" ; V22 rat0 [V22,T03] ( 6, 10 ) ref -> x20 "Final offset" ; V23 rat1 [V23,T06] ( 3, 4 ) long -> x0 "TlsRootAddr access" ; ; Lcl frame size = 16 Created: G_M47640_IG02: ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} Mark labels for codegen BB01 : first block BB02 : branch target BB22 : branch target BB10 : branch target BB10 : branch target BB08 : branch target BB09 : branch target BB04 : branch target BB11 : branch target BB13 : branch target BB15 : branch target BB18 : branch target BB18 : branch target BB18 : branch target BB20 : branch target *************** After genMarkLabelsForCodegen() --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] --------------------------------------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB02(0.5),BB03(0.5) ( cond ) i LIR label BB03 [0015] 1 BB01 1 [???..???)-> BB22(0),BB23(1) ( cond ) i LIR hascall nullcheck BB23 [0043] 1 BB03 1 [???..???)-> BB20(1) (always) LIR internal BB20 [0040] 2 BB22,BB23 1 [000..001)-> BB04(1) (always) i LIR label hascall nullcheck has-align BB04 [0002] 2 BB09,BB20 8 [000..001)-> BB10(0.5),BB05(0.5) ( cond ) i LIR loophead label bwd bwd-target align BB05 [0003] 1 BB04 4 [000..001)-> BB10(0.5),BB06(0.5) ( cond ) i LIR bwd BB06 [0004] 1 BB05 4 [000..001)-> BB08(0.5),BB07(0.5) ( cond ) i LIR bwd BB07 [0005] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR bwd BB08 [0006] 1 BB06 2 [000..001)-> BB09(1) (always) i LIR label bwd BB09 [0007] 2 BB07,BB08 4 [000..001)-> BB04(0.5),BB18(0.5) ( cond ) i LIR label bwd bwd-src BB18 [0039] 4 BB09,BB15,BB16,BB17 1 [000..007) (return) i LIR label nullcheck BB10 [0009] 2 BB04,BB05 0.50 [000..001)-> BB11(0),BB12(1) ( cond ) i LIR label BB12 [0011] 1 BB10 0.50 [000..001)-> BB13(0.5),BB14(0.5) ( cond ) i LIR nullcheck BB14 [0026] 1 BB12 0.50 [000..001)-> BB15(0.5),BB17(0.5) ( cond ) i LIR BB17 [0031] 1 BB14 0.50 [000..001)-> BB18(1) (always) i LIR BB15 [0029] 1 BB14 0.50 [000..001)-> BB18(0.5),BB16(0.5) ( cond ) i LIR label nullcheck BB16 [0030] 1 BB15 0.50 [000..001)-> BB18(1) (always) i LIR hascall gcsafe BB13 [0025] 1 BB12 0.50 [000..001) (throw ) i LIR label hascall gcsafe BB02 [0014] 1 BB01 0.50 [000..001) (throw ) i LIR label hascall gcsafe BB22 [0042] 1 BB03 0 [???..???)-> BB20(1) (always) LIR rare internal label BB11 [0010] 1 BB10 0 [000..001) (throw ) i LIR rare label hascall gcsafe newobj --------------------------------------------------------------------------------------------------------------------------------------------------------------------- =============== Generating BB01 [0000] [000..006) -> BB02(0.5),BB03(0.5) (cond), preds={} succs={BB03,BB02} flags=0x00000000.00004011: i LIR label BB01 IN (1)={V00} + ByrefExposed + GcHeap OUT(1)={V00} + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V00(x19) Change life 0000000000000000 {} -> 0000000000000020 {V00} V00 in reg x19 is becoming live [------] Live regs: 0000000000000000 {} + {x19} => 0000000000080000 {x19} Debug: New V00 debug range: first Live regs: (unchanged) 0000000000080000 {x19} GC regs: (unchanged) 80000 {x19} Byref regs: (unchanged) 0000 {} L_M47640_BB01: Label: G_M47640_IG02, GCvars=0000000000000000 {}, gcrefRegs=80000 {x19}, byrefRegs=0000 {} Scope info: begin block BB01, IL range [000..006) Added IP mapping: 0x0000 STACK_EMPTY (G_M47640_IG02,ins#0,ofs#0) label Generating: N003 (???,???) [000281] ----------- IL_OFFSET void INL02 @ 0x000[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA Generating: N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR ref V00 arg0 u:1 x19 REG x19 $80 Generating: N007 ( 1, 2) [000095] -c---+----- t95 = CNS_INT ref null REG NA $VN.Null /--* t0 ref +--* t95 ref Generating: N009 ( 5, 6) [000097] -----+----- * JCMP void REG NA Mapped BB01 to G_M47640_IG02 IN0001: cbz (LARGEJMP)L_M47640_BB02 Variable Live Range History Dump for BB01 V00 arg0: x19 [(G_M47640_IG02,ins#0,ofs#0), ...] =============== Generating BB03 [0015] [???..???) -> BB22(0),BB23(1) (cond), preds={BB01} succs={BB23,BB22} flags=0x00000000.08000411: i LIR hascall nullcheck BB03 IN (1)={ V00 } + ByrefExposed + GcHeap OUT(3)={V22 V00 V23} + ByrefExposed + GcHeap Recording Var Locations at start of BB03 V00(x19) Liveness not changing: 0000000000000020 {V00} Live regs: 0000000000000000 {} + {x19} => 0000000000080000 {x19} GC regs: 0000 {} => 80000 {x19} Byref regs: (unchanged) 0000 {} L_M47640_BB03: Scope info: begin block BB03, IL range [???..???) Scope info: ignoring block beginning genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N013 (???,???) [000283] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N015 ( 2, 8) [000265] H---------- t265 = CNS_INT(h) long 0x420480 UNKNOWN REG x2 /--* t265 long calli tgt Generating: N017 ( 19, 10) [000266] --CXG------ t266 = * CALL ind _tls_get_addr long REG x0 Mapped BB03 to G_M47640_IG02 IN0002: mrs x1, tpidr_el0 IN0003: adrp x0, [HIGH RELOC #0x420480] IN0004: ldr x2, [x0] IN0005: add x0, x0, [LOW RELOC #0x420480] Call: GCvars=0000000000000000 {}, gcrefRegs=80000 {x19}, byrefRegs=0000 {} IN0006: blr x0 IN0007: add x0, x1, x0 /--* t266 long Generating: N019 ( 23, 13) [000267] DACXG------ * STORE_LCL_VAR long V23 rat1 x0 REG x0 V23 in reg x0 is becoming live [000267] Live regs: 0000000000080000 {x19} + {x0} => 0000000000080001 {x0 x19} Live vars after [000267]: {V00} +{V23} => {V00 V23} Generating: N021 ( 3, 2) [000268] ----------- t268 = LCL_VAR long V23 rat1 x0 REG x0 /--* t268 long Generating: N023 ( 6, 4) [000269] #---------- t269 = * IND ref REG x20 IN0008: ldr x20, [x0] GC regs: 80000 {x19} => 180000 {x19 x20} /--* t269 ref Generating: N025 ( 10, 7) [000270] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 GC regs: 180000 {x19 x20} => 80000 {x19} V22 in reg x20 is becoming live [000270] Live regs: 0000000000080001 {x0 x19} + {x20} => 0000000000180001 {x0 x19 x20} Live vars after [000270]: {V00 V23} +{V22} => {V00 V22 V23} GC regs: 80000 {x19} => 180000 {x19 x20} Generating: N027 ( 3, 2) [000272] ----------- t272 = LCL_VAR ref V22 rat0 x20 REG x20 Generating: N029 ( 1, 2) [000271] -c--------- t271 = CNS_INT long 0 REG NA /--* t272 ref +--* t271 long Generating: N031 ( 10, 7) [000274] ----------- * JCMP void REG NA IN0009: cbz (LARGEJMP)L_M47640_BB22 Scope info: ignoring block end Variable Live Range History Dump for BB03 V00 arg0: x19 [(G_M47640_IG02,ins#0,ofs#0), ...] =============== Generating BB23 [0043] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} flags=0x00000000.00000021: LIR internal BB23 IN (2)={V22 V00} + ByrefExposed + GcHeap OUT(2)={V22 V00} + ByrefExposed + GcHeap Recording Var Locations at start of BB23 V22(x20) V00(x19) Change life 0000000000000068 {V00 V22 V23} -> 0000000000000028 {V00 V22} V23 in reg x0 is becoming dead [------] Live regs: (unchanged) 0000000000000000 {} Live regs: 0000000000000000 {} + {x19 x20} => 0000000000180000 {x19 x20} GC regs: 0000 {} => 180000 {x19 x20} Byref regs: (unchanged) 0000 {} L_M47640_BB23: Scope info: begin block BB23, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M47640_IG02,ins#9,ofs#44) label Added IP mapping: 0x0000 STACK_EMPTY (G_M47640_IG02,ins#9,ofs#44) label Generating: N035 (???,???) [000285] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N037 ( 3, 2) [000279] ----------- t279 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t279 ref Generating: N039 ( 7, 5) [000280] DA--------- * STORE_LCL_VAR ref V22 rat0 x20 REG x20 V22 in reg x20 is becoming dead [000279] Live regs: 0000000000180000 {x19 x20} - {x20} => 0000000000080000 {x19} Live vars after [000279]: {V00 V22} -{V22} => {V00} GC regs: 180000 {x19 x20} => 80000 {x19} V22 in reg x20 is becoming live [000280] Live regs: 0000000000080000 {x19} + {x20} => 0000000000180000 {x19 x20} Live vars after [000280]: {V00} +{V22} => {V00 V22} GC regs: 80000 {x19} => 180000 {x19 x20} Scope info: ignoring block end Variable Live Range History Dump for BB23 V00 arg0: x19 [(G_M47640_IG02,ins#0,ofs#0), ...] =============== Generating BB20 [0040] [000..001) -> BB04(1) (always), preds={BB22,BB23} succs={BB04} flags=0x00000000.08014411: i LIR label hascall nullcheck has-align BB20 IN (2)={ V22 V00} + ByrefExposed + GcHeap OUT(2)={V04 V02 } + ByrefExposed + GcHeap Recording Var Locations at start of BB20 V22(x20) V00(x19) Liveness not changing: 0000000000000028 {V00 V22} Live regs: 0000000000000000 {} + {x19 x20} => 0000000000180000 {x19 x20} GC regs: 0000 {} => 180000 {x19 x20} Byref regs: (unchanged) 0000 {} L_M47640_BB20: Saved: G_M47640_IG02: ; offs=0x000000, size=0x002C, bbWeight=1, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, BB01 [0000], BB03 [0015], byref Created: G_M47640_IG03: ; offs=0x00002C, size=0x0000, bbWeight=1, gcrefRegs=0000 {} Label: G_M47640_IG03, GCvars=0000000000000000 {}, gcrefRegs=180000 {x19 x20}, byrefRegs=0000 {} Scope info: begin block BB20, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N057 (???,???) [000286] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N059 ( 3, 2) [000263] ----------- t263 = LCL_VAR ref V22 rat0 x20 (last use) REG x20 /--* t263 ref Generating: N061 ( 5, 5) [000103] -c---+----- t103 = * LEA(b+40) byref REG NA /--* t103 byref Generating: N063 ( 6, 4) [000104] n---G+----- t104 = * IND int REG x0 V22 in reg x20 is becoming dead [000263] Live regs: 0000000000180000 {x19 x20} - {x20} => 0000000000080000 {x19} Live vars after [000263]: {V00 V22} -{V22} => {V00} GC regs: 180000 {x19 x20} => 80000 {x19} Mapped BB20 to G_M47640_IG03 IN000a: ldr w0, [x20, #0x28] /--* t104 int Generating: N065 ( 6, 4) [000007] DA--G+----- * STORE_LCL_VAR int V02 tmp1 d:1 x0 REG x0 $VN.Void V02 in reg x0 is becoming live [000007] Live regs: 0000000000080000 {x19} + {x0} => 0000000000080001 {x0 x19} Live vars after [000007]: {V00} +{V02} => {V00 V02} genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N067 (???,???) [000287] ----------- IL_OFFSET void INL01 @ 0x011[E-] <- INLRT @ 0x000[E-] REG NA Generating: N069 ( 1, 1) [000008] -----+----- t8 = LCL_VAR int V02 tmp1 u:1 x0 (last use) REG x0 Generating: N071 ( 1, 1) [000009] -----+----- t9 = LCL_VAR int V02 tmp1 u:1 x0 REG x0 Generating: N073 ( 1, 2) [000010] -c---+----- t10 = CNS_INT int -1 REG NA $41 /--* t9 int +--* t10 int Generating: N075 ( 3, 4) [000011] -----+----- t11 = * ADD int REG x1 IN000b: sub w1, w0, #1 Generating: N077 ( 1, 2) [000012] -c---+----- t12 = CNS_INT int 31 REG NA $42 /--* t11 int +--* t12 int Generating: N079 ( 5, 7) [000013] -c---+----- t13 = * RSH int REG NA /--* t8 int +--* t13 int Generating: N081 ( 7, 9) [000014] -----+----- t14 = * OR int REG x0 V02 in reg x0 is becoming dead [000008] Live regs: 0000000000080001 {x0 x19} - {x0} => 0000000000080000 {x19} Live vars after [000008]: {V00 V02} -{V02} => {V00} IN000c: orr w0, w0, w1, ASR #31 /--* t14 int Generating: N083 ( 7, 9) [000015] DA---+----- * STORE_LCL_VAR int V02 tmp1 d:2 x0 REG x0 $VN.Void V02 in reg x0 is becoming live [000015] Live regs: 0000000000080000 {x19} + {x0} => 0000000000080001 {x0 x19} Live vars after [000015]: {V00} +{V02} => {V00 V02} genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N085 (???,???) [000288] ----------- IL_OFFSET void INL01 @ 0x01A[E-] <- INLRT @ 0x000[E-] REG NA Generating: N087 ( 1, 1) [000225] -------N--- t225 = LCL_VAR ref V00 arg0 u:1 x19 (last use) REG x19 $80 /--* t225 ref Generating: N089 ( 1, 3) [000019] DA---O----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $281 V00 in reg x19 is becoming dead [000225] Live regs: 0000000000080001 {x0 x19} - {x19} => 0000000000000001 {x0} Debug: Closing V00 debug range. Live vars after [000225]: {V00 V02} -{V00} => {V02} GC regs: 80000 {x19} => 0000 {} IN000d: str x19, [fp, #0x18] // [V03 tmp2] genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N091 (???,???) [000289] ----------- IL_OFFSET void INL01 @ 0x021[E-] <- INLRT @ 0x000[E-] REG NA Generating: N093 ( 1, 1) [000020] -----+----- t20 = LCL_VAR byref V03 tmp2 x1 REG x1 $182 IN000e: ldr x1, [fp, #0x18] // [V03 tmp2] Byref regs: 0000 {} => 0002 {x1} /--* t20 byref Generating: N095 ( 1, 3) [000227] DA---+----- * STORE_LCL_VAR long V20 tmp19 d:1 x1 REG x1 $VN.Void Byref regs: 0002 {x1} => 0000 {} V20 in reg x1 is becoming live [000227] Live regs: 0000000000000001 {x0} + {x1} => 0000000000000003 {x0 x1} Live vars after [000227]: {V02} +{V20} => {V02 V20} Generating: N097 ( 1, 1) [000228] -----+----- t228 = LCL_VAR long V20 tmp19 u:1 x1 (last use) REG x1 $2c0 Generating: N099 ( 1, 2) [000110] -c---+----- t110 = CNS_INT long -4 REG NA $1c1 /--* t228 long +--* t110 long Generating: N101 ( 4, 7) [000111] -A---+----- t111 = * ADD long REG x1 $2c1 V20 in reg x1 is becoming dead [000228] Live regs: 0000000000000003 {x0 x1} - {x1} => 0000000000000001 {x0} Live vars after [000228]: {V02 V20} -{V20} => {V02} IN000f: sub x1, x1, #4 /--* t111 long Generating: N103 ( 4, 7) [000024] DA---+----- * STORE_LCL_VAR long V04 tmp3 d:1 x1 REG x1 $VN.Void V04 in reg x1 is becoming live [000024] Live regs: 0000000000000001 {x0} + {x1} => 0000000000000003 {x0 x1} Live vars after [000024]: {V02} +{V04} => {V02 V04} IN0010: align [4 bytes] IN0011: align [4 bytes] IN0012: align [4 bytes] IN0013: align [4 bytes] Adding 'align' instruction of 16 bytes in G_M47640_IG03. Mapping 'align' instruction in IG03 to target IG03 Saved: G_M47640_IG03: ; offs=0x00002C, size=0x0028, bbWeight=1, gcrefRegs=180000 {x19 x20}, byrefRegs=0000 {}, BB20 [0040], byref, align Created: G_M47640_IG04: ; offs=0x000054, size=0x0000, bbWeight=1, gcrefRegs=0000 {} Variable Live Range History Dump for BB20 V00 arg0: x19 [(G_M47640_IG02,ins#0,ofs#0), (G_M47640_IG03,ins#3,ofs#12)] =============== Generating BB04 [0002] [000..001) -> BB10(0.5),BB05(0.5) (cond), preds={BB09,BB20} succs={BB05,BB10} flags=0x00000000.a000e011: i LIR loophead label bwd bwd-target align BB04 IN (2)={ V04 V02} + ByrefExposed + GcHeap OUT(3)={V05 V04 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB04 V04(x1) V02(x0) Liveness not changing: 0000000000000006 {V02 V04} Live regs: 0000000000000000 {} + {x0 x1} => 0000000000000003 {x0 x1} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB04: Label: G_M47640_IG04, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB04, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N107 (???,???) [000290] ----------- IL_OFFSET void INL01 @ 0x029[E-] <- INLRT @ 0x000[E-] REG NA Generating: N109 ( 1, 1) [000025] -----+----- t25 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 /--* t25 long Generating: N111 ( 3, 2) [000026] ---XG+----- t26 = * IND int REG x2 Mapped BB04 to G_M47640_IG04 IN0014: ldr w2, [x1] /--* t26 int Generating: N113 ( 3, 3) [000027] DA-XG+----- * STORE_LCL_VAR int V05 tmp4 d:1 x2 REG x2 $284 V05 in reg x2 is becoming live [000027] Live regs: 0000000000000003 {x0 x1} + {x2} => 0000000000000007 {x0 x1 x2} Live vars after [000027]: {V02 V04} +{V05} => {V02 V04 V05} genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N115 (???,???) [000291] ----------- IL_OFFSET void INL01 @ 0x02D[E-] <- INLRT @ 0x000[E-] REG NA Generating: N117 ( 1, 1) [000028] -----+----- t28 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t28 int Generating: N119 ( 2, 3) [000031] -----+----- t31 = * CAST int <- ushort <- int REG x3 IN0015: uxth w3, w2 Generating: N121 ( 1, 1) [000032] -----+----- t32 = LCL_VAR int V02 tmp1 u:2 x0 REG x0 /--* t31 int +--* t32 int Generating: N123 ( 4, 5) [000033] -----+-N-U- * CMP void REG NA IN0016: cmp w3, w0 Generating: N125 ( 6, 7) [000034] -----+----- JCC void cond=UNE REG NA IN0017: bne (LARGEJMP)L_M47640_BB10 Variable Live Range History Dump for BB04 ..None.. =============== Generating BB05 [0003] [000..001) -> BB10(0.5),BB06(0.5) (cond), preds={BB04} succs={BB06,BB10} flags=0x00000000.20000011: i LIR bwd BB05 IN (3)={V05 V04 V02} + ByrefExposed + GcHeap OUT(3)={V05 V04 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB05 V05(x2) V04(x1) V02(x0) Liveness not changing: 0000000000000007 {V02 V04 V05} Live regs: 0000000000000000 {} + {x0 x1 x2} => 0000000000000007 {x0 x1 x2} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB05: Adding label due to BB weight difference: BBJ_COND BB04 with weight 800 different from BB05 with weight 400 Saved: G_M47640_IG04: ; offs=0x000054, size=0x0014, bbWeight=8, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0002], byref Created: G_M47640_IG05: ; offs=0x000068, size=0x0000, bbWeight=4, gcrefRegs=0000 {} Label: G_M47640_IG05, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB05, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N129 (???,???) [000292] ----------- IL_OFFSET void INL01 @ 0x038[E-] <- INLRT @ 0x000[E-] REG NA Generating: N131 ( 1, 1) [000059] -----+----- t59 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 Generating: N133 ( 1, 4) [000060] -c---+----- t60 = CNS_INT int 0x8000000 REG NA $46 /--* t59 int +--* t60 int Generating: N135 ( 7, 11) [000064] -----+----- * JTEST void REG NA Mapped BB05 to G_M47640_IG05 IN0018: tbnz (LARGEJMP)L_M47640_BB10 Variable Live Range History Dump for BB05 ..None.. =============== Generating BB06 [0004] [000..001) -> BB08(0.5),BB07(0.5) (cond), preds={BB05} succs={BB07,BB08} flags=0x00000000.20000011: i LIR bwd BB06 IN (3)={V05 V04 V02} + ByrefExposed + GcHeap OUT(3)={V05 V04 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB06 V05(x2) V04(x1) V02(x0) Liveness not changing: 0000000000000007 {V02 V04 V05} Live regs: 0000000000000000 {} + {x0 x1 x2} => 0000000000000007 {x0 x1 x2} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB06: Scope info: begin block BB06, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N139 (???,???) [000293] ----------- IL_OFFSET void INL01 @ 0x042[E-] <- INLRT @ 0x000[E-] REG NA Generating: N141 ( 1, 1) [000065] -----+----- t65 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 Generating: N143 ( 1, 2) [000066] -c---+----- t66 = CNS_INT int 0x3F0000 REG NA $47 /--* t65 int +--* t66 int Generating: N145 ( 5, 7) [000069] -----+-N--- * TEST void REG NA Mapped BB06 to G_M47640_IG05 IN0019: tst w2, #0x3F0000 Generating: N147 ( 7, 9) [000070] -----+----- JCC void cond=UNE REG NA IN001a: bne (LARGEJMP)L_M47640_BB08 Variable Live Range History Dump for BB06 ..None.. =============== Generating BB07 [0005] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} flags=0x00000000.20000011: i LIR bwd BB07 IN (3)={V05 V04 V02 } + ByrefExposed + GcHeap OUT(4)={V05 V04 V02 V09} + ByrefExposed + GcHeap Recording Var Locations at start of BB07 V05(x2) V04(x1) V02(x0) Liveness not changing: 0000000000000007 {V02 V04 V05} Live regs: 0000000000000000 {} + {x0 x1 x2} => 0000000000000007 {x0 x1 x2} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB07: Adding label due to BB weight difference: BBJ_COND BB06 with weight 400 different from BB07 with weight 200 Saved: G_M47640_IG05: ; offs=0x000068, size=0x0014, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0003], BB06 [0004], byref Created: G_M47640_IG06: ; offs=0x00007C, size=0x0000, bbWeight=2, gcrefRegs=0000 {} Label: G_M47640_IG06, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB07, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N163 (???,???) [000294] ----------- IL_OFFSET void INL01 @ 0x04C[E-] <- INLRT @ 0x000[E-] REG NA Generating: N165 ( 1, 1) [000085] -----+----- t85 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 Generating: N167 ( 1, 2) [000086] -c---+----- t86 = CNS_INT int -0x10000 REG NA $48 /--* t85 int +--* t86 int Generating: N169 ( 3, 4) [000087] -----+----- t87 = * AND int REG x3 Mapped BB07 to G_M47640_IG06 IN001b: and w3, w2, #0xFFFF0000 /--* t87 int Generating: N171 ( 3, 4) [000088] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:2 x3 REG x3 $VN.Void V09 in reg x3 is becoming live [000088] Live regs: 0000000000000007 {x0 x1 x2} + {x3} => 000000000000000F {x0 x1 x2 x3} Live vars after [000088]: {V02 V04 V05} +{V09} => {V02 V04 V05 V09} IN001c: b L_M47640_BB09 Variable Live Range History Dump for BB07 ..None.. =============== Generating BB08 [0006] [000..001) -> BB09(1) (always), preds={BB06} succs={BB09} flags=0x00000000.20004011: i LIR label bwd BB08 IN (3)={V05 V04 V02 } + ByrefExposed + GcHeap OUT(4)={V05 V04 V02 V09} + ByrefExposed + GcHeap Recording Var Locations at start of BB08 V05(x2) V04(x1) V02(x0) Change life 0000000000000017 {V02 V04 V05 V09} -> 0000000000000007 {V02 V04 V05} V09 in reg x3 is becoming dead [------] Live regs: (unchanged) 0000000000000000 {} Live regs: 0000000000000000 {} + {x0 x1 x2} => 0000000000000007 {x0 x1 x2} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB08: Saved: G_M47640_IG06: ; offs=0x00007C, size=0x0008, bbWeight=2, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB07 [0005], byref Created: G_M47640_IG07: ; offs=0x000084, size=0x0000, bbWeight=2, gcrefRegs=0000 {} Label: G_M47640_IG07, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB08, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N151 (???,???) [000295] ----------- IL_OFFSET void INL01 @ 0x056[E-] <- INLRT @ 0x000[E-] REG NA Generating: N153 ( 1, 1) [000071] -----+----- t71 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 Generating: N155 ( 1, 2) [000072] -c---+----- t72 = CNS_INT int -0x10000 REG NA $48 /--* t71 int +--* t72 int Generating: N157 ( 3, 4) [000073] -----+----- t73 = * ADD int REG x3 Mapped BB08 to G_M47640_IG07 IN001d: sub w3, w2, #16, LSL #12 /--* t73 int Generating: N159 ( 3, 4) [000074] DA---+----- * STORE_LCL_VAR int V09 tmp8 d:1 x3 REG x3 $VN.Void V09 in reg x3 is becoming live [000074] Live regs: 0000000000000007 {x0 x1 x2} + {x3} => 000000000000000F {x0 x1 x2 x3} Live vars after [000074]: {V02 V04 V05} +{V09} => {V02 V04 V05 V09} Variable Live Range History Dump for BB08 ..None.. =============== Generating BB09 [0007] [000..001) -> BB04(0.5),BB18(0.5) (cond), preds={BB07,BB08} succs={BB18,BB04} flags=0x00000000.60004011: i LIR label bwd bwd-src BB09 IN (4)={V05 V04 V02 V09} + ByrefExposed + GcHeap OUT(2)={ V04 V02 } + ByrefExposed + GcHeap Recording Var Locations at start of BB09 V05(x2) V04(x1) V02(x0) V09(x3) Liveness not changing: 0000000000000017 {V02 V04 V05 V09} Live regs: 0000000000000000 {} + {x0 x1 x2 x3} => 000000000000000F {x0 x1 x2 x3} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB09: Saved: G_M47640_IG07: ; offs=0x000084, size=0x0004, bbWeight=2, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB08 [0006], byref Created: G_M47640_IG08: ; offs=0x000088, size=0x0000, bbWeight=4, gcrefRegs=0000 {} Label: G_M47640_IG08, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB09, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N175 (???,???) [000296] ----------- IL_OFFSET void INL01 @ 0x060[E-] <- INLRT @ 0x000[E-] REG NA Generating: N177 ( 1, 1) [000078] -----+-N--- t78 = LCL_VAR long V04 tmp3 u:1 x1 REG x1 $2c1 Generating: N179 ( 1, 1) [000076] -----+----- t76 = LCL_VAR int V09 tmp8 u:3 x3 (last use) REG x3 $340 Generating: N181 ( 1, 1) [000080] -----+----- t80 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 /--* t78 long +--* t76 int +--* t80 int Generating: N183 (255, 8) [000081] -A-XG+----- t81 = * CMPXCHG int REG x5 $11a V09 in reg x3 is becoming dead [000076] Live regs: 000000000000000F {x0 x1 x2 x3} - {x3} => 0000000000000007 {x0 x1 x2} Live vars after [000076]: {V02 V04 V05 V09} -{V09} => {V02 V04 V05} New Basic Block BB24 [0044] created. Mark BB24 as label: codegen temp block New Basic Block BB25 [0045] created. Mark BB25 as label: codegen temp block L_M47640_BB24: Label: G_M47640_IG08, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Mapped BB09 to G_M47640_IG08 IN001e: ldaxr w5, [x1] IN001f: cmp w5, w2 IN0020: bne (LARGEJMP)L_M47640_BB25 IN0021: stlxr w4, w3, [x1] IN0022: cbnz (LARGEJMP)L_M47640_BB24 L_M47640_BB25: Saved: G_M47640_IG08: ; offs=0x000088, size=0x001C, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB09 [0007], byref Created: G_M47640_IG09: ; offs=0x0000A4, size=0x0000, bbWeight=4, gcrefRegs=0000 {} Label: G_M47640_IG09, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Mapped BB09 to G_M47640_IG09 IN0023: dmb ish Generating: N185 ( 1, 1) [000082] -----+----- t82 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 /--* t81 int +--* t82 int Generating: N187 (255, 10) [000083] -A-XG+-N-U- * CMP void REG NA V05 in reg x2 is becoming dead [000082] Live regs: 0000000000000007 {x0 x1 x2} - {x2} => 0000000000000003 {x0 x1} Live vars after [000082]: {V02 V04 V05} -{V05} => {V02 V04} IN0024: cmp w5, w2 Generating: N189 (255, 12) [000084] -A-XG+----- JCC void cond=UNE REG NA IN0025: bne (LARGEJMP)L_M47640_BB04 ** IG09 jumps back to IG04 forming a loop. Mark BB18 as label: alignment end-of-loop Variable Live Range History Dump for BB09 ..None.. =============== Generating BB18 [0039] [000..007) (return), preds={BB09,BB15,BB16,BB17} succs={} flags=0x00000000.00004411: i LIR label nullcheck BB18 IN (0)={} OUT(0)={} Recording Var Locations at start of BB18 Change life 0000000000000006 {V02 V04} -> 0000000000000000 {} V04 in reg x1 is becoming dead [------] Live regs: (unchanged) 0000000000000000 {} V02 in reg x0 is becoming dead [------] Live regs: (unchanged) 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB18: Adding label due to BB weight difference: BBJ_COND BB09 with weight 400 different from BB18 with weight 100 Saved: G_M47640_IG09: ; offs=0x0000A4, size=0x0010, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, loop=IG04, BB09 [0007], byref Created: G_M47640_IG10: ; offs=0x0000B4, size=0x0000, bbWeight=1, gcrefRegs=0000 {} Label: G_M47640_IG10, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB18, IL range [000..007) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N409 (???,???) [000315] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA Generating: N411 ( 1, 2) [000092] -c---+----- t92 = CNS_INT byref 0 REG NA $VN.Null /--* t92 byref Generating: N413 ( 1, 3) [000093] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void Mapped BB18 to G_M47640_IG10 IN0026: str xzr, [fp, #0x18] // [V03 tmp2] Added IP mapping: 0x0006 STACK_EMPTY (G_M47640_IG10,ins#1,ofs#4) Generating: N415 (???,???) [000316] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA Generating: N417 ( 0, 0) [000002] -----+----- RETURN void REG NA $VN.Void Added IP mapping: EPILOG (G_M47640_IG10,ins#1,ofs#4) label Reserving epilog IG for block BB18 Saved: G_M47640_IG10: ; offs=0x0000B4, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB18 [0039], byref Created: G_M47640_IG11: ; offs=0x0000B8, size=0x0000, bbWeight=1, gcrefRegs=0000 {} Created: G_M47640_IG12: ; offs=0x0001B8, size=0x0000, bbWeight=1, gcrefRegs=0000 {}, epilog *************** After placeholder IG creation G_M47640_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG G_M47640_IG02: ; offs=0x000000, size=0x002C, bbWeight=1, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, BB01 [0000], BB03 [0015], byref G_M47640_IG03: ; offs=0x00002C, size=0x0028, bbWeight=1, gcrefRegs=180000 {x19 x20}, byrefRegs=0000 {}, BB20 [0040], byref, align G_M47640_IG04: ; offs=0x000054, size=0x0014, bbWeight=8, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0002], byref G_M47640_IG05: ; offs=0x000068, size=0x0014, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0003], BB06 [0004], byref G_M47640_IG06: ; offs=0x00007C, size=0x0008, bbWeight=2, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB07 [0005], byref G_M47640_IG07: ; offs=0x000084, size=0x0004, bbWeight=2, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB08 [0006], byref G_M47640_IG08: ; offs=0x000088, size=0x001C, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB09 [0007], byref G_M47640_IG09: ; offs=0x0000A4, size=0x0010, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, loop=IG04, BB09 [0007], byref G_M47640_IG10: ; offs=0x0000B4, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB18 [0039], byref G_M47640_IG11: ; epilog placeholder, next placeholder=, BB18 [0039], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {} G_M47640_IG12: ; offs=0x0001B8, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Current IG Variable Live Range History Dump for BB18 ..None.. =============== Generating BB10 [0009] [000..001) -> BB11(0),BB12(1) (cond), preds={BB04,BB05} succs={BB12,BB11} flags=0x00000000.00004011: i LIR label BB10 IN (2)={V05 V02 } + ByrefExposed + GcHeap OUT(2)={ V02 V06} + ByrefExposed + GcHeap Recording Var Locations at start of BB10 V05(x2) V02(x0) Change life 0000000000000000 {} -> 0000000000000005 {V02 V05} V05 in reg x2 is becoming live [------] Live regs: 0000000000000000 {} + {x2} => 0000000000000004 {x2} V02 in reg x0 is becoming live [------] Live regs: 0000000000000004 {x2} + {x0} => 0000000000000005 {x0 x2} Live regs: (unchanged) 0000000000000005 {x0 x2} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB10: Label: G_M47640_IG12, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB10, IL range [000..001) Added IP mapping: 0x0000 STACK_EMPTY (G_M47640_IG12,ins#0,ofs#0) label Generating: N193 (???,???) [000297] ----------- IL_OFFSET void INL06 @ 0x000[E-] <- INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA Generating: N195 ( 1, 1) [000035] -----+----- t35 = LCL_VAR int V05 tmp4 u:1 x2 REG x2 Generating: N197 ( 1, 4) [000114] -c---+----- t114 = CNS_INT int 0x3FFFFFF REG NA $49 /--* t35 int +--* t114 int Generating: N199 ( 3, 6) [000115] -----+----- t115 = * AND int REG x1 Mapped BB10 to G_M47640_IG12 IN0027: and w1, w2, #0x3FFFFFF /--* t115 int Generating: N201 ( 7, 9) [000116] DA---+----- * STORE_LCL_VAR int V06 tmp5 d:1 x1 REG x1 $VN.Void V06 in reg x1 is becoming live [000116] Live regs: 0000000000000005 {x0 x2} + {x1} => 0000000000000007 {x0 x1 x2} Live vars after [000116]: {V02 V05} +{V06} => {V02 V05 V06} genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N203 (???,???) [000298] ----------- IL_OFFSET void INL01 @ 0x06F[E-] <- INLRT @ 0x000[E-] REG NA Generating: N205 ( 1, 1) [000117] -----+----- t117 = LCL_VAR int V05 tmp4 u:1 x2 (last use) REG x2 Generating: N207 ( 1, 4) [000121] -c---+----- t121 = CNS_INT int 0xC000000 REG NA $4a /--* t117 int +--* t121 int Generating: N209 ( 3, 6) [000122] -----+----- t122 = * AND int REG x2 V05 in reg x2 is becoming dead [000117] Live regs: 0000000000000007 {x0 x1 x2} - {x2} => 0000000000000003 {x0 x1} Live vars after [000117]: {V02 V05 V06} -{V05} => {V02 V06} IN0028: and w2, w2, #0xC000000 Generating: N211 ( 1, 4) [000123] -----+----- t123 = CNS_INT int 0x8000000 REG x3 $46 IN0029: mov w3, #0x8000000 /--* t122 int +--* t123 int Generating: N213 ( 5, 11) [000124] -----+-N--- * CMP void REG NA IN002a: cmp w2, w3 Generating: N215 ( 7, 13) [000041] -----+----- JCC void cond=UNE REG NA IN002b: bne (LARGEJMP)L_M47640_BB11 Variable Live Range History Dump for BB10 ..None.. =============== Generating BB12 [0011] [000..001) -> BB13(0.5),BB14(0.5) (cond), preds={BB10} succs={BB14,BB13} flags=0x00000000.00000411: i LIR nullcheck BB12 IN (2)={V02 V06} + ByrefExposed + GcHeap OUT(1)={ V07 } + ByrefExposed + GcHeap Recording Var Locations at start of BB12 V02(x0) V06(x1) Liveness not changing: 0000000000002004 {V02 V06} Live regs: 0000000000000000 {} + {x0 x1} => 0000000000000003 {x0 x1} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB12: Scope info: begin block BB12, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N219 (???,???) [000302] ----------- IL_OFFSET void INL09 @ 0x000[E-] <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA Generating: N221 ( 2, 8) [000133] H----+----- t133 = CNS_INT(h) long 0x4208C8 static base addr cell REG x2 $142 Mapped BB12 to G_M47640_IG12 IN002c: adrp x2, [HIGH RELOC #0x4208C8] IN002d: add x2, x2, [LOW RELOC #0x4208C8] /--* t133 long Generating: N223 ( 5, 10) [000134] #----+----- t134 = * IND long REG x2 $380 IN002e: ldr x2, [x2] /--* t134 long Generating: N225 ( 7, 13) [000136] -c---+----- t136 = * LEA(b+16) long REG NA /--* t136 long Generating: N227 ( 8, 12) [000137] ---XG+----- t137 = * IND ref REG x2 IN002f: ldr x2, [x2, #0x10] GC regs: 0000 {} => 0004 {x2} /--* t137 ref Generating: N229 ( 8, 12) [000138] DA-XG+----- * STORE_LCL_VAR ref V13 tmp12 d:2 x2 REG x2 $289 GC regs: 0004 {x2} => 0000 {} V13 in reg x2 is becoming live [000138] Live regs: 0000000000000003 {x0 x1} + {x2} => 0000000000000007 {x0 x1 x2} Live vars after [000138]: {V02 V06} +{V13} => {V02 V06 V13} GC regs: 0000 {} => 0004 {x2} genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N231 (???,???) [000303] ----------- IL_OFFSET void INL09 @ ??? <- INL08 @ 0x000[E-] <- INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA Generating: N233 ( 1, 1) [000140] -----+----- t140 = LCL_VAR ref V13 tmp12 u:2 x2 REG x2 /--* t140 ref Generating: N235 ( 2, 2) [000141] ---X-+----- * NULLCHECK byte REG NA IN0030: ldrsb wzr, [x2] genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N237 (???,???) [000304] ----------- IL_OFFSET void INL01 @ 0x080[E-] <- INLRT @ 0x000[E-] REG NA Generating: N239 ( 1, 1) [000139] -----+----- t139 = LCL_VAR ref V13 tmp12 u:2 x2 (last use) REG x2 Generating: N241 ( 1, 2) [000234] -c---+----- t234 = CNS_INT long 16 REG NA $1c3 /--* t139 ref +--* t234 long Generating: N243 ( 2, 5) [000235] -----+-N--- t235 = * ADD byref REG x2 V13 in reg x2 is becoming dead [000139] Live regs: 0000000000000007 {x0 x1 x2} - {x2} => 0000000000000003 {x0 x1} Live vars after [000139]: {V02 V06 V13} -{V13} => {V02 V06} GC regs: 0004 {x2} => 0000 {} Removing saved instruction in current IG G_M47640_IG12: > IN0030: ldrsb wzr, [x2] IN0030: ldrsb wzr, [x2], #0x10 Byref regs: 0000 {} => 0004 {x2} Generating: N245 ( 3, 2) [000126] -----+----- t126 = LCL_VAR int V06 tmp5 u:1 x1 (last use) REG x1 /--* t126 int Generating: N247 ( 4, 4) [000144] -c---+----- t144 = * CAST long <- int REG NA Generating: N249 ( 1, 2) [000145] -c---+----- t145 = CNS_INT long 5 REG NA $1c4 /--* t144 long +--* t145 long Generating: N251 ( 6, 7) [000146] -----+----- t146 = * BFIZ long REG x1 V06 in reg x1 is becoming dead [000126] Live regs: 0000000000000003 {x0 x1} - {x1} => 0000000000000001 {x0} Live vars after [000126]: {V02 V06} -{V06} => {V02} IN0031: sbfiz x1, x1, #5, #32 /--* t235 byref +--* t146 long Generating: N253 ( 9, 13) [000147] -c---+----- t147 = * LEA(b+(i*1)+0) byref REG NA /--* t147 byref Generating: N255 ( 11, 14) [000130] ---XG+----- t130 = * IND ref REG x1 Byref regs: 0004 {x2} => 0000 {} IN0032: ldr x1, [x2, x1] GC regs: 0000 {} => 0002 {x1} /--* t130 ref Generating: N257 ( 11, 14) [000045] DA-XG+----- * STORE_LCL_VAR ref V07 tmp6 d:2 x1 REG x1 GC regs: 0002 {x1} => 0000 {} V07 in reg x1 is becoming live [000045] Live regs: 0000000000000001 {x0} + {x1} => 0000000000000003 {x0 x1} Live vars after [000045]: {V02} +{V07} => {V02 V07} GC regs: 0000 {} => 0002 {x1} genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N259 (???,???) [000305] ----------- IL_OFFSET void INL01 @ 0x088[E-] <- INLRT @ 0x000[E-] REG NA Generating: N261 ( 1, 2) [000047] -c---+----- t47 = CNS_INT long 0 REG NA $1c2 /--* t47 long Generating: N263 ( 1, 3) [000048] DA---+----- * STORE_LCL_VAR byref V03 tmp2 NA REG NA $VN.Void IN0033: str xzr, [fp, #0x18] // [V03 tmp2] genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N265 (???,???) [000306] ----------- IL_OFFSET void INL10 @ 0x000[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N267 ( 1, 1) [000049] -----+----- t49 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t49 ref Generating: N269 ( 3, 4) [000238] -c---+----- t238 = * LEA(b+16) byref REG NA /--* t238 byref Generating: N271 ( 4, 3) [000150] ---XG+----- t150 = * IND int REG x2 IN0034: ldr w2, [x1, #0x10] Generating: N273 ( 1, 1) [000050] -----+----- t50 = LCL_VAR int V02 tmp1 u:2 x0 (last use) REG x0 /--* t150 int +--* t50 int Generating: N275 ( 6, 5) [000151] ---XG+-N--- * CMP void REG NA V02 in reg x0 is becoming dead [000050] Live regs: 0000000000000003 {x0 x1} - {x0} => 0000000000000002 {x1} Live vars after [000050]: {V02 V07} -{V02} => {V07} IN0035: cmp w2, w0 Generating: N277 ( 8, 7) [000152] ---XG+----- JCC void cond=UNE REG NA IN0036: bne (LARGEJMP)L_M47640_BB13 Variable Live Range History Dump for BB12 ..None.. =============== Generating BB14 [0026] [000..001) -> BB15(0.5),BB17(0.5) (cond), preds={BB12} succs={BB17,BB15} flags=0x00000000.00000011: i LIR BB14 IN (1)={V07 } + ByrefExposed + GcHeap OUT(2)={V07 V21} + ByrefExposed + GcHeap Recording Var Locations at start of BB14 V07(x1) Liveness not changing: 0000000000000100 {V07} Live regs: 0000000000000000 {} + {x1} => 0000000000000002 {x1} GC regs: 0000 {} => 0002 {x1} Byref regs: (unchanged) 0000 {} L_M47640_BB14: Scope info: begin block BB14, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N281 (???,???) [000308] ----------- IL_OFFSET void INL11 @ 0x000[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N283 ( 1, 1) [000153] ----------- t153 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t153 ref Generating: N285 ( 3, 4) [000240] -c--------- t240 = * LEA(b+24) byref REG NA /--* t240 byref Generating: N287 ( 4, 3) [000158] n---GO----- t158 = * IND int REG x0 Mapped BB14 to G_M47640_IG12 IN0037: ldr w0, [x1, #0x18] /--* t158 int Generating: N289 ( 8, 6) [000259] DA--GO----- * STORE_LCL_VAR int V21 cse0 d:1 x0 REG x0 V21 in reg x0 is becoming live [000259] Live regs: 0000000000000002 {x1} + {x0} => 0000000000000003 {x0 x1} Live vars after [000259]: {V07} +{V21} => {V07 V21} Generating: N291 ( 3, 2) [000260] ----------- t260 = LCL_VAR int V21 cse0 u:1 x0 REG x0 Generating: N293 ( 1, 2) [000159] -c--------- t159 = CNS_INT int 0 REG NA $40 /--* t260 int +--* t159 int Generating: N295 ( 15, 13) [000161] -A--GO----- * JCMP void REG NA IN0038: cbz (LARGEJMP)L_M47640_BB15 Variable Live Range History Dump for BB14 ..None.. =============== Generating BB17 [0031] [000..001) -> BB18(1) (always), preds={BB14} succs={BB18} flags=0x00000000.00000011: i LIR BB17 IN (2)={V07 V21} OUT(0)={ } Recording Var Locations at start of BB17 V07(x1) V21(x0) Liveness not changing: 0000000000001100 {V07 V21} Live regs: 0000000000000000 {} + {x0 x1} => 0000000000000003 {x0 x1} GC regs: 0000 {} => 0002 {x1} Byref regs: (unchanged) 0000 {} L_M47640_BB17: Scope info: begin block BB17, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N299 (???,???) [000314] ----------- IL_OFFSET void INL11 @ 0x027[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N301 ( 3, 2) [000262] ----------- t262 = LCL_VAR int V21 cse0 u:1 x0 (last use) REG x0 Generating: N303 ( 1, 2) [000166] -c--------- t166 = CNS_INT int -1 REG NA $41 /--* t262 int +--* t166 int Generating: N305 ( 5, 5) [000167] ----G------ t167 = * ADD int REG x0 V21 in reg x0 is becoming dead [000262] Live regs: 0000000000000003 {x0 x1} - {x0} => 0000000000000002 {x1} Live vars after [000262]: {V07 V21} -{V21} => {V07} Mapped BB17 to G_M47640_IG12 IN0039: sub w0, w0, #1 Generating: N307 ( 1, 1) [000162] ----------- t162 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t162 ref Generating: N309 ( 3, 4) [000242] -c--------- t242 = * LEA(b+24) byref REG NA /--* t242 byref +--* t167 int Generating: N311 ( 10, 9) [000169] nA--GO----- * STOREIND int REG NA V07 in reg x1 is becoming dead [000162] Live regs: 0000000000000002 {x1} - {x1} => 0000000000000000 {} Live vars after [000162]: {V07} -{V07} => {} GC regs: 0002 {x1} => 0000 {} IN003a: str w0, [x1, #0x18] IN003b: b L_M47640_BB18 Variable Live Range History Dump for BB17 ..None.. =============== Generating BB15 [0029] [000..001) -> BB18(0.5),BB16(0.5) (cond), preds={BB14} succs={BB16,BB18} flags=0x00000000.00004411: i LIR label nullcheck BB15 IN (1)={V07 } + ByrefExposed + GcHeap OUT(2)={V07 V19} + ByrefExposed + GcHeap Recording Var Locations at start of BB15 V07(x1) Change life 0000000000000000 {} -> 0000000000000100 {V07} V07 in reg x1 is becoming live [------] Live regs: 0000000000000000 {} + {x1} => 0000000000000002 {x1} Live regs: (unchanged) 0000000000000002 {x1} GC regs: (unchanged) 0002 {x1} Byref regs: (unchanged) 0000 {} L_M47640_BB15: Saved: G_M47640_IG12: ; offs=0x0001B8, size=0x0060, bbWeight=0.50, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB10 [0009], BB12 [0011], BB14 [0026], BB17 [0031], gcvars, byref Created: G_M47640_IG13: ; offs=0x000218, size=0x0000, bbWeight=0.50, gcrefRegs=0000 {} Label: G_M47640_IG13, GCvars=0000000000000000 {}, gcrefRegs=0002 {x1}, byrefRegs=0000 {} Scope info: begin block BB15, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N315 (???,???) [000309] ----------- IL_OFFSET void INL11 @ 0x008[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N317 ( 1, 1) [000170] ----------- t170 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 /--* t170 ref Generating: N319 ( 3, 4) [000246] -c--------- t246 = * LEA(b+16) byref REG NA Generating: N321 ( 1, 2) [000171] -c--------- t171 = CNS_INT int 0 REG NA $40 /--* t246 byref +--* t171 int Generating: N323 ( 6, 6) [000173] nA--GO----- * STOREIND int REG NA Mapped BB15 to G_M47640_IG13 IN003c: str wzr, [x1, #0x10] genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N325 (???,???) [000310] ----------- IL_OFFSET void INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N327 ( 1, 1) [000249] -----+----- t249 = LCL_VAR ref V07 tmp6 u:2 x1 REG x1 Generating: N329 ( 1, 2) [000250] -c---+----- t250 = CNS_INT long 20 Fseq[_state] REG NA $1c6 /--* t249 ref +--* t250 long Generating: N331 ( 3, 4) [000251] -----+----- t251 = * ADD byref REG x0 IN003d: add x0, x1, #20 Byref regs: 0000 {} => 0001 {x0} Generating: N333 ( 1, 2) [000203] -c---+----- t203 = CNS_INT int -1 REG NA $41 /--* t251 byref +--* t203 int Generating: N335 ( 5, 7) [000204] -A-XG+----- t204 = * XADD int REG x4 Byref regs: 0001 {x0} => 0000 {} Byref regs: 0000 {} => 0001 {x0} New Basic Block BB26 [0046] created. Mark BB26 as label: codegen temp block L_M47640_BB26: Saved: G_M47640_IG13: ; offs=0x000218, size=0x0008, bbWeight=0.50, gcrefRegs=0002 {x1}, byrefRegs=0000 {}, BB15 [0029], byref Created: G_M47640_IG14: ; offs=0x000220, size=0x0000, bbWeight=0.50, gcrefRegs=0000 {} Label: G_M47640_IG14, GCvars=0000000000000000 {}, gcrefRegs=0002 {x1}, byrefRegs=0001 {x0} Mapped BB15 to G_M47640_IG14 IN003e: ldaxr w4, [x0] IN003f: sub w3, w4, #1 IN0040: stlxr w2, w3, [x0] IN0041: cbnz (LARGEJMP)L_M47640_BB26 IN0042: dmb ish Byref regs: 0001 {x0} => 0000 {} Generating: N337 ( 1, 2) [000205] -c---+----- t205 = CNS_INT int -1 REG NA $41 /--* t204 int +--* t205 int Generating: N339 ( 7, 10) [000206] -A-XG+----- t206 = * ADD int REG x0 IN0043: sub w0, w4, #1 /--* t206 int Generating: N341 ( 7, 10) [000212] DA-XG+----- * STORE_LCL_VAR int V17 tmp16 d:1 x0 REG x0 V17 in reg x0 is becoming live [000212] Live regs: 0000000000000002 {x1} + {x0} => 0000000000000003 {x0 x1} Live vars after [000212]: {V07} +{V17} => {V07 V17} genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N343 (???,???) [000311] ----------- IL_OFFSET void INL15 @ 0x000[E-] <- INL12 @ ??? <- INL11 @ 0x00F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N345 ( 1, 1) [000209] -----+----- t209 = LCL_VAR int V17 tmp16 u:1 x0 (last use) REG x0 $13a /--* t209 int Generating: N347 ( 5, 4) [000211] DA---+----- * STORE_LCL_VAR int V19 tmp18 d:1 x2 REG x2 $VN.Void V17 in reg x0 is becoming dead [000209] Live regs: 0000000000000003 {x0 x1} - {x0} => 0000000000000002 {x1} Live vars after [000209]: {V07 V17} -{V17} => {V07} IN0044: sxtw w2, w0 V19 in reg x2 is becoming live [000211] Live regs: 0000000000000002 {x1} + {x2} => 0000000000000006 {x1 x2} Live vars after [000211]: {V07} +{V19} => {V07 V19} genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N349 (???,???) [000312] ----------- IL_OFFSET void INL11 @ 0x016[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N351 ( 1, 1) [000216] -----+----- t216 = LCL_VAR int V19 tmp18 u:1 x2 REG x2 $13a Generating: N353 ( 1, 2) [000217] -c---+----- t217 = CNS_INT int 128 REG NA $4d /--* t216 int +--* t217 int Generating: N355 ( 3, 4) [000218] -----+-N-U- * CMP void REG NA IN0045: cmp w2, #128 Generating: N357 ( 5, 6) [000183] -----+----- JCC void cond=ULT REG NA IN0046: blo (LARGEJMP)L_M47640_BB18 Variable Live Range History Dump for BB15 ..None.. =============== Generating BB16 [0030] [000..001) -> BB18(1) (always), preds={BB15} succs={BB18} flags=0x00000000.08040011: i LIR hascall gcsafe BB16 IN (2)={V07 V19} + ByrefExposed + GcHeap OUT(0)={ } Recording Var Locations at start of BB16 V07(x1) V19(x2) Liveness not changing: 0000000000000900 {V07 V19} Live regs: 0000000000000000 {} + {x1 x2} => 0000000000000006 {x1 x2} GC regs: 0000 {} => 0002 {x1} Byref regs: (unchanged) 0000 {} L_M47640_BB16: Scope info: begin block BB16, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N361 (???,???) [000313] ----------- IL_OFFSET void INL11 @ 0x01F[E-] <- INL10 @ 0x00E[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N363 ( 1, 1) [000184] -----+----- t184 = LCL_VAR ref V07 tmp6 u:2 x1 (last use) REG x1 /--* t184 ref Generating: N365 (???,???) [000322] ----------- t322 = * PUTARG_REG ref REG x0 V07 in reg x1 is becoming dead [000184] Live regs: 0000000000000006 {x1 x2} - {x1} => 0000000000000004 {x2} Live vars after [000184]: {V07 V19} -{V07} => {V19} GC regs: 0002 {x1} => 0000 {} Mapped BB16 to G_M47640_IG14 IN0047: mov x0, x1 GC regs: 0000 {} => 0001 {x0} Generating: N367 ( 3, 2) [000185] -----+----- t185 = LCL_VAR int V19 tmp18 u:1 x2 (last use) REG x2 $13a /--* t185 int Generating: N369 (???,???) [000323] ----------- t323 = * PUTARG_REG int REG x1 V19 in reg x2 is becoming dead [000185] Live regs: 0000000000000004 {x2} - {x2} => 0000000000000000 {} Live vars after [000185]: {V19} -{V19} => {} IN0048: mov w1, w2 /--* t322 ref this in x0 +--* t323 int arg1 in x1 Generating: N371 ( 18, 7) [000186] --CXG+----- * CALL void System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this REG NA $VN.Void GC regs: 0001 {x0} => 0000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} IN0049: bl System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this IN004a: b L_M47640_BB18 Variable Live Range History Dump for BB16 ..None.. =============== Generating BB13 [0025] [000..001) (throw), preds={BB12} succs={} flags=0x00000000.08044011: i LIR label hascall gcsafe BB13 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} Recording Var Locations at start of BB13 Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB13: Saved: G_M47640_IG14: ; offs=0x000220, size=0x003C, bbWeight=0.50, gcrefRegs=0002 {x1}, byrefRegs=0001 {x0}, BB15 [0029], BB16 [0030], byref Created: G_M47640_IG15: ; offs=0x00025C, size=0x0000, bbWeight=0.50, gcrefRegs=0000 {} Label: G_M47640_IG15, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB13, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N375 (???,???) [000307] ----------- IL_OFFSET void INL10 @ 0x009[E-] <- INL01 @ 0x08B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N377 ( 14, 2) [000155] --CXG+----- CALL void System.ThrowHelper:ThrowSynchronizationLockException_LockExit() REG NA $VN.Void Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Mapped BB13 to G_M47640_IG15 IN004b: bl System.ThrowHelper:ThrowSynchronizationLockException_LockExit() IN004c: brk #0 Variable Live Range History Dump for BB13 ..None.. =============== Generating BB02 [0014] [000..001) (throw), preds={BB01} succs={} flags=0x00000000.08044011: i LIR label hascall gcsafe BB02 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} Recording Var Locations at start of BB02 Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB02: Saved: G_M47640_IG15: ; offs=0x00025C, size=0x0008, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB13 [0025], byref Created: G_M47640_IG16: ; offs=0x000264, size=0x0000, bbWeight=0.50, gcrefRegs=0000 {} Label: G_M47640_IG16, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB02, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N421 (???,???) [000282] ----------- IL_OFFSET void INL02 @ 0x003[E-] <- INL01 @ 0x000[E-] <- INLRT @ 0x000[E-] REG NA Generating: N423 ( 2, 8) [000222] H----+----- t222 = CNS_INT(h) ref '"obj"' REG x0 $500 Mapped BB02 to G_M47640_IG16 IN004d: adrp x0, [HIGH RELOC #0x420A80] // '"obj"' IN004e: add x0, x0, [LOW RELOC #0x420A80] GC regs: 0000 {} => 0001 {x0} /--* t222 ref Generating: N425 (???,???) [000317] ----------- t317 = * PUTARG_REG ref REG x0 GC regs: 0001 {x0} => 0000 {} GC regs: 0000 {} => 0001 {x0} /--* t317 ref arg0 in x0 Generating: N427 ( 16, 11) [000099] --CXG+----- * CALL void System.ArgumentNullException:Throw(System.String) REG NA $VN.Void GC regs: 0001 {x0} => 0000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} IN004f: bl System.ArgumentNullException:Throw(System.String) IN0050: brk #0 Variable Live Range History Dump for BB02 ..None.. =============== Generating BB22 [0042] [???..???) -> BB20(1) (always), preds={BB03} succs={BB20} flags=0x00000000.00005021: LIR rare internal label BB22 IN (2)={ V00 V23} + ByrefExposed + GcHeap OUT(2)={V22 V00 } + ByrefExposed + GcHeap Recording Var Locations at start of BB22 V00(x19) V23(x0) Change life 0000000000000000 {} -> 0000000000000060 {V00 V23} V00 in reg x19 is becoming live [------] Live regs: 0000000000000000 {} + {x19} => 0000000000080000 {x19} Debug: New V00 debug range: new var or location V23 in reg x0 is becoming live [------] Live regs: 0000000000080000 {x19} + {x0} => 0000000000080001 {x0 x19} Live regs: (unchanged) 0000000000080001 {x0 x19} GC regs: (unchanged) 80000 {x19} Byref regs: (unchanged) 0000 {} L_M47640_BB22: Saved: G_M47640_IG16: ; offs=0x000264, size=0x0010, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0014], byref Created: G_M47640_IG17: ; offs=0x000274, size=0x0000, bbWeight=0, gcrefRegs=0000 {} Label: G_M47640_IG17, GCvars=0000000000000000 {}, gcrefRegs=80000 {x19}, byrefRegs=0000 {} Scope info: begin block BB22, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M47640_IG17,ins#0,ofs#0) label Added IP mapping: 0x0000 STACK_EMPTY (G_M47640_IG17,ins#0,ofs#0) label Generating: N043 (???,???) [000284] ----------- IL_OFFSET void INL01 @ 0x00B[E-] <- INLRT @ 0x000[E-] REG NA Generating: N045 ( 3, 2) [000277] ----------- t277 = LCL_VAR long V23 rat1 x0 (last use) REG x0 /--* t277 long Generating: N047 (???,???) [000318] ----------- t318 = * PUTARG_REG long REG x0 V23 in reg x0 is becoming dead [000277] Live regs: 0000000000080001 {x0 x19} - {x0} => 0000000000080000 {x19} Live vars after [000277]: {V00 V23} -{V23} => {V00} Generating: N049 ( 2, 8) [000275] H---------- t275 = CNS_INT(h) long 0x420488 tls REG x1 Mapped BB22 to G_M47640_IG17 IN0051: adrp x1, [HIGH RELOC #0x420488] IN0052: add x1, x1, [LOW RELOC #0x420488] /--* t318 long arg0 in x0 +--* t275 long calli tgt Generating: N051 ( 22, 13) [000276] --CXG------ t276 = * CALL ind ref REG x0 Call: GCvars=0000000000000000 {}, gcrefRegs=80000 {x19}, byrefRegs=0000 {} IN0053: blr x1 GC regs: 80000 {x19} => 80001 {x0 x19} /--* t276 ref Generating: N053 ( 26, 16) [000278] DACXG------ * STORE_LCL_VAR ref V22 rat0 x20 REG x20 GC regs: 80001 {x0 x19} => 80000 {x19} IN0054: mov x20, x0 V22 in reg x20 is becoming live [000278] Live regs: 0000000000080000 {x19} + {x20} => 0000000000180000 {x19 x20} Live vars after [000278]: {V00} +{V22} => {V00 V22} GC regs: 80000 {x19} => 180000 {x19 x20} Scope info: ignoring block end IN0055: b L_M47640_BB20 Variable Live Range History Dump for BB22 V00 arg0: x19 [(G_M47640_IG16,ins#4,ofs#16), ...] =============== Generating BB11 [0010] [000..001) (throw), preds={BB10} succs={} flags=0x00000000.08445011: i LIR rare label hascall gcsafe newobj BB11 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} Recording Var Locations at start of BB11 Change life 0000000000000028 {V00 V22} -> 0000000000000000 {} V22 in reg x20 is becoming dead [------] Live regs: (unchanged) 0000000000000000 {} V00 in reg x19 is becoming dead [------] Live regs: (unchanged) 0000000000000000 {} Debug: Closing V00 debug range. Live regs: (unchanged) 0000000000000000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M47640_BB11: Saved: G_M47640_IG17: ; offs=0x000274, size=0x0014, bbWeight=0, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, BB22 [0042], byref Created: G_M47640_IG18: ; offs=0x000288, size=0x0000, bbWeight=0, gcrefRegs=0000 {} Label: G_M47640_IG18, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB11, IL range [000..001) genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N381 (???,???) [000299] ----------- IL_OFFSET void INL01 @ 0x07A[E-] <- INLRT @ 0x000[E-] REG NA Generating: N383 ( 2, 8) [000052] H----+----- t52 = CNS_INT(h) long 0x420818 class REG x0 $147 Mapped BB11 to G_M47640_IG18 IN0056: adrp x0, [HIGH RELOC #0x420818] // System.Threading.SynchronizationLockException IN0057: add x0, x0, [LOW RELOC #0x420818] /--* t52 long Generating: N385 (???,???) [000319] ----------- t319 = * PUTARG_REG long REG x0 /--* t319 long arg0 in x0 Generating: N387 ( 16, 11) [000053] --C--+----- t53 = * CALL help ref CORINFO_HELP_NEWSFAST REG x0 $298 Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} IN0058: bl CORINFO_HELP_NEWSFAST GC regs: 0000 {} => 0001 {x0} /--* t53 ref Generating: N389 ( 20, 14) [000054] DAC--+----- * STORE_LCL_VAR ref V08 tmp7 d:2 x19 REG x19 $VN.Void GC regs: 0001 {x0} => 0000 {} IN0059: mov x19, x0 V08 in reg x19 is becoming live [000054] Live regs: 0000000000000000 {} + {x19} => 0000000000080000 {x19} Live vars after [000054]: {} +{V08} => {V08} GC regs: 0000 {} => 80000 {x19} genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N391 (???,???) [000300] ----------- IL_OFFSET void INL01 @ ??? <- INLRT @ 0x000[E-] REG NA Generating: N393 ( 3, 2) [000055] -----+----- t55 = LCL_VAR ref V08 tmp7 u:2 x19 REG x19 $298 /--* t55 ref Generating: N395 (???,???) [000320] ----------- t320 = * PUTARG_REG ref REG x0 -- suppressing mov because previous instruction already did an opposite move from dst to src register. GC regs: 80000 {x19} => 80001 {x0 x19} /--* t320 ref this in x0 Generating: N397 ( 17, 5) [000056] --CXG+----- * CALL void System.Threading.SynchronizationLockException:.ctor():this REG NA $VN.Void GC regs: 80001 {x0 x19} => 80000 {x19} Call: GCvars=0000000000000000 {}, gcrefRegs=80000 {x19}, byrefRegs=0000 {} IN005a: bl System.Threading.SynchronizationLockException:.ctor():this genIPmappingAdd: ignoring duplicate IL offset 0x0 Generating: N399 (???,???) [000301] ----------- IL_OFFSET void INL01 @ 0x07F[--] <- INLRT @ 0x000[E-] REG NA Generating: N401 ( 3, 2) [000057] -----+----- t57 = LCL_VAR ref V08 tmp7 u:2 x19 (last use) REG x19 $298 /--* t57 ref Generating: N403 (???,???) [000321] ----------- t321 = * PUTARG_REG ref REG x0 V08 in reg x19 is becoming dead [000057] Live regs: 0000000000080000 {x19} - {x19} => 0000000000000000 {} Live vars after [000057]: {V08} -{V08} => {} GC regs: 80000 {x19} => 0000 {} IN005b: mov x0, x19 GC regs: 0000 {} => 0001 {x0} /--* t321 ref arg0 in x0 Generating: N405 ( 17, 5) [000058] --CXG+----- * CALL help void CORINFO_HELP_THROW REG NA $29a GC regs: 0001 {x0} => 0000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} IN005c: bl CORINFO_HELP_THROW IN005d: brk #0 Variable Live Range History Dump for BB11 V00 arg0: x19 [(G_M47640_IG16,ins#4,ofs#16), (G_M47640_IG17,ins#5,ofs#20)] Liveness not changing: 0000000000000000 {} # compCycleEstimate = 578, compSizeEstimate = 282 System.Threading.Monitor:Exit(System.Object) ; Final local variable assignments ; ; V00 arg0 [V00,T05] ( 4, 4 ) ref -> x19 class-hnd single-def ;# V01 OutArgs [V01 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V02 tmp1 [V02,T02] ( 6, 12.50) int -> x0 "Inline stloc first use temp" ; V03 tmp2 [V03 ] ( 4, 3.50) byref -> [fp+0x18] must-init pinned "Inline stloc first use temp" ; V04 tmp3 [V04,T01] ( 3, 13 ) long -> x1 "Inline stloc first use temp" ; V05 tmp4 [V05,T00] ( 10, 37 ) int -> x2 "Inline stloc first use temp" ; V06 tmp5 [V06,T13] ( 2, 1 ) int -> x1 ld-addr-op "Inline ldloca(s) first use temp" ; V07 tmp6 [V07,T08] ( 7, 3.50) ref -> x1 class-hnd exact single-def "Inline stloc first use temp" ; V08 tmp7 [V08,T14] ( 3, 0 ) ref -> x19 class-hnd exact single-def "NewObj constructor temp" ; V09 tmp8 [V09,T04] ( 3, 8 ) int -> x3 ;* V10 tmp9 [V10 ] ( 0, 0 ) int -> zero-ref "Inline stloc first use temp" ;* V11 tmp10 [V11 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V12 tmp11 [V12 ] ( 0, 0 ) int -> zero-ref "Inlining Arg" ; V13 tmp12 [V13,T09] ( 3, 3 ) ref -> x2 single-def "MemoryMarshal.GetArrayDataReference array" ;* V14 tmp13 [V14 ] ( 0, 0 ) struct ( 8) zero-ref ld-addr-op "Inline stloc first use temp" ;* V15 tmp14 [V15 ] ( 0, 0 ) struct ( 8) zero-ref ld-addr-op "NewObj constructor temp" ;* V16 tmp15 [V16 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V17 tmp16 [V17,T10] ( 2, 2 ) int -> x0 "Inlining Arg" ;* V18 tmp17 [V18 ] ( 0, 0 ) int -> zero-ref "field V14._state (fldOffset=0x0)" P-INDEP ; V19 tmp18 [V19,T11] ( 3, 1.50) int -> x2 "field V15._state (fldOffset=0x0)" P-INDEP ; V20 tmp19 [V20,T07] ( 2, 4 ) long -> x1 "Cast away GC" ; V21 cse0 [V21,T12] ( 3, 1.50) int -> x0 "CSE #01: moderate" ; V22 rat0 [V22,T03] ( 6, 10 ) ref -> x20 "Final offset" ; V23 rat1 [V23,T06] ( 3, 4 ) long -> x0 "TlsRootAddr access" ; ; Lcl frame size = 16 *************** Before prolog / epilog generation G_M47640_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG G_M47640_IG02: ; offs=0x000000, size=0x002C, bbWeight=1, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, BB01 [0000], BB03 [0015], byref G_M47640_IG03: ; offs=0x00002C, size=0x0028, bbWeight=1, gcrefRegs=180000 {x19 x20}, byrefRegs=0000 {}, BB20 [0040], byref, align G_M47640_IG04: ; offs=0x000054, size=0x0014, bbWeight=8, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0002], byref G_M47640_IG05: ; offs=0x000068, size=0x0014, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0003], BB06 [0004], byref G_M47640_IG06: ; offs=0x00007C, size=0x0008, bbWeight=2, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB07 [0005], byref G_M47640_IG07: ; offs=0x000084, size=0x0004, bbWeight=2, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB08 [0006], byref G_M47640_IG08: ; offs=0x000088, size=0x001C, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB09 [0007], byref G_M47640_IG09: ; offs=0x0000A4, size=0x0010, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, loop=IG04, BB09 [0007], byref G_M47640_IG10: ; offs=0x0000B4, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB18 [0039], byref G_M47640_IG11: ; epilog placeholder, next placeholder=, BB18 [0039], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {} G_M47640_IG12: ; offs=0x0001B8, size=0x0060, bbWeight=0.50, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB10 [0009], BB12 [0011], BB14 [0026], BB17 [0031], gcvars, byref G_M47640_IG13: ; offs=0x000218, size=0x0008, bbWeight=0.50, gcrefRegs=0002 {x1}, byrefRegs=0000 {}, BB15 [0029], byref G_M47640_IG14: ; offs=0x000220, size=0x003C, bbWeight=0.50, gcrefRegs=0002 {x1}, byrefRegs=0001 {x0}, BB15 [0029], BB16 [0030], byref G_M47640_IG15: ; offs=0x00025C, size=0x0008, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB13 [0025], byref G_M47640_IG16: ; offs=0x000264, size=0x0010, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0014], byref G_M47640_IG17: ; offs=0x000274, size=0x0014, bbWeight=0, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, BB22 [0042], byref G_M47640_IG18: ; offs=0x000288, size=0x0000, bbWeight=0, gcrefRegs=0000 {}, BB11 [0010] <-- Current IG Recording Var Locations at start of BB01 V00(x19) Saved: G_M47640_IG18: ; offs=0x000288, size=0x0020, bbWeight=0, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB11 [0010], byref *************** In genFnProlog() Added IP mapping to front: PROLOG (G_M47640_IG01,ins#0,ofs#0) label __prolog: Debug: New V00 debug range: first Found 2 lvMustInit int-sized stack slots, frame offsets -24 through -32 Save float regs: [] Save int regs: [x19-x20 fp lr] Frame type 1. #outsz=0; #framesz=48; LclFrameSize=16 IN005e: stp fp, lr, [sp, #-0x30]! offset=32, calleeSaveSpDelta=0 IN005f: stp x19, x20, [sp, #0x20] offsetSpToSavedFp=0 IN0060: mov fp, sp IN0061: str xzr, [fp, #0x18] // [V03 tmp2] *************** In genHomeRegisterParams() 2 registers in register parameter interference graph x0 x19 <- x0 IN0062: mov x19, x0 *************** In genEnregisterIncomingStackArgs() Debug: Closing V00 debug range. Saved: G_M47640_IG01: ; offs=0x000000, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {} Frame type 1. #outsz=0; #framesz=48; localloc? false calleeSaveSpOffset=32, calleeSaveSpDelta=0 IN0063: ldp x19, x20, [sp, #0x20] IN0064: ldp fp, lr, [sp], #0x30 IN0065: ret lr Saved: G_M47640_IG11: ; offs=0x0000B8, size=0x000C, bbWeight=1, epilog, nogc, extend 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M47640_IG01: ; func=00, offs=0x000000, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG G_M47640_IG02: ; offs=0x000014, size=0x002C, bbWeight=1, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, BB01 [0000], BB03 [0015], byref G_M47640_IG03: ; offs=0x000040, size=0x0028, bbWeight=1, gcrefRegs=180000 {x19 x20}, byrefRegs=0000 {}, BB20 [0040], byref, align G_M47640_IG04: ; offs=0x000068, size=0x0014, bbWeight=8, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0002], byref G_M47640_IG05: ; offs=0x00007C, size=0x0014, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0003], BB06 [0004], byref G_M47640_IG06: ; offs=0x000090, size=0x0008, bbWeight=2, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB07 [0005], byref G_M47640_IG07: ; offs=0x000098, size=0x0004, bbWeight=2, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB08 [0006], byref G_M47640_IG08: ; offs=0x00009C, size=0x001C, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB09 [0007], byref G_M47640_IG09: ; offs=0x0000B8, size=0x0010, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, loop=IG04, BB09 [0007], byref G_M47640_IG10: ; offs=0x0000C8, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB18 [0039], byref G_M47640_IG11: ; offs=0x0000CC, size=0x000C, bbWeight=1, epilog, nogc, extend G_M47640_IG12: ; offs=0x0000D8, size=0x0060, bbWeight=0.50, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB10 [0009], BB12 [0011], BB14 [0026], BB17 [0031], gcvars, byref G_M47640_IG13: ; offs=0x000138, size=0x0008, bbWeight=0.50, gcrefRegs=0002 {x1}, byrefRegs=0000 {}, BB15 [0029], byref G_M47640_IG14: ; offs=0x000140, size=0x003C, bbWeight=0.50, gcrefRegs=0002 {x1}, byrefRegs=0001 {x0}, BB15 [0029], BB16 [0030], byref G_M47640_IG15: ; offs=0x00017C, size=0x0008, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB13 [0025], byref G_M47640_IG16: ; offs=0x000184, size=0x0010, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0014], byref G_M47640_IG17: ; offs=0x000194, size=0x0014, bbWeight=0, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, BB22 [0042], byref G_M47640_IG18: ; offs=0x0001A8, size=0x0020, bbWeight=0, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB11 [0010], byref *************** In emitJumpDistBind() Emitter Jump List: IG02 IN0001 cbz[8] -> IG16 IG02 IN0009 cbz[8] -> IG17 IG04 IN0017 bne[8] -> IG12 IG05 IN0018 tbnz[8] -> IG12 IG05 IN001a bne[8] -> IG07 IG06 IN001c b[4] -> IG08 IG08 IN0020 bne[8] -> IG09 IG08 IN0022 cbnz[8] -> IG08 IG09 IN0025 bne[8] -> IG04 IG12 IN002b bne[8] -> IG18 IG12 IN0036 bne[8] -> IG15 IG12 IN0038 cbz[8] -> IG13 IG12 IN003b b[4] -> IG10 IG14 IN0041 cbnz[8] -> IG14 IG14 IN0046 blo[8] -> IG10 IG14 IN004a b[4] -> IG10 IG17 IN0055 b[4] -> IG03 total jump count: 17 Binding: IN0001: cbz (LARGEJMP)L_M47640_BB02 Binding L_M47640_BB02 to G_M47640_IG16 Estimate of fwd jump [0043FB14/001]: 0014 -> 0184 = 0170 Shrinking jump [0043FB14/001] Binding: IN0009: cbz (LARGEJMP)L_M47640_BB22 Binding L_M47640_BB22 to G_M47640_IG17 Estimate of fwd jump [0043FC0C/009]: 0034 -> 0190 = 015C Shrinking jump [0043FC0C/009] Adjusted offset of BB03 from 0040 to 0038 Adjusted offset of BB04 from 0068 to 0060 Binding: IN0017: bne (LARGEJMP)L_M47640_BB10 Binding L_M47640_BB10 to G_M47640_IG12 Estimate of fwd jump [0044044C/023]: 006C -> 00D0 = 0064 Shrinking jump [0044044C/023] Adjusted offset of BB05 from 007C to 0070 Binding: IN0018: tbnz (LARGEJMP)L_M47640_BB10 Binding L_M47640_BB10 to G_M47640_IG12 Estimate of fwd jump [0044084C/024]: 0070 -> 00CC = 005C Shrinking jump [0044084C/024] Binding: IN001a: bne (LARGEJMP)L_M47640_BB08 Binding L_M47640_BB08 to G_M47640_IG07 Estimate of fwd jump [004408A4/026]: 0078 -> 0088 = 0010 Shrinking jump [004408A4/026] Adjusted offset of BB06 from 0090 to 007C Binding: IN001c: b L_M47640_BB09 Binding L_M47640_BB09 to G_M47640_IG08 Adjusted offset of BB07 from 0098 to 0084 Adjusted offset of BB08 from 009C to 0088 Binding: IN0020: bne (LARGEJMP)L_M47640_BB25 Binding L_M47640_BB25 to G_M47640_IG09 Estimate of fwd jump [00441414/032]: 0090 -> 00A4 = 0014 Shrinking jump [00441414/032] Binding: IN0022: cbnz (LARGEJMP)L_M47640_BB24 Binding L_M47640_BB24 to G_M47640_IG08 Estimate of bwd jump [00441464/034]: 0098 -> 0088 = 0010 Shrinking jump [00441464/034] Adjusted offset of BB09 from 00B8 to 009C Binding: IN0025: bne (LARGEJMP)L_M47640_BB04 Binding L_M47640_BB04 to G_M47640_IG04 Estimate of bwd jump [0044163C/037]: 00A4 -> 0060 = 0044 Shrinking jump [0044163C/037] Adjusted offset of BB10 from 00C8 to 00A8 Adjusted offset of BB11 from 00CC to 00AC Adjusted offset of BB12 from 00D8 to 00B8 Binding: IN002b: bne (LARGEJMP)L_M47640_BB11 Binding L_M47640_BB11 to G_M47640_IG18 Estimate of fwd jump [004424DC/043]: 00C8 -> 0188 = 00C0 Shrinking jump [004424DC/043] Binding: IN0036: bne (LARGEJMP)L_M47640_BB13 Binding L_M47640_BB13 to G_M47640_IG15 Estimate of fwd jump [0044260C/054]: 00F4 -> 0158 = 0064 Shrinking jump [0044260C/054] Binding: IN0038: cbz (LARGEJMP)L_M47640_BB15 Binding L_M47640_BB15 to G_M47640_IG13 Estimate of fwd jump [00442654/056]: 00FC -> 0110 = 0014 Shrinking jump [00442654/056] Binding: IN003b: b L_M47640_BB18 Binding L_M47640_BB18 to G_M47640_IG10 Adjusted offset of BB13 from 0138 to 010C Adjusted offset of BB14 from 0140 to 0114 Binding: IN0041: cbnz (LARGEJMP)L_M47640_BB26 Binding L_M47640_BB26 to G_M47640_IG14 Estimate of bwd jump [00442EB4/065]: 0120 -> 0114 = 000C Shrinking jump [00442EB4/065] Binding: IN0046: blo (LARGEJMP)L_M47640_BB18 Binding L_M47640_BB18 to G_M47640_IG10 Estimate of bwd jump [00442F3C/070]: 0134 -> 00A8 = 008C Shrinking jump [00442F3C/070] Binding: IN004a: b L_M47640_BB18 Binding L_M47640_BB18 to G_M47640_IG10 Adjusted offset of BB15 from 017C to 0148 Adjusted offset of BB16 from 0184 to 0150 Adjusted offset of BB17 from 0194 to 0160 Binding: IN0055: b L_M47640_BB20 Binding L_M47640_BB20 to G_M47640_IG03 Adjusted offset of BB18 from 01A8 to 0174 Total shrinkage = 52, min extra jump size = 4294967295 *************** In emitLoopAlignAdjustments() compJitAlignLoopAdaptive = true compJitAlignLoopBoundary = 32 compJitAlignLoopMinBlockWeight = 3 compJitAlignLoopForJcc = false compJitAlignLoopMaxCodeSize = 96 compJitAlignPaddingLimit = 16 Adjusting 'align' instruction in IG03 that is targeted for IG04 *************** In getLoopSize() for G_M47640_IG04 G_M47640_IG04 has 16 bytes. G_M47640_IG05 has 12 bytes. G_M47640_IG06 has 8 bytes. G_M47640_IG07 has 4 bytes. G_M47640_IG08 has 20 bytes. G_M47640_IG09 has 12 bytes. -- Found the back edge. loopSize of G_M47640_IG04 = 72 bytes. ;; Skip alignment: 'Loop at G_M47640_IG04 PaddingNeeded= 16, MaxPadding= 4, LoopSize= 72, AlignmentBoundary= 32B.' ;; Calculated padding to add 0 bytes to align G_M47640_IG04 at 32B boundary. Adjusted alignment for G_M47640_IG04 from 16 to 0. Adjusted size of G_M47640_IG03 from 40 to 24. Adjusted offset of G_M47640_IG04 from 0060 to 0050 Adjusted offset of G_M47640_IG05 from 0070 to 0060 Adjusted offset of G_M47640_IG06 from 007C to 006C Adjusted offset of G_M47640_IG07 from 0084 to 0074 Adjusted offset of G_M47640_IG08 from 0088 to 0078 Adjusted offset of G_M47640_IG09 from 009C to 008C Adjusted offset of G_M47640_IG10 from 00A8 to 0098 Adjusted offset of G_M47640_IG11 from 00AC to 009C Adjusted offset of G_M47640_IG12 from 00B8 to 00A8 Adjusted offset of G_M47640_IG13 from 010C to 00FC Adjusted offset of G_M47640_IG14 from 0114 to 0104 Adjusted offset of G_M47640_IG15 from 0148 to 0138 Adjusted offset of G_M47640_IG16 from 0150 to 0140 Adjusted offset of G_M47640_IG17 from 0160 to 0150 Adjusted offset of G_M47640_IG18 from 0174 to 0164 *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0x184 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x30) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M47640_IG01: ; offs=0x000000, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG IN005e: 000000 stp fp, lr, [sp, #-0x30]! IN005f: 000004 stp x19, x20, [sp, #0x20] IN0060: 000008 mov fp, sp IN0061: 00000C str xzr, [fp, #0x18] // [V03 tmp2] IN0062: 000010 mov x19, x0 ; gcrRegs +[x19] ;; size=20 bbWeight=1 PerfScore 4.00 G_M47640_IG02: ; offs=0x000014, size=0x0024, bbWeight=1, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, BB01 [0000], BB03 [0015], byref, isz IN0001: 000014 cbz x19, G_M47640_IG16 IN0002: 000018 mrs x1, tpidr_el0 recordRelocation: 000001CF35344234 (rw: 000001CF35344234) => 0000000000420480, type 263 (id->idIsTlsGD() ? IMAGE_REL_AARCH64_TLSDESC_ADR_PAGE21 : IMAGE_REL_ARM64_PAGEBASE_REL21), delta 0 IN0003: 00001C adrp x0, [HIGH RELOC #0x420480] recordRelocation: 000001CF35344238 (rw: 000001CF35344238) => 0000000000420480, type 264 (IMAGE_REL_AARCH64_TLSDESC_LD64_LO12), delta 0 IN0004: 000020 ldr x2, [x0] recordRelocation: 000001CF3534423C (rw: 000001CF3534423C) => 0000000000420480, type 265 (IMAGE_REL_AARCH64_TLSDESC_ADD_LO12), delta 0 IN0005: 000024 add x0, x0, [LOW RELOC #0x420480] recordRelocation: 000001CF35344240 (rw: 000001CF35344240) => 0000000000420480, type 266 (IMAGE_REL_AARCH64_TLSDESC_CALL), delta 0 IN0006: 000028 blr x0 ; gcrRegs -[x19] +[x20] IN0007: 00002C add x0, x1, x0 IN0008: 000030 ldr x20, [x0] IN0009: 000034 cbz x20, G_M47640_IG17 ;; size=36 bbWeight=1 PerfScore 11.50 G_M47640_IG03: ; offs=0x000038, size=0x0018, bbWeight=1, gcrefRegs=180000 {x19 x20}, byrefRegs=0000 {}, BB20 [0040], byref, isz ; gcrRegs +[x19] IN000a: 000038 ldr w0, [x20, #0x28] IN000b: 00003C sub w1, w0, #1 IN000c: 000040 orr w0, w0, w1, ASR #31 IN000d: 000044 str x19, [fp, #0x18] // [V03 tmp2] IN000e: 000048 ldr x1, [fp, #0x18] // [V03 tmp2] ; byrRegs +[x1] IN000f: 00004C sub x1, x1, #4 ; byrRegs -[x1] IN0010: 000050 align [0 bytes for IG04] IN0011: 000050 align [0 bytes] IN0012: 000050 align [0 bytes] IN0013: 000050 align [0 bytes] ;; size=24 bbWeight=1 PerfScore 8.00 G_M47640_IG04: ; offs=0x000050, size=0x0010, bbWeight=8, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0002], byref, isz ; gcrRegs -[x19-x20] IN0014: 000050 ldr w2, [x1] IN0015: 000054 uxth w3, w2 IN0016: 000058 cmp w3, w0 IN0017: 00005C bne G_M47640_IG12 ;; size=16 bbWeight=8 PerfScore 40.00 G_M47640_IG05: ; offs=0x000060, size=0x000C, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0003], BB06 [0004], byref, isz IN0018: 000060 tbnz w2, #27, G_M47640_IG12 IN0019: 000064 tst w2, #0x3F0000 IN001a: 000068 bne G_M47640_IG07 ;; size=12 bbWeight=4 PerfScore 10.00 G_M47640_IG06: ; offs=0x00006C, size=0x0008, bbWeight=2, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB07 [0005], byref IN001b: 00006C and w3, w2, #0xFFFF0000 IN001c: 000070 b G_M47640_IG08 ;; size=8 bbWeight=2 PerfScore 3.00 G_M47640_IG07: ; offs=0x000074, size=0x0004, bbWeight=2, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB08 [0006], byref IN001d: 000074 sub w3, w2, #16, LSL #12 ;; size=4 bbWeight=2 PerfScore 1.00 G_M47640_IG08: ; offs=0x000078, size=0x0014, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB09 [0007], byref, isz IN001e: 000078 ldaxr w5, [x1] IN001f: 00007C cmp w5, w2 IN0020: 000080 bne G_M47640_IG09 IN0021: 000084 stlxr w4, w3, [x1] IN0022: 000088 cbnz w4, G_M47640_IG08 ;; size=20 bbWeight=4 PerfScore 34.00 G_M47640_IG09: ; offs=0x00008C, size=0x000C, bbWeight=4, gcrefRegs=0000 {}, byrefRegs=0000 {}, loop=IG04, BB09 [0007], byref, isz IN0023: 00008C dmb ish IN0024: 000090 cmp w5, w2 IN0025: 000094 bne G_M47640_IG04 ;; size=12 bbWeight=4 PerfScore 46.00 G_M47640_IG10: ; offs=0x000098, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB18 [0039], byref IN0026: 000098 str xzr, [fp, #0x18] // [V03 tmp2] ;; size=4 bbWeight=1 PerfScore 1.00 G_M47640_IG11: ; offs=0x00009C, size=0x000C, bbWeight=1, epilog, nogc, extend IN0063: 00009C ldp x19, x20, [sp, #0x20] IN0064: 0000A0 ldp fp, lr, [sp], #0x30 IN0065: 0000A4 ret lr ;; size=12 bbWeight=1 PerfScore 3.00 G_M47640_IG12: ; offs=0x0000A8, size=0x0054, bbWeight=0.50, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB10 [0009], BB12 [0011], BB14 [0026], BB17 [0031], gcvars, byref, isz IN0027: 0000A8 and w1, w2, #0x3FFFFFF IN0028: 0000AC and w2, w2, #0xC000000 IN0029: 0000B0 mov w3, #0x8000000 IN002a: 0000B4 cmp w2, w3 IN002b: 0000B8 bne G_M47640_IG18 recordRelocation: 000001CF353442D4 (rw: 000001CF353442D4) => 00000000004208C8, type 4 (id->idIsTlsGD() ? IMAGE_REL_AARCH64_TLSDESC_ADR_PAGE21 : IMAGE_REL_ARM64_PAGEBASE_REL21), delta 0 IN002c: 0000BC adrp x2, [HIGH RELOC #0x4208C8] recordRelocation: 000001CF353442D8 (rw: 000001CF353442D8) => 00000000004208C8, type 6 (IMAGE_REL_ARM64_PAGEOFFSET_12A), delta 0 IN002d: 0000C0 add x2, x2, [LOW RELOC #0x4208C8] IN002e: 0000C4 ldr x2, [x2] IN002f: 0000C8 ldr x2, [x2, #0x10] ; gcrRegs +[x2] IN0030: 0000CC ldrsb wzr, [x2], #0x10 ; gcrRegs -[x2] ; byrRegs +[x2] IN0031: 0000D0 sbfiz x1, x1, #5, #32 IN0032: 0000D4 ldr x1, [x2, x1] ; gcrRegs +[x1] IN0033: 0000D8 str xzr, [fp, #0x18] // [V03 tmp2] IN0034: 0000DC ldr w2, [x1, #0x10] ; byrRegs -[x2] IN0035: 0000E0 cmp w2, w0 IN0036: 0000E4 bne G_M47640_IG15 IN0037: 0000E8 ldr w0, [x1, #0x18] IN0038: 0000EC cbz w0, G_M47640_IG13 IN0039: 0000F0 sub w0, w0, #1 IN003a: 0000F4 str w0, [x1, #0x18] IN003b: 0000F8 b G_M47640_IG10 ;; size=84 bbWeight=0.50 PerfScore 14.50 G_M47640_IG13: ; offs=0x0000FC, size=0x0008, bbWeight=0.50, gcrefRegs=0002 {x1}, byrefRegs=0000 {}, BB15 [0029], byref IN003c: 0000FC str wzr, [x1, #0x10] IN003d: 000100 add x0, x1, #20 ; byrRegs +[x0] ;; size=8 bbWeight=0.50 PerfScore 0.75 G_M47640_IG14: ; offs=0x000104, size=0x0034, bbWeight=0.50, gcrefRegs=0002 {x1}, byrefRegs=0001 {x0}, BB15 [0029], BB16 [0030], byref, isz IN003e: 000104 ldaxr w4, [x0] IN003f: 000108 sub w3, w4, #1 IN0040: 00010C stlxr w2, w3, [x0] IN0041: 000110 cbnz w2, G_M47640_IG14 IN0042: 000114 dmb ish IN0043: 000118 sub w0, w4, #1 ; byrRegs -[x0] IN0044: 00011C sxtw w2, w0 IN0045: 000120 cmp w2, #128 IN0046: 000124 blo G_M47640_IG10 IN0047: 000128 mov x0, x1 ; gcrRegs +[x0] IN0048: 00012C mov w1, w2 ; gcrRegs -[x1] recordRelocation: 000001CF35344348 (rw: 000001CF35344348) => 00000000004209C8, type 3 (IMAGE_REL_ARM64_BRANCH26), delta 0 IN0049: 000130 bl System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this ; gcrRegs -[x0] ; gcr arg pop 0 IN004a: 000134 b G_M47640_IG10 ;; size=52 bbWeight=0.50 PerfScore 11.50 G_M47640_IG15: ; offs=0x000138, size=0x0008, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB13 [0025], byref recordRelocation: 000001CF35344350 (rw: 000001CF35344350) => 0000000000420958, type 3 (IMAGE_REL_ARM64_BRANCH26), delta 0 IN004b: 000138 bl System.ThrowHelper:ThrowSynchronizationLockException_LockExit() ; gcr arg pop 0 IN004c: 00013C brk #0 ;; size=8 bbWeight=0.50 PerfScore 1.00 G_M47640_IG16: ; offs=0x000140, size=0x0010, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0014], byref recordRelocation: 000001CF35344358 (rw: 000001CF35344358) => 0000000000420A80, type 4 (id->idIsTlsGD() ? IMAGE_REL_AARCH64_TLSDESC_ADR_PAGE21 : IMAGE_REL_ARM64_PAGEBASE_REL21), delta 0 IN004d: 000140 adrp x0, [HIGH RELOC #0x420A80] // '"obj"' recordRelocation: 000001CF3534435C (rw: 000001CF3534435C) => 0000000000420A80, type 6 (IMAGE_REL_ARM64_PAGEOFFSET_12A), delta 0 IN004e: 000144 add x0, x0, [LOW RELOC #0x420A80] ; gcrRegs +[x0] recordRelocation: 000001CF35344360 (rw: 000001CF35344360) => 0000000000420848, type 3 (IMAGE_REL_ARM64_BRANCH26), delta 0 IN004f: 000148 bl System.ArgumentNullException:Throw(System.String) ; gcrRegs -[x0] ; gcr arg pop 0 IN0050: 00014C brk #0 ;; size=16 bbWeight=0.50 PerfScore 1.50 G_M47640_IG17: ; offs=0x000150, size=0x0014, bbWeight=0, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, BB22 [0042], byref ; gcrRegs +[x19] recordRelocation: 000001CF35344368 (rw: 000001CF35344368) => 0000000000420488, type 4 (id->idIsTlsGD() ? IMAGE_REL_AARCH64_TLSDESC_ADR_PAGE21 : IMAGE_REL_ARM64_PAGEBASE_REL21), delta 0 IN0051: 000150 adrp x1, [HIGH RELOC #0x420488] recordRelocation: 000001CF3534436C (rw: 000001CF3534436C) => 0000000000420488, type 6 (IMAGE_REL_ARM64_PAGEOFFSET_12A), delta 0 IN0052: 000154 add x1, x1, [LOW RELOC #0x420488] IN0053: 000158 blr x1 ; gcrRegs +[x0] ; gcr arg pop 0 IN0054: 00015C mov x20, x0 ; gcrRegs +[x20] IN0055: 000160 b G_M47640_IG03 ;; size=20 bbWeight=0 PerfScore 0.00 G_M47640_IG18: ; offs=0x000164, size=0x0020, bbWeight=0, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB11 [0010], byref ; gcrRegs -[x0 x19-x20] recordRelocation: 000001CF3534437C (rw: 000001CF3534437C) => 0000000000420818, type 4 (id->idIsTlsGD() ? IMAGE_REL_AARCH64_TLSDESC_ADR_PAGE21 : IMAGE_REL_ARM64_PAGEBASE_REL21), delta 0 IN0056: 000164 adrp x0, [HIGH RELOC #0x420818] // System.Threading.SynchronizationLockException recordRelocation: 000001CF35344380 (rw: 000001CF35344380) => 0000000000420818, type 6 (IMAGE_REL_ARM64_PAGEOFFSET_12A), delta 0 IN0057: 000168 add x0, x0, [LOW RELOC #0x420818] recordRelocation: 000001CF35344384 (rw: 000001CF35344384) => 00000000004205F0, type 3 (IMAGE_REL_ARM64_BRANCH26), delta 0 IN0058: 00016C bl CORINFO_HELP_NEWSFAST ; gcrRegs +[x0] ; gcr arg pop 0 IN0059: 000170 mov x19, x0 ; gcrRegs +[x19] recordRelocation: 000001CF3534438C (rw: 000001CF3534438C) => 0000000000420808, type 3 (IMAGE_REL_ARM64_BRANCH26), delta 0 IN005a: 000174 bl System.Threading.SynchronizationLockException:.ctor():this ; gcrRegs -[x0] ; gcr arg pop 0 IN005b: 000178 mov x0, x19 ; gcrRegs +[x0] recordRelocation: 000001CF35344394 (rw: 000001CF35344394) => 00000000004205F8, type 3 (IMAGE_REL_ARM64_BRANCH26), delta 0 IN005c: 00017C bl CORINFO_HELP_THROW ; gcrRegs -[x0 x19] ; gcr arg pop 0 IN005d: 000180 brk #0 ;; size=32 bbWeight=0 PerfScore 0.00 Allocated method code size = 388 , actual size = 388, unused size = 0 ; Total bytes of code 388, prolog size 20, PerfScore 190.75, instruction count 101, allocated bytes for code 388 (MethodHash=cb7d45e7) for method System.Threading.Monitor:Exit(System.Object) (FullOpts) ; ============================================================ *************** After end code gen, before unwindEmit() G_M47640_IG01: ; func=00, offs=0x000000, size=0x0014, bbWeight=1, PerfScore 4.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG IN005e: 000000 stp fp, lr, [sp, #-0x30]! IN005f: 000004 stp x19, x20, [sp, #0x20] IN0060: 000008 mov fp, sp IN0061: 00000C str xzr, [fp, #0x18] // [V03 tmp2] IN0062: 000010 mov x19, x0 G_M47640_IG02: ; offs=0x000014, size=0x0024, bbWeight=1, PerfScore 11.50, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, BB01 [0000], BB03 [0015], byref, isz IN0001: 000014 cbz x19, G_M47640_IG16 IN0002: 000018 mrs x1, tpidr_el0 IN0003: 00001C adrp x0, [HIGH RELOC #0x420480] IN0004: 000020 ldr x2, [x0] IN0005: 000024 add x0, x0, [LOW RELOC #0x420480] IN0006: 000028 blr x0 IN0007: 00002C add x0, x1, x0 IN0008: 000030 ldr x20, [x0] IN0009: 000034 cbz x20, G_M47640_IG17 G_M47640_IG03: ; offs=0x000038, size=0x0018, bbWeight=1, PerfScore 8.00, gcrefRegs=180000 {x19 x20}, byrefRegs=0000 {}, BB20 [0040], byref, isz IN000a: 000038 ldr w0, [x20, #0x28] IN000b: 00003C sub w1, w0, #1 IN000c: 000040 orr w0, w0, w1, ASR #31 IN000d: 000044 str x19, [fp, #0x18] // [V03 tmp2] IN000e: 000048 ldr x1, [fp, #0x18] // [V03 tmp2] IN000f: 00004C sub x1, x1, #4 IN0010: 000050 align [0 bytes for IG04] IN0011: 000050 align [0 bytes] IN0012: 000050 align [0 bytes] IN0013: 000050 align [0 bytes] G_M47640_IG04: ; offs=0x000050, size=0x0010, bbWeight=8, PerfScore 40.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0002], byref, isz IN0014: 000050 ldr w2, [x1] IN0015: 000054 uxth w3, w2 IN0016: 000058 cmp w3, w0 IN0017: 00005C bne G_M47640_IG12 G_M47640_IG05: ; offs=0x000060, size=0x000C, bbWeight=4, PerfScore 10.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0003], BB06 [0004], byref, isz IN0018: 000060 tbnz w2, #27, G_M47640_IG12 IN0019: 000064 tst w2, #0x3F0000 IN001a: 000068 bne G_M47640_IG07 G_M47640_IG06: ; offs=0x00006C, size=0x0008, bbWeight=2, PerfScore 3.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB07 [0005], byref IN001b: 00006C and w3, w2, #0xFFFF0000 IN001c: 000070 b G_M47640_IG08 G_M47640_IG07: ; offs=0x000074, size=0x0004, bbWeight=2, PerfScore 1.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB08 [0006], byref IN001d: 000074 sub w3, w2, #16, LSL #12 G_M47640_IG08: ; offs=0x000078, size=0x0014, bbWeight=4, PerfScore 34.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB09 [0007], byref, isz IN001e: 000078 ldaxr w5, [x1] IN001f: 00007C cmp w5, w2 IN0020: 000080 bne G_M47640_IG09 IN0021: 000084 stlxr w4, w3, [x1] IN0022: 000088 cbnz w4, G_M47640_IG08 G_M47640_IG09: ; offs=0x00008C, size=0x000C, bbWeight=4, PerfScore 46.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, loop=IG04, BB09 [0007], byref, isz IN0023: 00008C dmb ish IN0024: 000090 cmp w5, w2 IN0025: 000094 bne G_M47640_IG04 G_M47640_IG10: ; offs=0x000098, size=0x0004, bbWeight=1, PerfScore 1.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB18 [0039], byref IN0026: 000098 str xzr, [fp, #0x18] // [V03 tmp2] G_M47640_IG11: ; offs=0x00009C, size=0x000C, bbWeight=1, PerfScore 3.00, epilog, nogc, extend IN0063: 00009C ldp x19, x20, [sp, #0x20] IN0064: 0000A0 ldp fp, lr, [sp], #0x30 IN0065: 0000A4 ret lr G_M47640_IG12: ; offs=0x0000A8, size=0x0054, bbWeight=0.50, PerfScore 14.50, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB10 [0009], BB12 [0011], BB14 [0026], BB17 [0031], gcvars, byref, isz IN0027: 0000A8 and w1, w2, #0x3FFFFFF IN0028: 0000AC and w2, w2, #0xC000000 IN0029: 0000B0 mov w3, #0x8000000 IN002a: 0000B4 cmp w2, w3 IN002b: 0000B8 bne G_M47640_IG18 IN002c: 0000BC adrp x2, [HIGH RELOC #0x4208C8] IN002d: 0000C0 add x2, x2, [LOW RELOC #0x4208C8] IN002e: 0000C4 ldr x2, [x2] IN002f: 0000C8 ldr x2, [x2, #0x10] IN0030: 0000CC ldrsb wzr, [x2], #0x10 IN0031: 0000D0 sbfiz x1, x1, #5, #32 IN0032: 0000D4 ldr x1, [x2, x1] IN0033: 0000D8 str xzr, [fp, #0x18] // [V03 tmp2] IN0034: 0000DC ldr w2, [x1, #0x10] IN0035: 0000E0 cmp w2, w0 IN0036: 0000E4 bne G_M47640_IG15 IN0037: 0000E8 ldr w0, [x1, #0x18] IN0038: 0000EC cbz w0, G_M47640_IG13 IN0039: 0000F0 sub w0, w0, #1 IN003a: 0000F4 str w0, [x1, #0x18] IN003b: 0000F8 b G_M47640_IG10 G_M47640_IG13: ; offs=0x0000FC, size=0x0008, bbWeight=0.50, PerfScore 0.75, gcrefRegs=0002 {x1}, byrefRegs=0000 {}, BB15 [0029], byref IN003c: 0000FC str wzr, [x1, #0x10] IN003d: 000100 add x0, x1, #20 G_M47640_IG14: ; offs=0x000104, size=0x0034, bbWeight=0.50, PerfScore 11.50, gcrefRegs=0002 {x1}, byrefRegs=0001 {x0}, BB15 [0029], BB16 [0030], byref, isz IN003e: 000104 ldaxr w4, [x0] IN003f: 000108 sub w3, w4, #1 IN0040: 00010C stlxr w2, w3, [x0] IN0041: 000110 cbnz w2, G_M47640_IG14 IN0042: 000114 dmb ish IN0043: 000118 sub w0, w4, #1 IN0044: 00011C sxtw w2, w0 IN0045: 000120 cmp w2, #128 IN0046: 000124 blo G_M47640_IG10 IN0047: 000128 mov x0, x1 IN0048: 00012C mov w1, w2 IN0049: 000130 bl System.Threading.Lock:SignalWaiterIfNecessary(System.Threading.Lock+State):this IN004a: 000134 b G_M47640_IG10 G_M47640_IG15: ; offs=0x000138, size=0x0008, bbWeight=0.50, PerfScore 1.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB13 [0025], byref IN004b: 000138 bl System.ThrowHelper:ThrowSynchronizationLockException_LockExit() IN004c: 00013C brk #0 G_M47640_IG16: ; offs=0x000140, size=0x0010, bbWeight=0.50, PerfScore 1.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0014], byref IN004d: 000140 adrp x0, [HIGH RELOC #0x420A80] // '"obj"' IN004e: 000144 add x0, x0, [LOW RELOC #0x420A80] IN004f: 000148 bl System.ArgumentNullException:Throw(System.String) IN0050: 00014C brk #0 G_M47640_IG17: ; offs=0x000150, size=0x0014, bbWeight=0, PerfScore 0.00, gcrefRegs=80000 {x19}, byrefRegs=0000 {}, BB22 [0042], byref IN0051: 000150 adrp x1, [HIGH RELOC #0x420488] IN0052: 000154 add x1, x1, [LOW RELOC #0x420488] IN0053: 000158 blr x1 IN0054: 00015C mov x20, x0 IN0055: 000160 b G_M47640_IG03 G_M47640_IG18: ; offs=0x000164, size=0x0020, bbWeight=0, PerfScore 0.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB11 [0010], byref IN0056: 000164 adrp x0, [HIGH RELOC #0x420818] // System.Threading.SynchronizationLockException IN0057: 000168 add x0, x0, [LOW RELOC #0x420818] IN0058: 00016C bl CORINFO_HELP_NEWSFAST IN0059: 000170 mov x19, x0 IN005a: 000174 bl System.Threading.SynchronizationLockException:.ctor():this IN005b: 000178 mov x0, x19 IN005c: 00017C bl CORINFO_HELP_THROW IN005d: 000180 brk #0 *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Cfi Info: >> Start offset : 0x000000 >> End offset : 0x000184 CodeOffset: 0x04 Op: AdjustCfaOffset Offset:0x30 CodeOffset: 0x04 Op: RelOffset DwarfReg:0x1d Offset:0x0 CodeOffset: 0x04 Op: RelOffset DwarfReg:0x1e Offset:0x8 CodeOffset: 0x08 Op: RelOffset DwarfReg:0x13 Offset:0x20 CodeOffset: 0x08 Op: RelOffset DwarfReg:0x14 Offset:0x28 CodeOffset: 0x0C Op: DefCfaRegister DwarfReg:0x1D allocUnwindInfo(pHotCode=0x000001CF35344218, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x184, unwindSize=0x30, pUnwindBlock=0x000001CF00444178, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 7 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000014 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000038 ( STACK_EMPTY ) IL offs 0x0006 : 0x0000009C ( STACK_EMPTY ) IL offs EPILOG : 0x0000009C ( STACK_EMPTY ) IL offs 0x0000 : 0x000000A8 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000150 ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 3 ; Variable debug info: 3 live ranges, 1 vars for method System.Threading.Monitor:Exit(System.Object) (V00 arg0) : From 00000000h to 00000014h, in x0 (V00 arg0) : From 00000014h to 00000044h, in x19 (V00 arg0) : From 00000150h to 00000164h, in x19 *************** In gcInfoBlockHdrSave() Set code length to 388. Set stack base register to fp. Set Outgoing stack arg area size to 0. Stack slot id for offset 24 (0x18) (frame) (byref, pinned, untracked) = 0. Register slot id for reg x19 = 1. Register slot id for reg x20 = 2. Register slot id for reg x1 (byref) = 3. Register slot id for reg x2 = 4. Register slot id for reg x2 (byref) = 5. Register slot id for reg x1 = 6. Register slot id for reg x0 (byref) = 7. Register slot id for reg x0 = 8. Set state of slot 1 at instr offset 0x14 to Live. Set state of slot 1 at instr offset 0x2c to Dead. Set state of slot 2 at instr offset 0x2c to Live. Set state of slot 1 at instr offset 0x38 to Live. Set state of slot 3 at instr offset 0x4c to Live. Set state of slot 3 at instr offset 0x50 to Dead. Set state of slot 1 at instr offset 0x50 to Dead. Set state of slot 2 at instr offset 0x50 to Dead. Set state of slot 4 at instr offset 0xcc to Live. Set state of slot 4 at instr offset 0xd0 to Dead. Set state of slot 5 at instr offset 0xd0 to Live. Set state of slot 6 at instr offset 0xd8 to Live. Set state of slot 5 at instr offset 0xe0 to Dead. Set state of slot 7 at instr offset 0x104 to Live. Set state of slot 7 at instr offset 0x11c to Dead. Set state of slot 8 at instr offset 0x12c to Live. Set state of slot 6 at instr offset 0x130 to Dead. Set state of slot 8 at instr offset 0x134 to Dead. Set state of slot 8 at instr offset 0x148 to Live. Set state of slot 8 at instr offset 0x14c to Dead. Set state of slot 1 at instr offset 0x150 to Live. Set state of slot 8 at instr offset 0x15c to Live. Set state of slot 2 at instr offset 0x160 to Live. Set state of slot 8 at instr offset 0x164 to Dead. Set state of slot 1 at instr offset 0x164 to Dead. Set state of slot 2 at instr offset 0x164 to Dead. Set state of slot 8 at instr offset 0x170 to Live. Set state of slot 1 at instr offset 0x174 to Live. Set state of slot 8 at instr offset 0x178 to Dead. Set state of slot 8 at instr offset 0x17c to Live. Set state of slot 8 at instr offset 0x180 to Dead. Set state of slot 1 at instr offset 0x180 to Dead. Defining interruptible range: [0x14, 0xa0). Defining interruptible range: [0xa8, 0x184). *************** Finishing PHASE Emit GC+EH tables Method code size: 388 Allocations for System.Threading.Monitor:Exit(System.Object) (MethodHash=cb7d45e7) count: 4577, size: 454674, max = 7872 allocateMemory: 524288, nraUsed: 461776 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- ABI | 152 | 0.03% AssertionProp | 7172 | 1.58% ASTNode | 47280 | 10.40% InstDesc | 15316 | 3.37% ImpStack | 408 | 0.09% BasicBlock | 14912 | 3.28% CallArgs | 2808 | 0.62% FlowEdge | 1888 | 0.42% DepthFirstSearch | 19936 | 4.38% Loops | 1920 | 0.42% TreeStatementList | 64 | 0.01% SiScope | 0 | 0.00% DominatorMemory | 2112 | 0.46% LSRA | 13440 | 2.96% LSRA_Interval | 5568 | 1.22% LSRA_RefPosition | 16160 | 3.55% Reachability | 184 | 0.04% SSA | 2592 | 0.57% ValueNumber | 29976 | 6.59% LvaTable | 4548 | 1.00% UnwindInfo | 32 | 0.01% hashBv | 40 | 0.01% bitset | 2624 | 0.58% FixedBitVect | 344 | 0.08% Generic | 1520 | 0.33% LocalAddressVisitor | 448 | 0.10% FieldSeqStore | 304 | 0.07% MemorySsaMap | 40 | 0.01% MemoryPhiArg | 32 | 0.01% CSE | 4004 | 0.88% GC | 4388 | 0.97% CorTailCallInfo | 0 | 0.00% Inlining | 14608 | 3.21% ArrayStack | 512 | 0.11% DebugInfo | 472 | 0.10% DebugOnly | 227957 | 50.14% Codegen | 2664 | 0.59% LoopOpt | 64 | 0.01% LoopClone | 48 | 0.01% LoopUnroll | 0 | 0.00% LoopHoist | 432 | 0.10% LoopIVOpts | 0 | 0.00% Unknown | 1521 | 0.33% RangeCheck | 0 | 0.00% CopyProp | 2720 | 0.60% Promotion | 2280 | 0.50% SideEffects | 0 | 0.00% ObjectAllocator | 152 | 0.03% VariableLiveRanges | 416 | 0.09% ClassLayout | 200 | 0.04% TailMergeThrows | 136 | 0.03% EarlyProp | 192 | 0.04% ZeroInit | 88 | 0.02% Pgo | 0 | 0.00% MaskConversionOpt | 0 | 0.00% TryRegionClone | 0 | 0.00% Final metrics: ActualCodeBytes : 388 AllocatedHotCodeBytes : 388 AllocatedColdCodeBytes : 0 ReadOnlyDataBytes : 0 GCInfoBytes : 51 EHClauseCount : 0 PhysicallyPromotedFields : 0 LoopsFoundDuringOpts : 1 LoopsInverted : 0 LoopsCloned : 0 LoopsUnrolled : 0 LoopAlignmentCandidates : 1 LoopsAligned : 0 LoopsIVWidened : 0 WidenedIVs : 0 UnusedIVsRemoved : 0 LoopsMadeDownwardsCounted : 0 LoopsStrengthReduced : 0 VarsInSsa : 14 HoistedExpressions : 0 RedundantBranchesEliminated : 0 JumpThreadingsPerformed : 0 CseCount : 1 BasicBlocksAtCodegen : 21 PerfScore : 190.750000 BytesAllocated : 461776 ImporterBranchFold : 0 ImporterSwitchFold : 0 DevirtualizedCall : 0 DevirtualizedCallUnboxedEntry : 0 DevirtualizedCallRemovedBox : 0 GDV : 0 ClassGDV : 0 MethodGDV : 0 MultiGuessGDV : 0 ChainedGDV : 0 EnumeratorGDV : 0 InlinerBranchFold : 0 InlineAttempt : 16 InlineCount : 16 ProfileConsistentBeforeInline : 0 ProfileConsistentAfterInline : 0 ProfileConsistentBeforeMorph : 0 ProfileConsistentAfterMorph : 0 ProfileSynthesizedBlendedOrRepaired : 0 ProfileInconsistentInitially : 0 ProfileInconsistentResetLeave : 0 ProfileInconsistentImporterBranchFold : 0 ProfileInconsistentImporterSwitchFold : 0 ProfileInconsistentChainedGDV : 0 ProfileInconsistentScratchBB : 0 ProfileInconsistentInlinerBranchFold : 0 ProfileInconsistentInlineeScale : 0 ProfileInconsistentInlinee : 0 ProfileInconsistentNoReturnInlinee : 0 ProfileInconsistentMayThrowInlinee : 0 NewRefClassHelperCalls : 1 StackAllocatedRefClasses : 0 NewBoxedValueClassHelperCalls : 0 StackAllocatedBoxedValueClasses : 0 NewArrayHelperCalls : 0 StackAllocatedArrays : 0 LocalAssertionCount : 9 LocalAssertionOverflow : 0 MorphTrackedLocals : 15 MorphLocals : 21 EnumeratorGDVProvisionalNoEscape : 0 EnumeratorGDVCanCloneToEnsureNoEscape : 0 ****** DONE compiling System.Threading.Monitor:Exit(System.Object)