diff --git a/components/ulp/lp_core/lp_core/lp_core_uart.c b/components/ulp/lp_core/lp_core/lp_core_uart.c
index ef20026587..80426a6c28 100644
--- a/components/ulp/lp_core/lp_core/lp_core_uart.c
+++ b/components/ulp/lp_core/lp_core/lp_core_uart.c
@@ -56,8 +56,36 @@ int lp_core_uart_tx_chars(uart_port_t lp_uart_num, const void *src, size_t size)
         return 0;
     }
 
+    /* Enable Tx interrupt */
+    uint32_t intr_mask = LP_UART_TX_INT_FLAG | LP_UART_ERR_INT_FLAG;
+    uart_hal_clr_intsts_mask(&hal, intr_mask);
+    uart_hal_ena_intr_mask(&hal, intr_mask);
+
     /* Write the data to the Tx FIFO */
     uart_hal_write_txfifo(&hal, src, size, &tx_len);
+    if (tx_len) {
+        while (1) {
+            /* Fetch the interrupt status */
+            uint32_t intr_status = uart_hal_get_intsts_mask(&hal);
+            if (intr_status & LP_UART_TX_INT_FLAG) {
+                /* Clear interrupt status and break */
+                uart_hal_clr_intsts_mask(&hal, intr_mask);
+                break;
+            } else if ((intr_status & LP_UART_ERR_INT_FLAG)) {
+                /* Transaction error. Abort */
+                return 0;
+            }
+
+            /* Check for transaction timeout. Assume a timeout of 100 cycles. */
+            uint32_t to = 0;
+            esp_err_t ret = lp_core_uart_check_timeout(intr_mask, 100, &to);
+            if (ret == ESP_ERR_TIMEOUT) {
+                /* Timeout */
+                uart_hal_disable_intr_mask(&hal, intr_mask);
+                return 0;
+            }
+        }
+    }
 
     /* Return the number of bytes written */
     return tx_len;