From ed8a217756ccdb3ffa4caf5878dc876faab998d4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 25 Mar 2020 16:32:27 -0700 Subject: [PATCH 1/3] [make] split up specific make vars/targets into frags --- common.mk | 45 +++++++++++++-------------------- generators/ariane | 2 +- generators/tracegen/tracegen.mk | 18 +++++++++++++ sims/vcs/Makefile | 11 ++++---- sims/verilator/Makefile | 25 +++++++++++++----- variables.mk | 2 +- 6 files changed, 62 insertions(+), 41 deletions(-) create mode 100644 generators/tracegen/tracegen.mk diff --git a/common.mk b/common.mk index bf40e60262..4fb2cf8216 100644 --- a/common.mk +++ b/common.mk @@ -3,6 +3,18 @@ ######################################################################################### SHELL=/bin/bash +######################################################################################### +# extra make variables/rules from subprojects +# +# EXTRA_GENERATOR_REQS - requirements needed for the main generator +# EXTRA_SIM_FLAGS - runtime simulation flags +# EXTRA_SIM_CC_FLAGS - cc flags for simulators +# EXTRA_SIM_SOURCES - simulation sources needed for simulator +# EXTRA_SIM_REQS - requirements to build the simulator +######################################################################################### +include $(base_dir)/generators/ariane/ariane.mk +include $(base_dir)/generators/tracegen/tracegen.mk + ######################################################################################### # variables to get all *.scala files ######################################################################################### @@ -11,7 +23,6 @@ lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -prin SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) -ARIANE_VLOG_SOURCES = $(call lookup_srcs,$(base_dir)/generators/ariane,sv) $(call lookup_srcs,$(base_dir)/generators/ariane,v) ######################################################################################### # rocket and testchipip classes @@ -45,7 +56,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): generator_temp @echo "" > /dev/null # AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile -generator_temp: $(SCALA_SOURCES) $(ARIANE_VLOG_SOURCES) $(sim_files) +generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)" @@ -105,19 +116,19 @@ verilog: $(sim_vsrcs) ######################################################################################### .PHONY: run-binary run-binary-fast run-binary-debug run-fast run-binary: $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) ######################################################################################### # helper rules to run simulator as fast as possible ######################################################################################### run-binary-fast: $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast @@ -129,10 +140,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) ######################################################################################### # include build/project specific makefrags made from the generator @@ -141,26 +152,6 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) -include $(build_dir)/$(long_name).d endif -################################################# -# Rules for running and checking tracegen tests # -################################################# - -AXE_DIR=$(base_dir)/tools/axe/src -AXE=$(AXE_DIR)/axe - -$(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh - cd $(AXE_DIR) && ./make.sh - -$(output_dir)/tracegen.out: $(sim) - mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ - -$(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) - $(base_dir)/scripts/check-tracegen.sh $< > $@ - -tracegen: $(output_dir)/tracegen.result - -.PHONY: tracegen - ####################################### # Rules for building DRAMSim2 library # ####################################### diff --git a/generators/ariane b/generators/ariane index 145b5ed106..e02436d2aa 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 145b5ed106efd0b22c2105c20722ab303fa4039b +Subproject commit e02436d2aaf934b6e58d5e11e87276ba0d840f2a diff --git a/generators/tracegen/tracegen.mk b/generators/tracegen/tracegen.mk new file mode 100644 index 0000000000..499606f28d --- /dev/null +++ b/generators/tracegen/tracegen.mk @@ -0,0 +1,18 @@ +############################################################## +# extra variables/targets ingested by the chipyard make system +############################################################## + +AXE_DIR=$(base_dir)/tools/axe/src +AXE=$(AXE_DIR)/axe + +$(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh + cd $(AXE_DIR) && ./make.sh + +$(output_dir)/tracegen.out: $(sim) + mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) +dramsim +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ + +$(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) + $(base_dir)/scripts/check-tracegen.sh $< > $@ + +.PHONY: tracegen +tracegen: $(output_dir)/tracegen.result diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index e829047cbb..659d1fc03a 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -50,7 +50,8 @@ VCS_CC_OPTS = \ -CC "-I$(dramsim_dir)" \ -CC "-std=c++11" \ $(dramsim_lib) \ - $(RISCV)/lib/libfesvr.a + $(RISCV)/lib/libfesvr.a \ + -CC "$(EXTRA_SIM_CC_FLAGS)" VCS_NONCC_OPTS = \ +lint=all,noVCDE,noONGS,noUI \ @@ -80,16 +81,16 @@ VCS_DEFINES = \ +define+RANDOMIZE_GARBAGE_ASSIGN \ +define+RANDOMIZE_INVALID_ASSIGN -VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINES) +VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINES) $(EXTRA_SIM_SOURCES) ######################################################################################### # vcs simulator rules ######################################################################################### -$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) +$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) +$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG \ -debug_pp @@ -99,7 +100,7 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) ######################################################################################### .PRECIOUS: $(output_dir)/%.vpd %.vpd $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 13e7d20125..8bd4cd75ee 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -47,14 +47,25 @@ include $(base_dir)/common.mk ######################################################################################### VERILATOR := verilator --cc --exe -CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -I$(dramsim_dir) -D__STDC_FORMAT_MACROS -LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(dramsim_dir) -Wl,-rpath,$(dramsim_dir) -L$(sim_dir) -lfesvr -lpthread -ldramsim +CXXFLAGS := \ + $(CXXFLAGS) -O1 -std=c++11 \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -D__STDC_FORMAT_MACROS \ + $(EXTRA_SIM_CC_FLAGS) + +LDFLAGS := \ + $(LDFLAGS) \ + -L$(sim_dir) \ + -lpthread VERILATOR_CC_OPTS = \ -O3 \ -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \ - -LDFLAGS "$(LDFLAGS)" + -LDFLAGS "$(LDFLAGS)" \ + $(RISCV)/lib/libfesvr.a \ + $(dramsim_lib) # default flags added for ariane ARIANE_VERILATOR_FLAGS = \ @@ -87,7 +98,7 @@ VERILATOR_DEFINES = \ +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ +define+STOP_COND=\$$c\(\"done_reset\"\) -VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) +VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) $(EXTRA_SIM_SOURCES) ######################################################################################### # verilator build paths and file names @@ -104,13 +115,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules ######################################################################################### -$(model_mk): $(sim_vsrcs) $(sim_common_files) +$(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ -$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) +$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" @@ -132,7 +143,7 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule diff --git a/variables.mk b/variables.mk index 8a1bb1dfc0..5692296bcb 100644 --- a/variables.mk +++ b/variables.mk @@ -143,7 +143,7 @@ output_dir=$(sim_dir)/output/$(long_name) # helper variables to run binaries ######################################################################################### BINARY ?= -SIM_FLAGS ?= +override SIM_FLAGS += +dramsim +max-cycles=$(timeout_cycles) VERBOSE_FLAGS ?= +verbose sim_out_name = $(subst $() $(),_,$(notdir $(basename $(BINARY))).$(long_name)) From e21ff9890345b6481e1c8edfaa9db62790501295 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 25 Mar 2020 16:42:59 -0700 Subject: [PATCH 2/3] [make] move dramsim and max-cycles into SIM_FLAGS --- generators/tracegen/tracegen.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/tracegen/tracegen.mk b/generators/tracegen/tracegen.mk index 499606f28d..fc4bd2465b 100644 --- a/generators/tracegen/tracegen.mk +++ b/generators/tracegen/tracegen.mk @@ -9,7 +9,7 @@ $(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh cd $(AXE_DIR) && ./make.sh $(output_dir)/tracegen.out: $(sim) - mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) +dramsim +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ + mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) $(base_dir)/scripts/check-tracegen.sh $< > $@ From 89449e0531e72851c30fc3aa2046b6b32e7b224f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 27 Mar 2020 13:55:24 -0700 Subject: [PATCH 3/3] [misc] move ariane configs to configs/ folder --- .../chipyard/src/main/scala/{ => config}/ArianeConfigs.scala | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename generators/chipyard/src/main/scala/{ => config}/ArianeConfigs.scala (100%) diff --git a/generators/chipyard/src/main/scala/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala similarity index 100% rename from generators/chipyard/src/main/scala/ArianeConfigs.scala rename to generators/chipyard/src/main/scala/config/ArianeConfigs.scala