From 45eeee5092cbdb9d5b29fb44a8a832dda2bcb346 Mon Sep 17 00:00:00 2001 From: jerryho Date: Fri, 26 May 2023 16:08:59 +0800 Subject: [PATCH 1/2] fix the data field width mismatch between AXI that goes to MIG core and that of the Memory Bus --- fpga/src/main/scala/vcu118/TestHarness.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index ac9f9d05d8..b6a232523d 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -84,8 +84,8 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S name = "chip_ddr", sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits) ))))) - ddrNode := ddrClient - + ddrNode := TLWidthWidget(dp(XLen)/8) := ddrClient + // module implementation override lazy val module = new VCU118FPGATestHarnessImp(this) } From 9844deb1723b331b89fb52d0a630e3e9b4d7dee2 Mon Sep 17 00:00:00 2001 From: jerryho Date: Sat, 27 May 2023 18:12:56 +0800 Subject: [PATCH 2/2] using dp(ExtTLMem).get.master.beatBytes to obtain MemoryBus data width --- fpga/src/main/scala/vcu118/TestHarness.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index b6a232523d..850b7f6288 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -84,8 +84,8 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S name = "chip_ddr", sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits) ))))) - ddrNode := TLWidthWidget(dp(XLen)/8) := ddrClient - + ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient + // module implementation override lazy val module = new VCU118FPGATestHarnessImp(this) }