From 85fe0612448a8f1036d4f93bfd7da80cee4deb54 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 15 Feb 2023 14:19:55 -0800 Subject: [PATCH 1/4] Use EICG_wrapper model as addResource/Path | Fix Makefile parsing --- fpga/Makefile | 3 --- generators/chipyard/src/main/scala/config/AbstractConfig.scala | 1 + sims/common-sim-flags.mk | 3 --- vlsi/Makefile | 3 +-- 4 files changed, 2 insertions(+), 8 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index d037833bb2..7b0f3f80b6 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -90,9 +90,6 @@ fpga_common_script_dir := $(fpga_dir)/common/tcl ######################################################################################### # setup misc. sim files ######################################################################################### -SIM_FILE_REQS += \ - $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v - # copy files but ignore *.h files in *.f (match vcs) $(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR) cp -f $^ $(OUT_DIR) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 1f43dcbf2a..3df76ed9ae 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -51,6 +51,7 @@ class AbstractConfig extends Config( new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus + new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 3b4281c3a5..37dd390521 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -33,6 +33,3 @@ SIM_LDFLAGS = \ -lfesvr \ -ldramsim \ $(EXTRA_SIM_LDFLAGS) - -SIM_FILE_REQS += \ - $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v diff --git a/vlsi/Makefile b/vlsi/Makefile index 0693db7e57..9759ce41a0 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -54,7 +54,7 @@ endif ######################################################################################### # general rules ######################################################################################### -.PHONY: default +.PHONY: default all default: all all: drc lvs @@ -82,7 +82,6 @@ ifneq ($(CUSTOM_VLOG), ) else cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u > $(VLSI_RTL) echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL) - echo $(build_dir)/EICG_wrapper.v >> $(VLSI_RTL) endif ######################################################################################### From 959cca64d242d6b990e73aec94cbcd1c6ad2c68d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 15 Feb 2023 14:26:33 -0800 Subject: [PATCH 2/4] Fix make help --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index 609fbf4915..912233717e 100644 --- a/common.mk +++ b/common.mk @@ -17,7 +17,7 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \ -" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog) \ +" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler" From 64bc8c1d077a481521ac36a09c46ad7a2fccdc64 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 15 Feb 2023 14:26:53 -0800 Subject: [PATCH 3/4] Bump SBT to 1.8.2 --- project/build.properties | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/project/build.properties b/project/build.properties index 10fd9eee04..46e43a97ed 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.5.5 +sbt.version=1.8.2 From aa02295a0b01919bc0a5b7134f05709cc457d266 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 15 Feb 2023 19:24:43 -0800 Subject: [PATCH 4/4] Fix spacing of AbstactConfig --- generators/chipyard/src/main/scala/config/AbstractConfig.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 3df76ed9ae..191954f613 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -51,7 +51,7 @@ class AbstractConfig extends Config( new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus - new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model + new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)