From c027a93c553f9ae448edb505601f0c89595549de Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 14 Dec 2021 17:09:43 -0800 Subject: [PATCH 1/3] Split ConfigFragments.scala into multiple files by usage --- docs/Customization/Heterogeneous-SoCs.rst | 2 +- docs/Generators/SiFive-Generators.rst | 2 +- .../src/main/scala/ConfigFragments.scala | 340 ------------------ .../config/fragments/ClockingFragments.scala | 132 +++++++ .../fragments/PeripheralFragments.scala | 74 ++++ .../config/fragments/RoCCFragments.scala | 85 +++++ .../config/fragments/SubsystemFragments.scala | 11 + .../config/fragments/TileFragments.scala | 67 ++++ .../config/fragments/TracegenFragments.scala | 13 + 9 files changed, 384 insertions(+), 342 deletions(-) delete mode 100644 generators/chipyard/src/main/scala/ConfigFragments.scala create mode 100644 generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala create mode 100644 generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala create mode 100644 generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala create mode 100644 generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala create mode 100644 generators/chipyard/src/main/scala/config/fragments/TileFragments.scala create mode 100644 generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index 7e31108bb0..1f5343932f 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -38,7 +38,7 @@ All with the same Hwacha parameters. Assigning Accelerators to Specific Tiles with MultiRoCC ------------------------------------------------------- -Located in ``generators/chipyard/src/main/scala/ConfigFragments.scala`` is a config fragment that provides support for adding RoCC accelerators to specific tiles in your SoC. +Located in ``generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala`` is a config fragment that provides support for adding RoCC accelerators to specific tiles in your SoC. Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile. For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles. An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached. diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/SiFive-Generators.rst index 7ac0105f82..40b741d9c7 100644 --- a/docs/Generators/SiFive-Generators.rst +++ b/docs/Generators/SiFive-Generators.rst @@ -18,7 +18,7 @@ Peripheral Devices These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well. To integrate one of these devices in your SoC, you will need to define a custom config fragment with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following config fragment to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. -.. literalinclude:: ../../generators/chipyard/src/main/scala/ConfigFragments.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala :language: scala :start-after: DOC include start: gpio config fragment :end-before: DOC include end: gpio config fragment diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala deleted file mode 100644 index a41bfae008..0000000000 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ /dev/null @@ -1,340 +0,0 @@ -package chipyard.config - -import scala.util.matching.Regex -import chisel3._ -import chisel3.util.{log2Up} - -import freechips.rocketchip.config.{Field, Parameters, Config} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.devices.tilelink.{BootROMLocated} -import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} -import freechips.rocketchip.groundtest.{GroundTestSubsystem} -import freechips.rocketchip.tile._ -import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} -import freechips.rocketchip.tilelink.{HasTLBusParams} -import freechips.rocketchip.util.{AsyncResetReg, Symmetric} -import freechips.rocketchip.prci._ -import freechips.rocketchip.stage.phases.TargetDirKey - -import testchipip._ -import tracegen.{TraceGenSystem} - -import hwacha.{Hwacha} -import gemmini._ - -import boom.common.{BoomTileAttachParams} -import cva6.{CVA6TileAttachParams} - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ - -import chipyard._ -import chipyard.clocking._ - -// ----------------------- -// Common Config Fragments -// ----------------------- - -class WithBootROM extends Config((site, here, up) => { - case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img")) -}) - -// DOC include start: gpio config fragment -class WithGPIO extends Config((site, here, up) => { - case PeripheryGPIOKey => Seq( - GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) -}) -// DOC include end: gpio config fragment - -class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => { - case PeripheryUARTKey => Seq( - UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) -}) - -class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => { - // Note: the default size matches freedom with the addresses below - case PeripherySPIFlashKey => Seq( - SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) -}) - -class WithL2TLBs(entries: Int) extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nL2TLBEntries = entries))) - case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nL2TLBEntries = entries))) - case other => other - } -}) - -class TraceGenTop(implicit p: Parameters) extends TraceGenSystem - with HasChipyardPRCI -class WithTracegenSystem extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new TraceGenTop()(p) -}) - -/** - * Map from a hartId to a particular RoCC accelerator - */ -case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]]) - -/** - * Config fragment to enable different RoCCs based on the hartId - */ -class WithMultiRoCC extends Config((site, here, up) => { - case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil) -}) - -/** - * Assigns what was previously in the BuildRoCC key to specific harts with MultiRoCCKey - * Must be paired with WithMultiRoCC - */ -class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) => { - case BuildRoCC => Nil - case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => - (i -> up(BuildRoCC, site)) - } -}) - -/** - * Config fragment to add Hwachas to cores based on hart - * - * For ex: - * Core 0, 1, 2, 3 have been defined earlier - * with hartIds of 0, 1, 2, 3 respectively - * And you call WithMultiRoCCHwacha(0,1) - * Then Core 0 and 1 will get a Hwacha - * - * @param harts harts to specify which will get a Hwacha - */ -class WithMultiRoCCHwacha(harts: Int*) extends Config( - new chipyard.config.WithHwachaTest ++ - new Config((site, here, up) => { - case MultiRoCCKey => { - up(MultiRoCCKey, site) ++ harts.distinct.map{ i => - (i -> Seq((p: Parameters) => { - val hwacha = LazyModule(new Hwacha()(p)) - hwacha - })) - } - } - }) -) - -class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data]( - harts: Int*)(gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.defaultConfig) extends Config((site, here, up) => { - case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => - (i -> Seq((p: Parameters) => { - implicit val q = p - val gemmini = LazyModule(new Gemmini(gemminiConfig)) - gemmini - })) - } -}) - -class WithTraceIO extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - trace = true)) - case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - trace = true)) - case other => other - } - case TracePortKey => Some(TracePortParams()) -}) - -class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nPerfCounters = n))) - case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nPerfCounters = n))) - case other => other - } -}) - -class WithNPMPs(n: Int = 8) extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nPMPs = n))) - case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nPMPs = n))) - case other => other - } -}) - -class WithRocketICacheScratchpad extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site) map { r => - r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x300000 + r.hartId * 0x10000)))) - } -}) - -class WithRocketDCacheScratchpad extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site) map { r => - r.copy(dcache = r.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + r.hartId * 0x10000)))) - } -}) - -// Replaces the L2 with a broadcast manager for maintaining coherence -class WithBroadcastManager extends Config((site, here, up) => { - case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) -}) - -class WithHwachaTest extends Config((site, here, up) => { - case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => { - up(TestSuitesKey).apply(tileParams, suiteHelper, p) - import hwacha.HwachaTestSuites._ - suiteHelper.addSuites(rv64uv.map(_("p"))) - suiteHelper.addSuites(rv64uv.map(_("vp"))) - suiteHelper.addSuite(rv64sv("p")) - suiteHelper.addSuite(hwachaBmarks) - "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha" - } -}) - -// The default RocketChip BaseSubsystem drives its diplomatic clock graph -// with the implicit clocks of Subsystem. Don't do that, instead we extend -// the diplomacy graph upwards into the ChipTop, where we connect it to -// our clock drivers -class WithNoSubsystemDrivenClocks extends Config((site, here, up) => { - case SubsystemDriveAsyncClockGroupsKey => None -}) - -class WithDMIDTM extends Config((site, here, up) => { - case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) -}) - -class WithNoDebug extends Config((site, here, up) => { - case DebugModuleKey => None -}) - -class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => { - case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere) -}) - -class WithTLBackingMemory extends Config((site, here, up) => { - case ExtMem => None // disable AXI backing memory - case ExtTLMem => up(ExtMem, site) // enable TL backing memory -}) - -class WithSerialTLBackingMemory extends Config((site, here, up) => { - case ExtMem => None - case SerialTLKey => up(SerialTLKey, site).map { k => k.copy( - memParams = { - val memPortParams = up(ExtMem, site).get - require(memPortParams.nMemoryChannels == 1) - memPortParams.master - }, - isMemoryDevice = true - )} -}) - -/** - * Mixins to define either a specific tile frequency for a single hart or all harts - * - * @param fMHz Frequency in MHz of the tile or all tiles - * @param hartId Optional hartid to assign the frequency to (if unspecified default to all harts) - */ -class WithTileFrequency(fMHz: Double, hartId: Option[Int] = None) extends ClockNameContainsAssignment({ - hartId match { - case Some(id) => s"tile_$id" - case None => "tile" - } - }, - fMHz) - -class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { - case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble -}) - -class WithSystemBusFrequencyAsDefault extends Config((site, here, up) => { - case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toDouble -}) - -class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => { - case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++ - Seq((cName: String) => site(key).dtsFrequency.flatMap { f => - re.findFirstIn(cName).map {_ => (f / (1000 * 1000)).toDouble } - }) -}) - -/** - * Provides a diplomatic frequency for all clock sinks with an unspecified - * frequency bound to each bus. - * - * For example, the L2 cache, when bound to the sbus, receives a separate - * clock that appears as "subsystem_sbus_". This fragment ensures that - * clock requests the same frequency as the sbus itself. - */ - -class WithInheritBusFrequencyAssignments extends Config( - new BusFrequencyAssignment("subsystem_sbus_\\d+".r, SystemBusKey) ++ - new BusFrequencyAssignment("subsystem_pbus_\\d+".r, PeripheryBusKey) ++ - new BusFrequencyAssignment("subsystem_cbus_\\d+".r, ControlBusKey) ++ - new BusFrequencyAssignment("subsystem_fbus_\\d+".r, FrontBusKey) ++ - new BusFrequencyAssignment("subsystem_mbus_\\d+".r, MemoryBusKey) -) - -/** - * Mixins to specify crossing types between the 5 traditional TL buses - * - * Note: these presuppose the legacy connections between buses and set - * parameters in SubsystemCrossingParams; they may not be resuable in custom - * topologies (but you can specify the desired crossings in your topology). - * - * @param xType The clock crossing type - * - */ - -class WithSbusToMbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case SbusToMbusXTypeKey => xType -}) -class WithSbusToCbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case SbusToCbusXTypeKey => xType -}) -class WithCbusToPbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case CbusToPbusXTypeKey => xType -}) -class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { - case FbusToSbusXTypeKey => xType -}) - -/** - * Mixins to set the dtsFrequency field of BusParams -- these will percolate its way - * up the diplomatic graph to the clock sources. - */ -class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) -}) -class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) -}) -class WithSystemBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case SystemBusKey => up(SystemBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) -}) -class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) -}) -class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) -}) - -class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric)) -class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing()) - -class WithTestChipBusFreqs extends Config( - // Frequency specifications - new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 - new chipyard.config.WithSystemBusFrequency(800.0) ++ // Put the system bus at a lower freq, representative of ncore working at a lower frequency than the tiles. Same freq as U540 - new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus) - new chipyard.config.WithPeripheryBusFrequency(800.0) ++ // Match the sbus and pbus frequency - new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (800 MHz) - // Crossing specifications - new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS - new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS - new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore - new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore - new testchipip.WithAsynchronousSerialSlaveCrossing // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS -) diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala new file mode 100644 index 0000000000..c4172a7aeb --- /dev/null +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -0,0 +1,132 @@ +package chipyard.config + +import scala.util.matching.Regex +import chisel3._ +import chisel3.util.{log2Up} + +import freechips.rocketchip.config.{Field, Parameters, Config} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.prci._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.util.{Symmetric} +import freechips.rocketchip.tilelink.{HasTLBusParams} + +import chipyard._ +import chipyard.clocking._ + + +// The default RocketChip BaseSubsystem drives its diplomatic clock graph +// with the implicit clocks of Subsystem. Don't do that, instead we extend +// the diplomacy graph upwards into the ChipTop, where we connect it to +// our clock drivers +class WithNoSubsystemDrivenClocks extends Config((site, here, up) => { + case SubsystemDriveAsyncClockGroupsKey => None +}) + +/** + * Mixins to define either a specific tile frequency for a single hart or all harts + * + * @param fMHz Frequency in MHz of the tile or all tiles + * @param hartId Optional hartid to assign the frequency to (if unspecified default to all harts) + */ +class WithTileFrequency(fMHz: Double, hartId: Option[Int] = None) extends ClockNameContainsAssignment({ + hartId match { + case Some(id) => s"tile_$id" + case None => "tile" + } + }, + fMHz) + +class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { + case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble +}) + +class WithSystemBusFrequencyAsDefault extends Config((site, here, up) => { + case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toDouble +}) + +class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => { + case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++ + Seq((cName: String) => site(key).dtsFrequency.flatMap { f => + re.findFirstIn(cName).map {_ => (f / (1000 * 1000)).toDouble } + }) +}) + +/** + * Provides a diplomatic frequency for all clock sinks with an unspecified + * frequency bound to each bus. + * + * For example, the L2 cache, when bound to the sbus, receives a separate + * clock that appears as "subsystem_sbus_". This fragment ensures that + * clock requests the same frequency as the sbus itself. + */ + +class WithInheritBusFrequencyAssignments extends Config( + new BusFrequencyAssignment("subsystem_sbus_\\d+".r, SystemBusKey) ++ + new BusFrequencyAssignment("subsystem_pbus_\\d+".r, PeripheryBusKey) ++ + new BusFrequencyAssignment("subsystem_cbus_\\d+".r, ControlBusKey) ++ + new BusFrequencyAssignment("subsystem_fbus_\\d+".r, FrontBusKey) ++ + new BusFrequencyAssignment("subsystem_mbus_\\d+".r, MemoryBusKey) +) + +/** + * Mixins to specify crossing types between the 5 traditional TL buses + * + * Note: these presuppose the legacy connections between buses and set + * parameters in SubsystemCrossingParams; they may not be resuable in custom + * topologies (but you can specify the desired crossings in your topology). + * + * @param xType The clock crossing type + * + */ + +class WithSbusToMbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case SbusToMbusXTypeKey => xType +}) +class WithSbusToCbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case SbusToCbusXTypeKey => xType +}) +class WithCbusToPbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case CbusToPbusXTypeKey => xType +}) +class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => { + case FbusToSbusXTypeKey => xType +}) + +/** + * Mixins to set the dtsFrequency field of BusParams -- these will percolate its way + * up the diplomatic graph to the clock sources. + */ +class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithSystemBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case SystemBusKey => up(SystemBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) + +class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric)) +class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing()) + +class WithTestChipBusFreqs extends Config( + // Frequency specifications + new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 + new chipyard.config.WithSystemBusFrequency(800.0) ++ // Put the system bus at a lower freq, representative of ncore working at a lower frequency than the tiles. Same freq as U540 + new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus) + new chipyard.config.WithPeripheryBusFrequency(800.0) ++ // Match the sbus and pbus frequency + new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (800 MHz) + // Crossing specifications + new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS + new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS + new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore + new testchipip.WithAsynchronousSerialSlaveCrossing // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS +) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala new file mode 100644 index 0000000000..0161edcced --- /dev/null +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -0,0 +1,74 @@ +package chipyard.config + +import scala.util.matching.Regex +import chisel3._ +import chisel3.util.{log2Up} + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.devices.tilelink.{BootROMLocated} +import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} +import freechips.rocketchip.stage.phases.TargetDirKey +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.tile.{XLen} + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ + +import testchipip._ + +import chipyard.{ExtTLMem} + +// Set the bootrom to the Chipyard bootrom +class WithBootROM extends Config((site, here, up) => { + case BootROMLocated(x) => up(BootROMLocated(x), site) + .map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img")) +}) + +// DOC include start: gpio config fragment +class WithGPIO extends Config((site, here, up) => { + case PeripheryGPIOKey => Seq( + GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) +}) +// DOC include end: gpio config fragment + +class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => { + case PeripheryUARTKey => Seq( + UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) +}) + +class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => { + // Note: the default size matches freedom with the addresses below + case PeripherySPIFlashKey => Seq( + SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) +}) + +class WithDMIDTM extends Config((site, here, up) => { + case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) +}) + +class WithNoDebug extends Config((site, here, up) => { + case DebugModuleKey => None +}) + +class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => { + case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere) +}) + +class WithTLBackingMemory extends Config((site, here, up) => { + case ExtMem => None // disable AXI backing memory + case ExtTLMem => up(ExtMem, site) // enable TL backing memory +}) + +class WithSerialTLBackingMemory extends Config((site, here, up) => { + case ExtMem => None + case SerialTLKey => up(SerialTLKey, site).map { k => k.copy( + memParams = { + val memPortParams = up(ExtMem, site).get + require(memPortParams.nMemoryChannels == 1) + memPortParams.master + }, + isMemoryDevice = true + )} +}) + diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala new file mode 100644 index 0000000000..646e0e6be7 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala @@ -0,0 +1,85 @@ +package chipyard.config + +import chisel3._ + +import freechips.rocketchip.config.{Field, Parameters, Config} +import freechips.rocketchip.tile._ +import freechips.rocketchip.diplomacy._ + +import hwacha.{Hwacha} +import gemmini._ + +import chipyard.{TestSuitesKey, TestSuiteHelper} + +/** + * Map from a hartId to a particular RoCC accelerator + */ +case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]]) + +/** + * Config fragment to enable different RoCCs based on the hartId + */ +class WithMultiRoCC extends Config((site, here, up) => { + case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil) +}) + +/** + * Assigns what was previously in the BuildRoCC key to specific harts with MultiRoCCKey + * Must be paired with WithMultiRoCC + */ +class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) => { + case BuildRoCC => Nil + case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => + (i -> up(BuildRoCC, site)) + } +}) + +/** + * Config fragment to add Hwachas to cores based on hart + * + * For ex: + * Core 0, 1, 2, 3 have been defined earlier + * with hartIds of 0, 1, 2, 3 respectively + * And you call WithMultiRoCCHwacha(0,1) + * Then Core 0 and 1 will get a Hwacha + * + * @param harts harts to specify which will get a Hwacha + */ +class WithMultiRoCCHwacha(harts: Int*) extends Config( + new chipyard.config.WithHwachaTest ++ + new Config((site, here, up) => { + case MultiRoCCKey => { + up(MultiRoCCKey, site) ++ harts.distinct.map{ i => + (i -> Seq((p: Parameters) => { + val hwacha = LazyModule(new Hwacha()(p)) + hwacha + })) + } + } + }) +) + +class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data]( + harts: Int*)(gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.defaultConfig) extends Config((site, here, up) => { + case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => + (i -> Seq((p: Parameters) => { + implicit val q = p + val gemmini = LazyModule(new Gemmini(gemminiConfig)) + gemmini + })) + } +}) + + +class WithHwachaTest extends Config((site, here, up) => { + case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => { + up(TestSuitesKey).apply(tileParams, suiteHelper, p) + import hwacha.HwachaTestSuites._ + suiteHelper.addSuites(rv64uv.map(_("p"))) + suiteHelper.addSuites(rv64uv.map(_("vp"))) + suiteHelper.addSuite(rv64sv("p")) + suiteHelper.addSuite(hwachaBmarks) + "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha" + } +}) + diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala new file mode 100644 index 0000000000..144e57625f --- /dev/null +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -0,0 +1,11 @@ +package chipyard.config + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.subsystem.{BankedL2Key, CoherenceManagerWrapper} + +// Replaces the L2 with a broadcast manager for maintaining coherence +class WithBroadcastManager extends Config((site, here, up) => { + case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) +}) + + diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala new file mode 100644 index 0000000000..906f2a9508 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -0,0 +1,67 @@ +package chipyard.config + +import chisel3._ + +import freechips.rocketchip.config.{Field, Parameters, Config} +import freechips.rocketchip.tile._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} + +import boom.common.{BoomTileAttachParams} +import cva6.{CVA6TileAttachParams} + +import testchipip._ + +class WithL2TLBs(entries: Int) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nL2TLBEntries = entries))) + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nL2TLBEntries = entries))) + case other => other + } +}) + +class WithTraceIO extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + trace = true)) + case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + trace = true)) + case other => other + } + case TracePortKey => Some(TracePortParams()) +}) + +class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nPerfCounters = n))) + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nPerfCounters = n))) + case other => other + } +}) + +class WithNPMPs(n: Int = 8) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nPMPs = n))) + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nPMPs = n))) + case other => other + } +}) + +class WithRocketICacheScratchpad extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey, site) map { r => + r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x300000 + r.hartId * 0x10000)))) + } +}) + +class WithRocketDCacheScratchpad extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey, site) map { r => + r.copy(dcache = r.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + r.hartId * 0x10000)))) + } +}) + diff --git a/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala new file mode 100644 index 0000000000..dbb4fb73d8 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala @@ -0,0 +1,13 @@ +package chipyard.config + +import freechips.rocketchip.config.{Config, Field, Parameters} +import tracegen.{TraceGenSystem} +import chipyard.{BuildSystem} +import chipyard.clocking.{HasChipyardPRCI} + +class TraceGenTop(implicit p: Parameters) extends TraceGenSystem + with HasChipyardPRCI +class WithTracegenSystem extends Config((site, here, up) => { + case BuildSystem => (p: Parameters) => new TraceGenTop()(p) +}) + From 21f3865ec6470518a98b49b41732ca47fa8085da Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 14 Dec 2021 17:29:40 -0800 Subject: [PATCH 2/3] Remove firrtl-interpreter and treadle from GH actions check-commit script --- .github/scripts/check-commit.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index 87b27ea7e2..e056921db8 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -89,7 +89,7 @@ else fi search -submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "rocket-dsp-utils" "firrtl-interpreter" "torture" "treadle") +submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "rocket-dsp-utils" "torture") dir="tools" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then From 657faf22988b018a4c27bd5c770578f45b4f1a07 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 Dec 2021 17:27:19 -0800 Subject: [PATCH 3/3] Update comments on config fragments --- .../config/fragments/RoCCFragments.scala | 26 ++++++++++--------- .../config/fragments/SubsystemFragments.scala | 1 - .../config/fragments/TracegenFragments.scala | 1 + 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala index 646e0e6be7..774b23c234 100644 --- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala @@ -59,18 +59,6 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config( }) ) -class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data]( - harts: Int*)(gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.defaultConfig) extends Config((site, here, up) => { - case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => - (i -> Seq((p: Parameters) => { - implicit val q = p - val gemmini = LazyModule(new Gemmini(gemminiConfig)) - gemmini - })) - } -}) - - class WithHwachaTest extends Config((site, here, up) => { case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => { up(TestSuitesKey).apply(tileParams, suiteHelper, p) @@ -83,3 +71,17 @@ class WithHwachaTest extends Config((site, here, up) => { } }) +/** + * The MultiRoCCGemmini fragment functions similarly to the + * WithMultiRoCCHwacha fragment defined above + */ +class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data]( + harts: Int*)(gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.defaultConfig) extends Config((site, here, up) => { + case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => + (i -> Seq((p: Parameters) => { + implicit val q = p + val gemmini = LazyModule(new Gemmini(gemminiConfig)) + gemmini + })) + } +}) diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index 144e57625f..47f24cdc77 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -8,4 +8,3 @@ class WithBroadcastManager extends Config((site, here, up) => { case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) }) - diff --git a/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala index dbb4fb73d8..9640be9ee7 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala @@ -7,6 +7,7 @@ import chipyard.clocking.{HasChipyardPRCI} class TraceGenTop(implicit p: Parameters) extends TraceGenSystem with HasChipyardPRCI + class WithTracegenSystem extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => new TraceGenTop()(p) })