From 30df6dad0b1898390383297e7afe702b63a18628 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 23 Feb 2023 11:01:33 -0800 Subject: [PATCH 01/15] add disallowPackedArrays --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index f592fa5ce2..7b99193230 100644 --- a/common.mk +++ b/common.mk @@ -196,7 +196,7 @@ endif --disable-annotation-classless \ --disable-annotation-unknown \ --mlir-timing \ - --lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ + --lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,disallowPackedArrays,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ --repl-seq-mem \ --repl-seq-mem-file=$(MFC_SMEMS_CONF) \ --repl-seq-mem-circuit=$(MODEL) \ From 07b194e85adea5e9c82ba781d0f1bb1f348547f2 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 23 Feb 2023 11:01:33 -0800 Subject: [PATCH 02/15] add disallowPackedArrays --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index 73d2d6c4cf..e3926deb05 100644 --- a/common.mk +++ b/common.mk @@ -208,7 +208,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LE --disable-annotation-classless \ --disable-annotation-unknown \ --mlir-timing \ - --lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ + --lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,disallowPackedArrays,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ --repl-seq-mem \ --repl-seq-mem-file=$(MFC_SMEMS_CONF) \ --repl-seq-mem-circuit=$(MODEL) \ From af2a146397fc83463426f87c575c223e1703f037 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Wed, 1 Mar 2023 10:50:57 -0800 Subject: [PATCH 03/15] bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 30900965f0..39b4af7da9 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 30900965f0cc2d5046e2160dd9c700805a8e0542 +Subproject commit 39b4af7da9725acb56ffd809b3679facf7fee6b2 From 3a53dc60d0dd9c5e16950dfaba846f078eb00513 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Fri, 3 Mar 2023 22:34:00 -0800 Subject: [PATCH 04/15] Add ENABLE_VLSI_FLOW flag --- common.mk | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/common.mk b/common.mk index e3926deb05..b1738926f9 100644 --- a/common.mk +++ b/common.mk @@ -18,6 +18,7 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \ " ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \ +" ENABLE_VLSI_FLOW = if set, add compilation flags to enable the vlsi flow for hammer \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler" @@ -26,6 +27,11 @@ EXTRA_SIM_CXXFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= EXTRA_SIM_REQS ?= +ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_VLSI_FLOW) + + +$(info $$ENABLE_CUSTOM_FIRRTL_PASS is [${ENABLE_CUSTOM_FIRRTL_PASS}]) +$(info $$ENABLE_VLSI_FLOW is [${ENABLE_VLSI_FLOW}]) #---------------------------------------------------------------------------- HELP_SIMULATION_VARIABLES += \ From e3424f7193286e4c68bbf76c5517e2a5cde290b3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 3 Mar 2023 16:50:00 -0800 Subject: [PATCH 05/15] Remove chisel-testers submodule --- .github/scripts/check-commit.sh | 2 +- .gitmodules | 3 --- docs/Tools/Chisel-Testers.rst | 7 ------- docs/Tools/index.rst | 1 - tools/chisel-testers | 1 - 5 files changed, 1 insertion(+), 13 deletions(-) delete mode 100644 docs/Tools/Chisel-Testers.rst delete mode 160000 tools/chisel-testers diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index 11d12599da..a9c0300b15 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -88,7 +88,7 @@ dir="software" branches=("master" "dev") search -submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "rocket-dsp-utils" "torture") +submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture") dir="tools" branches=("master" "dev") search diff --git a/.gitmodules b/.gitmodules index 5d4b82262d..82e738199c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -31,9 +31,6 @@ [submodule "tools/dsptools"] path = tools/dsptools url = https://github.com/ucb-bar/dsptools.git -[submodule "tools/chisel-testers"] - path = tools/chisel-testers - url = https://github.com/freechipsproject/chisel-testers.git [submodule "generators/sha3"] path = generators/sha3 url = https://github.com/ucb-bar/sha3.git diff --git a/docs/Tools/Chisel-Testers.rst b/docs/Tools/Chisel-Testers.rst deleted file mode 100644 index 9570dd61e1..0000000000 --- a/docs/Tools/Chisel-Testers.rst +++ /dev/null @@ -1,7 +0,0 @@ -Chisel Testers -============================== - -`Chisel Testers `__ is a library for writing tests for Chisel designs. -It provides a Scala API for interacting with a DUT. -It can use multiple backends, including things such as Treadle and Verilator. -See :ref:`Tools/Treadle:Treadle and FIRRTL Interpreter` and :ref:`sw-rtl-sim-intro` for more information on these simulation methods. diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst index fecb204350..8816126927 100644 --- a/docs/Tools/index.rst +++ b/docs/Tools/index.rst @@ -11,7 +11,6 @@ The following pages will introduce them, and how we can use them in order to gen Chisel FIRRTL Treadle - Chisel-Testers Dsptools Barstools Dromajo diff --git a/tools/chisel-testers b/tools/chisel-testers deleted file mode 160000 index ce4e027e5f..0000000000 --- a/tools/chisel-testers +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ce4e027e5f3d871df59236b8471ea3e5be40130e From 317e0db4fd996d64d9fd8d0363bf975f7bc59163 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 6 Mar 2023 14:00:20 -0800 Subject: [PATCH 06/15] Config finder `make` target (#1328) * Add config-finder make target * Add recursive functionality * Add config finder to CI * Workaround bash argument limit failures --- .github/workflows/chipyard-full-flow.yml | 13 ++++ common.mk | 16 ++++- docs/Customization/Keys-Traits-Configs.rst | 6 ++ scripts/config-finder.py | 76 ++++++++++++++++++++++ 4 files changed, 110 insertions(+), 1 deletion(-) create mode 100755 scripts/config-finder.py diff --git a/.github/workflows/chipyard-full-flow.yml b/.github/workflows/chipyard-full-flow.yml index 22382571d3..23bc7152e2 100644 --- a/.github/workflows/chipyard-full-flow.yml +++ b/.github/workflows/chipyard-full-flow.yml @@ -81,6 +81,19 @@ jobs: export MAKEFLAGS="-j32" ./build-setup.sh -f + run-cfg-finder: + name: run-cfg-finder + needs: [setup-repo] + runs-on: ferry + steps: + - name: Run config finder + run: | + cd ${{ env.REMOTE_WORK_DIR }} + eval "$(conda shell.bash hook)" + source env.sh + cd sims/verilator + make find-config-fragments + run-tutorial: name: run-tutorial needs: [setup-repo] diff --git a/common.mk b/common.mk index b1738926f9..02c55b16bc 100644 --- a/common.mk +++ b/common.mk @@ -54,6 +54,7 @@ HELP_COMMANDS += \ " run-tests = run all assembly and benchmark tests" \ " launch-sbt = start sbt terminal" \ " {shutdown,start}-sbt-server = shutdown or start sbt server if using ENABLE_SBT_THIN_CLIENT" \ +" find-config-fragments = list all config. fragments and their locations (recursive up to CONFIG_FRAG_LEVELS=$(CONFIG_FRAG_LEVELS))" ######################################################################################### # include additional subproject make fragments @@ -393,8 +394,21 @@ start-sbt-server: check-thin-client cd $(base_dir) && $(SBT) "exit" ######################################################################################### -# print help text +# print help text (and other help) ######################################################################################### +# helper to add newlines (avoid bash argument too long) +define \n + + +endef + +CONFIG_FRAG_LEVELS ?= 3 +.PHONY: find-config-fragments +find-config-fragments: $(SCALA_SOURCES) + rm -rf /tmp/scala_files.f + @$(foreach file,$(SCALA_SOURCES),echo $(file) >> /tmp/scala_files.f${\n}) + $(base_dir)/scripts/config-finder.py -l $(CONFIG_FRAG_LEVELS) /tmp/scala_files.f + .PHONY: help help: @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index c92ad2013b..364f31cb1f 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -75,3 +75,9 @@ We can use this config fragment when composing our configs. .. note:: Readers who want more information on the configuration system may be interested in reading :ref:`cdes`. + +Chipyard Config Fragments +------------------------- + +For discoverability, users can run ``make find-config-fragments`` to see a list of config. fragments +(config. fragments that match "class NAME extends CONFIG\n" on a single line and a subset of their children) and their file path in a fully initialized Chipyard repository. diff --git a/scripts/config-finder.py b/scripts/config-finder.py new file mode 100755 index 0000000000..a7377939cb --- /dev/null +++ b/scripts/config-finder.py @@ -0,0 +1,76 @@ +#!/usr/bin/env python3 + +import argparse +import subprocess +from collections import defaultdict +import re +from copy import deepcopy +import os + +cy_path = os.path.dirname(os.path.dirname(os.path.realpath(__file__))) + +# from https://gist.github.com/angstwad/bf22d1822c38a92ec0a9 +def deep_merge(a: dict, b: dict) -> dict: + """Merge two dicts and return a singular dict""" + result = deepcopy(a) + for bk, bv in b.items(): + av = result.get(bk) + if isinstance(av, dict) and isinstance(bv, dict): + result[bk] = deep_merge(av, bv) + else: + result[bk] = deepcopy(bv) + return result + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description='Pretty print all configs given a filelist of scala files') + parser.add_argument('FILE', type=str, help='Filelist of scala files to search within') + parser.add_argument('-l', '--levels', default=0, type=int, help='Number of levels to recursively look for configs') + args = parser.parse_args() + + files = [] + with open(args.FILE, 'r') as f: + files = f.read().splitlines() + + cmd = ['grep', '-o', r"class \+.* \+extends \+Config"] + files + r = subprocess.run(cmd, check=True, capture_output=True) + + base_file_path_dict = defaultdict(list) + for l in r.stdout.decode("UTF-8").splitlines(): + match = re.match(r"^(.*):class +([a-zA-Z_$][a-zA-Z\d_$]*).* +extends", l) + if match: + base_file_path_dict[match.group(1)].append(match.group(2)) + + levels = [] + for level in range(args.levels): + if level == 0: + # use the base + dict_to_use = base_file_path_dict + else: + # use the level-1 dict + assert len(levels) > 0 + dict_to_use = levels[-1] + + file_path_dict = defaultdict(list) + + for configs in dict_to_use.values(): + for config in configs: + cmd = ['grep', '-o', r"class \+.* \+extends \+" + f"{config}"] + files + r = subprocess.run(cmd, capture_output=True) + + for l in r.stdout.decode("UTF-8").splitlines(): + match = re.match(r"^(.*):class +([a-zA-Z_$][a-zA-Z\d_$]*).* +extends", l) + if match: + file_path_dict[match.group(1)].append(match.group(2)) + + levels.append(file_path_dict) + + final_dict = base_file_path_dict + for dct in levels: + final_dict = deep_merge(final_dict, dct) + + print(f"Finding all one-line config. fragments (up to {args.levels} levels)\n") + for k, v in final_dict.items(): + print(f"{k.replace(cy_path, 'chipyard')}:") + for e in v: + print(f" {e}") + print("") From 2ef3b58cfaa0086859e78a44762ad2c3041ff58d Mon Sep 17 00:00:00 2001 From: joey0320 Date: Mon, 6 Mar 2023 18:12:08 -0800 Subject: [PATCH 07/15] Revert "bump barstools" This reverts commit af2a146397fc83463426f87c575c223e1703f037. --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 39b4af7da9..30900965f0 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 39b4af7da9725acb56ffd809b3679facf7fee6b2 +Subproject commit 30900965f0cc2d5046e2160dd9c700805a8e0542 From 02fd30b2f890ab9b66f77068ee2f1407928afa92 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Mon, 6 Mar 2023 18:26:03 -0800 Subject: [PATCH 08/15] Fix makefile --- common.mk | 14 ++++++++------ vlsi/Makefile | 2 ++ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/common.mk b/common.mk index 02c55b16bc..3d5985524b 100644 --- a/common.mk +++ b/common.mk @@ -29,10 +29,6 @@ EXTRA_SIM_SOURCES ?= EXTRA_SIM_REQS ?= ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_VLSI_FLOW) - -$(info $$ENABLE_CUSTOM_FIRRTL_PASS is [${ENABLE_CUSTOM_FIRRTL_PASS}]) -$(info $$ENABLE_VLSI_FLOW is [${ENABLE_VLSI_FLOW}]) - #---------------------------------------------------------------------------- HELP_SIMULATION_VARIABLES += \ " EXTRA_SIM_FLAGS = additional runtime simulation flags (passed within +permissive)" \ @@ -165,6 +161,7 @@ SFC_MFC_TARGETS = \ $(GEN_COLLATERAL_DIR) SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) +MFC_BASE_LOWERING_OPTIONS = emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket # DOC include start: FirrtlCompiler # There are two possible cases for this step. In the first case, SFC @@ -177,13 +174,18 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) # hack: lower to low firrtl if Fixed types are found # hack: when using dontTouch, io.cpu annotations are not removed by SFC, # hence we remove them manually by using jq before passing them to firtool -$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) +$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS)) $(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none)) $(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),)) else $(eval SFC_LEVEL := low) $(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM)) +endif +ifeq (,$(ENABLE_VLSI_FLOW)) + $(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS)) +else + $(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays) endif if [ $(SFC_LEVEL) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi @@ -215,7 +217,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LE --disable-annotation-classless \ --disable-annotation-unknown \ --mlir-timing \ - --lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,disallowPackedArrays,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ + --lowering-options=$(MFC_LOWERING_OPTIONS) \ --repl-seq-mem \ --repl-seq-mem-file=$(MFC_SMEMS_CONF) \ --repl-seq-mem-circuit=$(MODEL) \ diff --git a/vlsi/Makefile b/vlsi/Makefile index ab8438d50c..f54067e353 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -51,6 +51,8 @@ else OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) endif +ENABLE_VLSI_FLOW ?= 1 + ######################################################################################### # general rules ######################################################################################### From 817b6dece9407875ba9aebcec4eb310458536c33 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 7 Mar 2023 11:25:27 -0800 Subject: [PATCH 09/15] Use temp directory for config finder (#1381) --- common.mk | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index 3d5985524b..e6cd140457 100644 --- a/common.mk +++ b/common.mk @@ -406,10 +406,11 @@ endef CONFIG_FRAG_LEVELS ?= 3 .PHONY: find-config-fragments +find-config-fragments: private IN_F := $(shell mktemp -d -t cy-XXXXXXXX)/scala_files.f find-config-fragments: $(SCALA_SOURCES) - rm -rf /tmp/scala_files.f - @$(foreach file,$(SCALA_SOURCES),echo $(file) >> /tmp/scala_files.f${\n}) - $(base_dir)/scripts/config-finder.py -l $(CONFIG_FRAG_LEVELS) /tmp/scala_files.f + @$(foreach file,$(SCALA_SOURCES),echo $(file) >> $(IN_F)${\n}) + $(base_dir)/scripts/config-finder.py -l $(CONFIG_FRAG_LEVELS) $(IN_F) + @rm -rf $(dir $(IN_F)) .PHONY: help help: From 4add9f7e9eb60b4fa8eae8a02b6c985498692656 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 22 Feb 2023 22:45:16 -0800 Subject: [PATCH 10/15] Move .ivy2 and .sbt into Chipyard root --- .gitignore | 2 ++ variables.mk | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index d3cf251d14..9c73c6e1c6 100644 --- a/.gitignore +++ b/.gitignore @@ -24,3 +24,5 @@ first-clone-setup-fast-log project/.bloop/ project/metals.sbt project/project/ +.ivy2 +.sbt diff --git a/variables.mk b/variables.mk index a89d23a0f4..27d9645b0a 100644 --- a/variables.mk +++ b/variables.mk @@ -222,7 +222,8 @@ SBT_CLIENT_FLAG = --client endif # passes $(JAVA_TOOL_OPTIONS) from env to java -SBT_BIN ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar +export SBT_OPTS ?= -Dsbt.ivy.home=$(base_dir)/.ivy2 -Dsbt.global.base=$(base_dir)/.sbt -Dsbt.boot.directory=$(base_dir)/.sbt/boot/ +SBT_BIN ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) SBT = $(SBT_BIN) $(SBT_CLIENT_FLAG) SBT_NON_THIN = $(subst $(SBT_CLIENT_FLAG),,$(SBT)) From 2acb986ba1c8cfdb42b53dfb6f502f7e3589f03a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 5 Mar 2023 22:40:05 -0800 Subject: [PATCH 11/15] Use local .ivy/.sbt in FireSim | Disable supershell | Rework remote env. vars. --- .github/scripts/defaults.sh | 6 ++---- .github/scripts/remote-do-rtl-build.sh | 6 ++++-- .github/scripts/remote-run-firesim-scala-tests.sh | 7 ++++--- .github/workflows/chipyard-full-flow.yml | 1 + variables.mk | 2 +- 5 files changed, 12 insertions(+), 10 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index fb83ad00ba..6013d7d492 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -14,9 +14,6 @@ REMOTE_CHIPYARD_DIR=$GITHUB_WORKSPACE REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim REMOTE_FPGA_DIR=$REMOTE_CHIPYARD_DIR/fpga -REMOTE_JAVA_OPTS="-Xmx10G -Xss8M" -# Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI -REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" # local variables (aka within the docker container) LOCAL_CHIPYARD_DIR=$GITHUB_WORKSPACE @@ -26,7 +23,8 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # CI uses temp directories with very long names # explicitly force socket creation to use /tmp to avoid name length errors # https://github.com/sbt/sbt/pull/6887 -JAVA_TMP_DIR=$(mktemp -d -t ci-cy-XXXXXXXX) +REMOTE_JAVA_TMP_DIR=$(mktemp -d -t ci-cy-XXXXXXXX) +REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping diff --git a/.github/scripts/remote-do-rtl-build.sh b/.github/scripts/remote-do-rtl-build.sh index b5755d0156..445c1c31eb 100755 --- a/.github/scripts/remote-do-rtl-build.sh +++ b/.github/scripts/remote-do-rtl-build.sh @@ -52,6 +52,8 @@ read -a keys <<< ${grouping[$1]} # need to set the PATH to use the new verilator (with the new verilator root) for key in "${keys[@]}" do - export COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache - make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_TMP_DIR=$JAVA_TMP_DIR SBT_OPTS="$REMOTE_SBT_OPTS" ${mapping[$key]} + export COURSIER_CACHE=$REMOTE_COURSIER_CACHE + export JVM_MEMORY=10G + export JAVA_TMP_DIR=$REMOTE_JAVA_TMP_DIR + make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info ${mapping[$key]} done diff --git a/.github/scripts/remote-run-firesim-scala-tests.sh b/.github/scripts/remote-run-firesim-scala-tests.sh index 960d170699..70a41e27d3 100755 --- a/.github/scripts/remote-run-firesim-scala-tests.sh +++ b/.github/scripts/remote-run-firesim-scala-tests.sh @@ -15,6 +15,7 @@ cd $REMOTE_CHIPYARD_DIR # Run Firesim Scala Tests export FIRESIM_ENV_SOURCED=1; -export COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache -JAVA_TOOL_OPTIONS="$REMOTE_JAVA_OPTS -Djava.io.tmpdir=$(mktemp -d -t cy-fsim-XXXXXXXX)" -make -C $REMOTE_FIRESIM_DIR JAVA_TOOL_OPTIONS="$JAVA_TOOL_OPTIONS" SBT_OPTS="$REMOTE_SBT_OPTS" TARGET_SBT_PROJECT="{file:$REMOTE_CHIPYARD_DIR}firechip" testOnly ${mapping[$1]} +export COURSIER_CACHE=$REMOTE_COURSIER_CACHE +export JVM_MEMORY=10G +export JAVA_TMP_DIR=$REMOTE_JAVA_TMP_DIR +make -C $REMOTE_FIRESIM_DIR TARGET_SBT_PROJECT="{file:$REMOTE_CHIPYARD_DIR}firechip" testOnly ${mapping[$1]} diff --git a/.github/workflows/chipyard-full-flow.yml b/.github/workflows/chipyard-full-flow.yml index 23bc7152e2..7fe09a23a4 100644 --- a/.github/workflows/chipyard-full-flow.yml +++ b/.github/workflows/chipyard-full-flow.yml @@ -78,6 +78,7 @@ jobs: run: | cd ${{ env.REMOTE_WORK_DIR }} eval "$(conda shell.bash hook)" + mkdir ${{ env.JAVA_TMP_DIR }} export MAKEFLAGS="-j32" ./build-setup.sh -f diff --git a/variables.mk b/variables.mk index 27d9645b0a..28727a26e8 100644 --- a/variables.mk +++ b/variables.mk @@ -205,7 +205,7 @@ sim_common_files ?= $(build_dir)/sim_files.common.f ######################################################################################### JAVA_HEAP_SIZE ?= 8G JAVA_TMP_DIR ?= $(base_dir)/.java_tmp -export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Djava.io.tmpdir=$(JAVA_TMP_DIR) +export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Dsbt.supershell=false -Djava.io.tmpdir=$(JAVA_TMP_DIR) ######################################################################################### # default sbt launch command From c15a72d8e1e2fbffc22934018836c394e7cbe156 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 6 Mar 2023 22:42:20 -0800 Subject: [PATCH 12/15] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 9d3462ed13..69e428f010 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 9d3462ed1357cc198be8485ae57635b9651999d5 +Subproject commit 69e428f01029dbdb21f23288f74bd37f0f759a60 From fd8a49100c1812f554b427755db493e2db1c8c63 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Wed, 8 Mar 2023 09:24:48 -0800 Subject: [PATCH 13/15] update ENABLE_VLSI_FLOW to ENABLE_YOSYS_FLOW --- common.mk | 6 +++--- vlsi/Makefile | 2 -- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/common.mk b/common.mk index e6cd140457..c0893453ca 100644 --- a/common.mk +++ b/common.mk @@ -18,7 +18,7 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \ " ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \ -" ENABLE_VLSI_FLOW = if set, add compilation flags to enable the vlsi flow for hammer \ +" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow) \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler" @@ -27,7 +27,7 @@ EXTRA_SIM_CXXFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= EXTRA_SIM_REQS ?= -ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_VLSI_FLOW) +ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_YOSYS_FLOW) #---------------------------------------------------------------------------- HELP_SIMULATION_VARIABLES += \ @@ -182,7 +182,7 @@ else $(eval SFC_LEVEL := low) $(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM)) endif -ifeq (,$(ENABLE_VLSI_FLOW)) +ifeq (,$(ENABLE_YOSYS_FLOW)) $(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS)) else $(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays) diff --git a/vlsi/Makefile b/vlsi/Makefile index f54067e353..ab8438d50c 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -51,8 +51,6 @@ else OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) endif -ENABLE_VLSI_FLOW ?= 1 - ######################################################################################### # general rules ######################################################################################### From a4db80c3d3b3c3970579c1f2f027a5565e13d31d Mon Sep 17 00:00:00 2001 From: joey0320 Date: Wed, 8 Mar 2023 09:26:00 -0800 Subject: [PATCH 14/15] oops --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index c0893453ca..2f67b8d85c 100644 --- a/common.mk +++ b/common.mk @@ -18,7 +18,7 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \ " ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \ -" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow) \ +" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow) \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler" From 1b7a424c6987ae3e088cd78185c48486aa7741e1 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Wed, 8 Mar 2023 11:40:21 -0800 Subject: [PATCH 15/15] adding ENABLE_YOSYS_FLOW to tutorial makefile --- vlsi/tutorial.mk | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk index 9b69b14933..b3d8874147 100644 --- a/vlsi/tutorial.mk +++ b/vlsi/tutorial.mk @@ -1,7 +1,10 @@ ######################################################################################### # makefile variables for Hammer tutorials ######################################################################################### -tutorial ?= none +# tutorial ?= none +tutorial ?= sky130-openroad + +extra ?= # TODO: eventually have asap7 commercial/openroad tutorial flavors ifeq ($(tutorial),asap7) @@ -34,5 +37,7 @@ ifeq ($(tutorial),sky130-openroad) INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) VLSI_OBJ_DIR ?= build-sky130-openroad # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time. - ENABLE_CUSTOM_FIRRTL_PASS = 1 + ENABLE_YOSYS_FLOW = 1 endif + +HAMMER_EXTRA_ARGS ?= -p $(TOOLS_CONF) -p $(TECH_CONF) -p $(DESIGN_CONF) $(extra)