From d9858c1dc8ca995014ad08fc3ba8daad2e64a383 Mon Sep 17 00:00:00 2001
From: Duy-Hieu Bui <duyhieu.bui@gmail.com>
Date: Fri, 3 Sep 2021 05:02:36 +0700
Subject: [PATCH] Fixes UART portmap for Arty.

---
 fpga/src/main/scala/arty/HarnessBinders.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
index a8c54dc638..aaec1a8600 100644
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -72,8 +72,8 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
 class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
   (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
-      IOBUF(th.uart_txd_in,  ports.head.txd)
-      ports.head.rxd := IOBUF(th.uart_rxd_out)
+      IOBUF(th.uart_rxd_out,  ports.head.txd)
+      ports.head.rxd := IOBUF(th.uart_txd_in)
     }
   }
 })