diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
index e07aa73daa..a7d2113f81 100644
--- a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
@@ -11,6 +11,7 @@ import testchipip.soc.{OBUS}
 
 // Simple design which exposes a second serial-tl port that can connect to another instance of itself
 class SymmetricChipletRocketConfig extends Config(
+  new testchipip.soc.WithChipIdPin ++                               // Add pin to identify chips
   new chipyard.harness.WithSerialTLTiedOff(tieoffs=Some(Seq(1))) ++ // Tie-off the chip-to-chip link in single-chip sims
   new testchipip.serdes.WithSerialTL(Seq(
     testchipip.serdes.SerialTLParams(                               // 0th serial-tl is chip-to-bringup-fpga
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index aeaec1c776..11fa670d70 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -254,8 +254,8 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
 
 //TODO: Set with chipId argument to harness binder, hardcoding is temporary hack
 class WithDriveChipIdPin extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: ChipIdPort) => {
-    port.io := 0.U
+  case (th: HasHarnessInstantiators, port: ChipIdPort, chipId: Int) => {
+    port.io := chipId.U
   }
 })